PC/104TM STACKABLE SYNCHRO/RESOLVER/LVDT TRACKING …support.bentech-taiwan.com/ccc/pc104.pdf ·...
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Actual Size, True 16 Bit Data Bus, ISOLATED TOO! ~~~~ FEATURES ~~~~ q Dir Dir Dir Dir Direct ect ect ect ect Synchro, Resolver and LVDT Inputs Inputs Inputs Inputs Inputs q Quad Channel Quad Channel Quad Channel Quad Channel Quad Channel Solid State Input Modules q Transformer Isolated Models, q No external conditioning or components req'd. q Wide band ide band ide band ide band ide band 47-1K hz. Reference Inputs, Model options to 10Khz. q PC/104 TM Form-Factor, Stack through q True 16 Bit Address Decode q True 16 Bit "Word Level" Data Bus q Bus/Stack Powered Std. q True card level accuracy and test data. q Auto Handshake, no need to Inhibit Converters q BIT/Fault Output Status, w/Loss detect q Forced Angle Test Mode For Self Test DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION The PC104 Series” are 3 and 4 Chan- nel PC/104 and compatible synchro, re- solver, and LVDT/RVDT to digital con- verters, employing type 2 ratiometric track- ing converters specifically suited for high performance embedded applications. They will accept any group of upto 4 individual, 3-wire Sync Sync Sync Sync Sync hr hr hr hr hr o o o, or 4-wire Re- Re- Re- Re- Re- solv solv solv solv solv er er er er er inputs, or 2-4 wir or 2-4 wir or 2-4 wir or 2-4 wir or 2-4 wir e L e L e L e L e L VDT/R VDT/R VDT/R VDT/R VDT/R VDT VDT VDT VDT VDT inputs inputs inputs inputs inputs; over a frequency range of 50Hz. 50Hz. 50Hz. 50Hz. 50Hz. to 10KHZ to 10KHZ to 10KHZ to 10KHZ to 10KHZ., and convert them into 10-16 bit words of virtually jitter-and lag free, natural binary data representing the in- put signals absolute physical position. Data is addressable in a single w single w single w single w single w or or or or or d 16 d 16 d 16 d 16 d 16 bit f bit f bit f bit f bit f or or or or or ma ma ma ma ma t t t over the PC/104 TM stack-bus. Data made available to the bus is con- tinuously updated (tracking) without in- terruption; output data is accurate, mono- data is accurate, mono- data is accurate, mono- data is accurate, mono- data is accurate, mono- tonic tonic tonic tonic tonic , , , and al and al and al and al and al w w w a a a ys fr ys fr ys fr ys fr ys fr esh esh esh esh esh up to the maxi- mum tracking rate of the converter. For or or or orced ced ced ced ced Test Mode: est Mode: est Mode: est Mode: est Mode: All modules include a force angle test mode for self-test to excersize the con- verters for module checks following PC/104 TM STACKABLE SYNCHRO/RESOLVER/LVDT TRACKING INPUT MODULES power-ups. 3 seperate test-to angles are provided on 3 channel isolated models, and a single test-to 30 degree angle is provided on 4 channel units. The forced test mode may be activated by setting bits SD0/SD1 in the control word, once activated the converters in- ternally switch their inputs from the field I/O and instead insert fixed analog test angles for validation, when switching to or from the forced angle test mode, the user can either wait the specified settling time rated for those converters (20 to 300msec.), or monitor fault/BIT status bits as a ready indicator. Test within .15 de- grees. Built-In-T Built-In-T Built-In-T Built-In-T Built-In-Test/Loss/F est/Loss/F est/Loss/F est/Loss/F est/Loss/Fault Detect Sta ault Detect Sta ault Detect Sta ault Detect Sta ault Detect Status tus tus tus tus Additionally, a single Sta Sta Sta Sta Sta tus tus tus tus tus W W W or or or or or d d d is provided to report the BIT/F BIT/F BIT/F BIT/F BIT/F ault ault ault ault ault sta sta sta sta sta tus tus tus tus tus of each independent channel, indication include loss of signal, loss of reference, overspeed/accel and malfunction alert. Dir Dir Dir Dir Direct F ect F ect F ect F ect Field ield ield ield ield Volta olta olta olta oltage Inputs e Inputs e Inputs e Inputs e Inputs No e No e No e No e No e xter xter xter xter xter nal tr nal tr nal tr nal tr nal tr ansf ansf ansf ansf ansf or or or or or mer mer mer mer mer s, s, s, s, s, modules or signal conditioners are r r r equir equir equir equir equir ed ed ed ed ed. The syn- chro/resolver and LVDT converters used feature inter inter inter inter inter nal nal nal nal nal solid-state or T T T r r r ansf ansf ansf ansf ansf or or or or or mer mer mer mer mer Isola Isola Isola Isola Isola ted ted ted ted ted Scott T’s that accept dir dir dir dir dir ect f ect f ect f ect f ect f ield ield ield ield ield v v v olta olta olta olta olta g g g e inputs e inputs e inputs e inputs e inputs. T T T r r r ansf ansf ansf ansf ansf or or or or or mer mer mer mer mer Isola Isola Isola Isola Isola tion tion tion tion tion is offered for all all all all all the reference and signal input lines, This This This This This completel completel completel completel completel y isola y isola y isola y isola y isola tes the car tes the car tes the car tes the car tes the car d and ef d and ef d and ef d and ef d and ef f f f ec- ec- ec- ec- ec- ti ti ti ti ti v v v el el el el el y the w y the w y the w y the w y the w hole computer fr hole computer fr hole computer fr hole computer fr hole computer fr om all f om all f om all f om all f om all f ield ield ield ield ield wir wir wir wir wir ing ing ing ing ing , , , elimina elimina elimina elimina elimina ting concer ting concer ting concer ting concer ting concer ns o ns o ns o ns o ns o v v v er; er; er; er; er; troublesome ground loops, ground in- troublesome ground loops, ground in- troublesome ground loops, ground in- troublesome ground loops, ground in- troublesome ground loops, ground in- duced noise duced noise duced noise duced noise duced noise , , , dif dif dif dif dif f f f er er er er er ing potentials, ing potentials, ing potentials, ing potentials, ing potentials, g g g g g r r r ound ound ound ound ound interjected spik interjected spik interjected spik interjected spik interjected spik es, es, es, es, es, and ghostl and ghostl and ghostl and ghostl and ghostl y f y f y f y f y f ield noise ield noise ield noise ield noise ield noise tha tha tha tha tha t so fr t so fr t so fr t so fr t so fr equentl equentl equentl equentl equentl y tak y tak y tak y tak y tak es do es do es do es do es do wn, wn, wn, wn, wn, and/or and/or and/or and/or and/or cor cor cor cor cor r r r upts the oper upts the oper upts the oper upts the oper upts the oper a a a tion of tion of tion of tion of tion of , , , entir entir entir entir entir e systems. e systems. e systems. e systems. e systems. Transformer isolated units, facilitate ~~~~ APPLICATIONS ~~~~ q q q q q Synchro/Resolver Test Sets q q q q q Embedded Display and Inst. Sets q q q q q OEM Mobile Antenna Gear q q q q q Marine Gyro/GPS Systems q q q q q Automated Guided Vehicles q q q q q Drones, Radars, Weather Inst's. q q q q q Surveying & Mapping Apparatus
Transcript of PC/104TM STACKABLE SYNCHRO/RESOLVER/LVDT TRACKING …support.bentech-taiwan.com/ccc/pc104.pdf ·...
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Actual Size, True 16 Bit Data Bus, ISOLATED TOO!
~~~~ FEATURES ~~~~q DirDirDirDirDirectectectectect Synchro, Resolver and LVDT InputsInputsInputsInputsInputs
q Quad Channel Quad Channel Quad Channel Quad Channel Quad Channel Solid State Input Modules
q Transformer Isolated Models,
q No external conditioning or components req'd.
q WWWWWide band ide band ide band ide band ide band 47-1K hz. Reference Inputs, Model options to 10Khz.q PC/104TM Form-Factor, Stack through
q True 16 Bit Address Decode
q True 16 Bit "Word Level" Data Bus
q Bus/Stack Powered Std.
q True card level accuracy and test data.
q Auto Handshake, no need to Inhibit Converters
q BIT/Fault Output Status, w/Loss detect
q Forced Angle Test Mode For Self Test
DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION The PC104 Series” are 3 and 4 Chan-nel PC/104 and compatible synchro, re-solver, and LVDT/RVDT to digital con-verters, employing type 2 ratiometric track-ing converters specifically suited for highperformance embedded applications. They will accept any group of upto 4individual, 3-wire SyncSyncSyncSyncSynchrhrhrhrhrooooo, or 4-wire Re-Re-Re-Re-Re-solvsolvsolvsolvsolver er er er er inputs, or 2-4 wiror 2-4 wiror 2-4 wiror 2-4 wiror 2-4 wire Le Le Le Le LVDT/RVDT/RVDT/RVDT/RVDT/RVDTVDTVDTVDTVDTinputsinputsinputsinputsinputs; over a frequency range of 50Hz.50Hz.50Hz.50Hz.50Hz.to 10KHZto 10KHZto 10KHZto 10KHZto 10KHZ., and convert them into 10-16bit words of virtually jitter-and lag free,natural binary data representing the in-put signals absolute physical position.
Data is addressable in a single wsingle wsingle wsingle wsingle wororororord 16d 16d 16d 16d 16bit fbit fbit fbit fbit fororororormamamamamattttt over the PC/104TM stack-bus.Data made available to the bus is con-tinuously updated (tracking) without in-terruption; output data is accurate, mono-data is accurate, mono-data is accurate, mono-data is accurate, mono-data is accurate, mono-tonictonictonictonictonic,,,,, and al and al and al and al and alwwwwwaaaaays frys frys frys frys fresh esh esh esh esh up to the maxi-mum tracking rate of the converter.
FFFFForororororced ced ced ced ced TTTTTest Mode:est Mode:est Mode:est Mode:est Mode: All modules include a force angle testmode for self-test to excersize the con-verters for module checks following
PC/104TM STACKABLESYNCHRO/RESOLVER/LVDTTRACKING INPUT MODULES
power-ups. 3 seperate test-to angles areprovided on 3 channel isolated models,and a single test-to 30 degree angle isprovided on 4 channel units. The forced test mode may be activatedby setting bits SD0/SD1 in the controlword, once activated the converters in-ternally switch their inputs from the fieldI/O and instead insert fixed analog testangles for validation, when switching toor from the forced angle test mode, theuser can either wait the specified settlingtime rated for those converters (20 to300msec.), or monitor fault/BIT status bitsas a ready indicator. Test within .15 de-grees.
Built-In-TBuilt-In-TBuilt-In-TBuilt-In-TBuilt-In-T est/Loss/Fest/Loss/Fest/Loss/Fest/Loss/Fest/Loss/Fault Detect Staault Detect Staault Detect Staault Detect Staault Detect Statustustustustus Additionally, a single StaStaStaStaStatus tus tus tus tus WWWWWorororororddddd isprovided to report the BIT/FBIT/FBIT/FBIT/FBIT/Faultaultaultaultault stastastastastatustustustustusof each independent channel, indicationinclude loss of signal, loss of reference,overspeed/accel and malfunction alert.
DirDirDirDirDir ect Fect Fect Fect Fect Field ield ield ield ield VVVVVoltaoltaoltaoltaoltaggggge Inputse Inputse Inputse Inputse InputsNo eNo eNo eNo eNo exterxterxterxterxternal trnal trnal trnal trnal transfansfansfansfansfororororormermermermermers,s,s,s,s, modules orsignal conditioners are rrrrrequirequirequirequirequirededededed. The syn-chro/resolver and LVDT converters used
feature interinterinterinterinternal nal nal nal nal solid-state or TTTTTrrrrransfansfansfansfansfororororormermermermermerIsolaIsolaIsolaIsolaIsolatedtedtedtedted Scott T’s that accept dirdirdirdirdirect fect fect fect fect fieldieldieldieldieldvvvvvoltaoltaoltaoltaoltaggggge inputse inputse inputse inputse inputs.TTTTTrrrrransfansfansfansfansfororororormermermermermer IsolaIsolaIsolaIsolaIsolationtiontiontiontion is offered for allallallallallthe reference and signal input lines, ThisThisThisThisThiscompletelcompletelcompletelcompletelcompletely isolay isolay isolay isolay isolates the cartes the cartes the cartes the cartes the card and efd and efd and efd and efd and effffffec-ec-ec-ec-ec-tititititivvvvvelelelelely the wy the wy the wy the wy the whole computer frhole computer frhole computer frhole computer frhole computer from all fom all fom all fom all fom all fieldieldieldieldieldwirwirwirwirwir inginginginging,,,,, elimina elimina elimina elimina eliminating concerting concerting concerting concerting concerns ons ons ons ons ovvvvver;er;er;er;er;troublesome ground loops, ground in-troublesome ground loops, ground in-troublesome ground loops, ground in-troublesome ground loops, ground in-troublesome ground loops, ground in-duced noiseduced noiseduced noiseduced noiseduced noise,,,,, dif dif dif dif diffffffererererering potentials,ing potentials,ing potentials,ing potentials,ing potentials, g g g g grrrrroundoundoundoundoundinterjected spikinterjected spikinterjected spikinterjected spikinterjected spikes,es,es,es,es, and ghostl and ghostl and ghostl and ghostl and ghostly fy fy fy fy field noiseield noiseield noiseield noiseield noisethathathathathat so frt so frt so frt so frt so frequentlequentlequentlequentlequently taky taky taky taky takes does does does does down,wn,wn,wn,wn, and/or and/or and/or and/or and/orcorcorcorcorcorrrrrrupts the operupts the operupts the operupts the operupts the operaaaaation oftion oftion oftion oftion of,,,,, entir entir entir entir entire systems.e systems.e systems.e systems.e systems. Transformer isolated units, facilitate
~~~~ APPLICATIONS ~~~~
q q q q q Synchro/Resolver Test Sets
q q q q q Embedded Display and Inst. Sets
q q q q q OEM Mobile Antenna Gear
q q q q q Marine Gyro/GPS Systems
q q q q q Automated Guided Vehicles
q q q q q Drones, Radars, Weather Inst's.
q q q q q Surveying & Mapping Apparatus
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Envir onmental Specifications:Temperature: see chart & model #Humidity : 0 to 95% (non-condensing)Wheight: 4-8 ounces = 1-4 Channel
Vibration : 3.5 mm. 5-9Hz. : 1.0 G 9 - 150Hz.Shock: 15 g's for 11 msec.
densities upto 4 channels per card, andseparate reference inputs are provided foreach channel; allowing differing referencesources to be used with a single card, andchannel to channel and channel to busisolation exceeding 500VDC.
Solid State input units are for price-para-mount applications, offering densities upto4 channels per module, with separate ref-erence inputs for each channel, and com-mon mode rejection exceeding 70 db..Because only "whole complete convert-ers" are used throughout; direct field in-put voltages are facilitated and neitherexternal components, conditioning, or fieldcomponent selections/changes, are re-quired.
Accuracy, performance, anddynamiccharacteristics, are specified andspecified andspecified andspecified andspecified andtested inctested inctested inctested inctested inclusilusilusilusilusivvvvve of the we of the we of the we of the we of the whole PC/104hole PC/104hole PC/104hole PC/104hole PC/104TMTMTMTMTM
assembassembassembassembassemblllllyyyyy,,,,, and printed test data is provided,and maintained, on all units.
Maximum versatility has been em-ployed on the PC104 Series' products toassure the universal compatibility in ad-dressing, timing, system, and specificcomputer harharharharhardddddwwwwwararararare and softwe and softwe and softwe and softwe and softwararararare inde-e inde-e inde-e inde-e inde-pendence.pendence.pendence.pendence.pendence. The PC104 Series cards are configuredwith a full 16 bit range of jumper-plugselectable I/O addressing . The interfaceis a solidly-reliablesolidly-reliablesolidly-reliablesolidly-reliablesolidly-reliable, high-speed, true 1616161616bit "Wbit "Wbit "Wbit "Wbit "Wororororord-Led-Led-Led-Led-Levvvvvel"el"el"el"el" register access. Sim-ply address the I/O; and read the data.
Because 'auto-handshakingauto-handshakingauto-handshakingauto-handshakingauto-handshaking is providedon-board, to prto prto prto prto preeeeevvvvvent fent fent fent fent false ralse ralse ralse ralse reads,eads,eads,eads,eads, and and and and and atrue 16 bit data bus is used; there is nonononononeed to emploneed to emploneed to emploneed to emploneed to employ any any any any any ady ady ady ady additional softwditional softwditional softwditional softwditional softwararararareeeeesteps to inhibit the converters, or manipu-lating 8 bit bytes; and the user is assuredonly the most current, valid and "dynamic"data is presented to the bus.
Softw Softw Softw Softw Softwararararare e e e e code fragments that may beused as drdrdrdrdriiiiivvvvvererererersssss, ar ar ar ar are pre pre pre pre prooooovidedvidedvidedvidedvided in C, andsimple inport/outport commands are usedin assembly. In addition, a C writtenDemonstration program is provided forOut-Of-The-Box testing, scaling, and off-setting; without any user programmingrequired, and includes source code .
PC104's are available in: commercialOoC to +70oC, industrial -40OC to +85OC.
SNOITACIFICEPS SNOITACIFICEPS SNOITACIFICEPS SNOITACIFICEPS SNOITACIFICEPSstiB01 stiB01 stiB01 stiB01 stiB01 stiB21 stiB21 stiB21 stiB21 stiB21 stiB41 stiB41 stiB41 stiB41 stiB41 stiB61 stiB61 stiB61 stiB61 stiB61
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Copyright C 1995 Computer Conversions Corp. PC/104TM is a Trademark of the PC/104 Consortium
ASSEMBLY CODE FOR READING REGISTERS
MOV DX,Port_address in Hex ; place address of port ; in DX registerINW AX,DX ; place value in AX register
BLOCK DIAGRAM PC/104
Notes:1) All shields to go direct to Earth Ground on the com- puter side only.2) To reverse direction of rotation swap S1 with S3 or invert data in software.3) S4 is not used on Synchro units.
SOFTWARE SUPPORTAll cards shipped with Soft-ware Packs having a DemoProgram for Out-Of-The-BoxTesting & Scaling, and Self-Test features etc. with SourceCode provided for extraction.Code fragments for use asDrivers provided in C, As-sembly uses inport/outportsee below. NT Drivers areExtra.
PAMSSERDDASEIRES401CP PAMSSERDDASEIRES401CP PAMSSERDDASEIRES401CP PAMSSERDDASEIRES401CP PAMSSERDDASEIRES401CP
XEH XEH XEH XEH XEH stiBsserddA stiBsserddA stiBsserddA stiBsserddA stiBsserddA retrevnoC retrevnoC retrevnoC retrevnoC retrevnoC .nahC .nahC .nahC .nahC .nahC#nhC
tceleS tceleS tceleS tceleS tceleS 1A2A3A4A 1A2A3A4A 1A2A3A4A 1A2A3A4A 1A2A3A4A noitcnuF noitcnuF noitcnuF noitcnuF noitcnuF
h00 0 0 0 0 LENNAHCDAERATAD
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/tamrofXEH /tamrofXEH /tamrofXEH /tamrofXEH /tamrofXEHnoitatneserpeR 00000 33333 00000 00000
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stiBsserddA stiBsserddA stiBsserddA stiBsserddA stiBsserddA 5151515151 4141414141 3131313131 2121212121 1111111111 0101010101 99999 88888 77777 66666 55555 44444 33333 22222 11111 NNNNN
SEIRES401CProfPAMTIBDROWSUTATS SEIRES401CProfPAMTIBDROWSUTATS SEIRES401CProfPAMTIBDROWSUTATS SEIRES401CProfPAMTIBDROWSUTATS SEIRES401CProfPAMTIBDROWSUTATS
BSLstiBataDsutatSO/IBSM BSLstiBataDsutatSO/IBSM BSLstiBataDsutatSO/IBSM BSLstiBataDsutatSO/IBSM BSLstiBataDsutatSO/IBSM
5151515151 4141414141 3131313131 2121212121 1111111111 0101010101 99999 88888 77777 66666 55555 44444 33333 22222 11111 00000
ksaM,desutoN=X=51-4stiB
ssoL/TIB/tluaF3lennahCtseT-ni-tliuB=0
ssoL/TIB/tluaF2lennahCtseT-ni-tliuB=0
ssoL/TIB/tluaF1lennahCtseT-ni-tliuB=0
ssoL/TIB/tluaF0lennahCtseT-ni-tliuB=0
,seireS401CP:SNOITANIMRETNIP ,seireS401CP:SNOITANIMRETNIP ,seireS401CP:SNOITANIMRETNIP ,seireS401CP:SNOITANIMRETNIP ,seireS401CP:SNOITANIMRETNIP
NIP NIP NIP NIP NIP dradnatS dradnatS dradnatS dradnatS dradnatS NIP NIP NIP NIP NIP dradnatS dradnatS dradnatS dradnatS dradnatS
1 LR ecnerefeR ecnerefeR ecnerefeR ecnerefeR ecnerefeR0#lennahC
71 LR ecnerefeR ecnerefeR ecnerefeR ecnerefeR ecnerefeR2#lennahC2 HR 81 HR
3 1S
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slangiS slangiS slangiS slangiS slangiS2#lennahC
4 2S 02 2S
5 3S 12 3S
6 4S 22 4S
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8 dnG dnuorG 42 dnG dnuorG
9 LR ecnerefeR ecnerefeR ecnerefeR ecnerefeR ecnerefeR1#lennahC
52 LR ecnerefeR ecnerefeR ecnerefeR ecnerefeR ecnerefeR3#lennahC01 HR 62 HR
11 1S
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72 1S
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21 2S 82 2S
31 3S 92 3S
41 4S 03 4S
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61 .dnG dnuorG 23 dnG dnuorG
7043-906#YELSNArotcennoC3J)1:SETON
8-783201#PMA:gnisuoH:eriW:ETAM3J)2)nobbiresut’noD(,3-843201ro2-843201#PMA:sniP.
.stinutupnietatsdilosnodesutontuptuoyticoleV)3
reffiD.losIslennahC4,sihtesustinUdetalosIlennahC3)4
-
Cable Belden 8777 or Equal
CABLE DRAWING Example: Model; PC104-B4B4B5-X-1 Includes:
1 PC104 Card, Populated with: 2 - 14 Bit S-D Converters 115/90V. @ 400Hz. 1- 14 Bit S-D Converter 115/90V. @ 60 Hz.
All Reference and Signal inputs are Trans-former Isolated, 0oC to 70 oC oper. temp.
Your Local CCC Representative is:
PC104TM SERIESSYNCHRO/RESOLVER InputsMODEL SELECTION GUIDE
STINU401CPROFEDIUGNOITCELESLEDOM STINU401CPROFEDIUGNOITCELESLEDOM STINU401CPROFEDIUGNOITCELESLEDOM STINU401CPROFEDIUGNOITCELESLEDOM STINU401CPROFEDIUGNOITCELESLEDOM
:ledoM :ledoM :ledoM :ledoM :ledoM 401CP 401CP 401CP 401CP 401CP ----- 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 5B 5B 5B 5B 5B 00000 ----- XXXXX VVVVV ----- 11111
aelbatees:abelbatees:b
ba ba ba ba .pmeT1-.mmoC3-dednetxE
0.HC 1.HC 2.HC 3.HC
stinudetalosIremrofsnarTrofX-tresnI
.ylnostinUdetalosIremrofsnarTrofnoitpostuptuoyticoleVCDrofV-tresnI
DNAEPYTRETREVNOCTCELES)a DNAEPYTRETREVNOCTCELES)a DNAEPYTRETREVNOCTCELES)a DNAEPYTRETREVNOCTCELES)a DNAEPYTRETREVNOCTCELES)aEDOCNOITULOSER
STIB STIB STIB STIB STIB 6161616161 4141414141 2121212121 0101010101
LATIGIDOTORHCNYS LATIGIDOTORHCNYS LATIGIDOTORHCNYS LATIGIDOTORHCNYS LATIGIDOTORHCNYS
edoC AAAAA BBBBB CCCCC DDDDD
LATIGIDOTREVLOSER LATIGIDOTREVLOSER LATIGIDOTREVLOSER LATIGIDOTREVLOSER LATIGIDOTREVLOSER
edoC EEEEE FFFFF GGGGG HHHHH
EDIUGLEDOM.TXETSEUQERSREHTOLLA
)#EDOCTRESNI(SLANGISTCELES)b )#EDOCTRESNI(SLANGISTCELES)b )#EDOCTRESNI(SLANGISTCELES)b )#EDOCTRESNI(SLANGISTCELES)b )#EDOCTRESNI(SLANGISTCELES)b
ECNEREFEREGATLOV
LANGISSLEVEL
YCNEUQERFZTREHNI
SIHTTRESNIEDOC
CAV62 L-L.V8.11 .zH004 1
CAV62 L-L.V8.11 .zHK6.2 2
CAV62 L-L.V62 .zH004 3
CAV511 L-L.V09 .zH004 4
CAV511 L-L.V09 .zH06 5
EDIUGLEDOM.D’TXETSEUQERSREHTOLLA
