Particle pixel detectors in high-voltage CMOS technology

1IWLC 2010 – Ivan Peric

Particle pixel detectors in high-voltage CMOS technology

Ivan Peric

University of Heidelberg


Pixel detector in HV CMOS technology

• Monolithic pixel sensor

• 100% fill-factor

• In-pixel CMOS signal processing

• Excellent SNR (seed 21 μm-pixel SNR for high energy betas > 80)

• Allows thinning below 50 μm without signal decrease

• Good timing properties (theoretically 40 ps signal collection time)

• Radiation hard (tested to 50 MRad (x-rays) and 1015 neq (protons))

• Not expensive (standard technology used, wafer run costs 98 k€)


The detecor stucture

Deep n-well

Pixel electronics in the deep n-well

Based on twin-well structure

P-substrate

NMOS transistorin its p-well

PMOS transistor

The CMOS signal processing electronics are placed inside the deep-n-well. PMOS are placed directly inside n-well, NMOS transistors are situated in their p-wells that are embedded in the n-well as well.


“Smart” diode array

Deep n-well


Based on twin-well structure

P-substrate


PMOS transistor

Smart diode


“Smart” diode array in HV CMOS technology

P-substrate


PMOS transistor

Particle

E-field

14 μm at 100V bias (MIP: 1080e from depleted layer)

Deep n-well


High voltage deep n-well used


Signal detection

ComparatorCR-RC

CSA

N-well

AC coupling

3.3 V

-50 V

P-substrate


Strong points

• 1) CMOS in-pixel electronics

• 2) Good SNR

• 3) Fast signal collection– Theoretically 40ps

• 4) Thinning possible– Since the charge collection is limited to the chip surface, the sensors can be thinned

• 5) Price and technology availability– Standard technology without any adjustment is used

– Many industry relevant applications of HV CMOS technologies assure their long tern availability

• 6) High tolerance to non-ionizing radiation damage – High drift speed

– Short drift path

• 7) High tolerance to ionizing radiation– Deep submicron technology

– Radiation tolerant design can be used

– Radiation tolerant PMOS transistors can be used (in contrast to MAPS with high-resistance substrate)


Drawbacks

• 1) Capacitive feedback– must be taken into account when the pixels are designed and simulated.

– In some cases the capacitive feedback can be of use, for instance if provides a feedback capacitance for the charge sensitive amplifier.

– Despite some limitations, we can implement the majority of important pixel circuits in CMOS, like the charge sensitive amplifier, shaper, tune DAC, SRAM…

– CMOS logic gates in pixels should be avoided – current mode logic can be used instead

• 2) Relatively large size of the collecting electrode– However the high voltage deep n-well has relatively small area capacitance.

– Typical values for the total n-well capacitance are from 10fF (small pixels and simple pixel electronics) to 100fF larger CMOS pixels.

– Despite of the capacitance, we achieve excellent SNR values.


HV deep N-well

P-Well

Depleted

P-substrate

Pixel i Pixel i+1

14 m @ 100V (1080 e)

Not depleted


Project overview

First chip – CMOS pixelsHit detection in pixels

Binary ROPixel size 55x55μm

Noise: 60eMIP seed pixel signal 1800 e

Time resolution 200ns

CCPD1 ChipBumpless hybrid detector

Based on capacitive chip to chipsignal transfer

Pixel size 78x60μmRO type: capacitive

Noise: 80eMIP signal 1800e

CCPD2 ChipEdgeless CCPD

Pixel size 50x50μmNoise: 30-40e

Time resolution 300nsSNR 45-60

PM1 ChipPixel size 21x21μm

Frame mode readout4 PMOS pixel electronics

128 on chip ADCsNoise: 90e

Test-beam: MIP signal 2200e/1300eEfficiency > 85% (timing problem)

Spatial resolution 7μmUniform detection

PM2 ChipNoise: 25e, Seed MIP SNR ~ 100

Test beam plannedIrradiations of test pixels60MRad – SNR 22 at 10C (CCPD1)

1015neq SNR 50 at 10C (CCPD2)

Frame readout - monolithicBumpless hybrid detector

1.5 mm

Readout chip (CAPPIX)

Sensor chip (CAPSENSE)

Power supplyand cont. signalsfor the sensor

Power supplyand cont. signalsfor the readout chip

Testbeam DESY

Testbeam CERN

EUDET telescope

DUT

DUT

0 5 10 15 20 25 30 35 40 45 500

100

200

300

400

500

600

700

800

seed p ix e l3 M S P

w h o le c lu s te r

S N R

coun

t

MIP spectrum (CERN SpS - 120GeV protons)

Testchip

PCB

PCB with PPGA and analog supply voltage regulators/DACs

60V bias voltage (3 batteries)

Trigger ID

USB connector

2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5T

T^ 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Efficiency

Purity

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 20 40 60 80 100 1200

10

20

30

40

50

60

effic iencyeffic iency

pixel coordinate x

pix

el

coo

rdin

ate

yEfficiency

Seed and cluster cut [SNR]

2.7

mm

ADC channel

Pixel matrix

ComparatorCR-RC

CSA

N-well

AC coupling

3.3 V

-50 V

P-substrate

0 100 200 300 400 500 600 700 8000

20

40

60

80

100

120

140

160

180

200

220Sr-90, Regular pixel, 55V

Num

ber

of h

its

ToT/Clk

MIP Signal: 2000e/1.17 = 1710 eLow energy peak:1.080 e

a)b)

0 100 200 300 400 500 600 700 8000,0

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

1,0

1,1

Regular pixel, 55V

Fe-55 Sr-90

~hi

t pr

obab

ility

ToT/Clk

Sensor pixels

Readout electrodes

Pads for power and signals


Experimental results

• Measurements with HVPixelM2


HVPixelM2 chip2

.7 m

m

ADC channel

Pixel matrix

20IWLC 2010 – Ivan PericADC

Row

-contro

l („Sw

itcher“)

Digital output

10000001000

Pixel size: 21 X 21 m Matrix size: 2.69 X 2.69 mm (128 X 128) Possible readout time/matrix: ~ simulated 40 s (tested 160 s/matrix) ADC: 8 – Bit Measured power: 3 μW/pixel analog 8 μW/pixel digital at 160 s/matrix (can be reduced to 2.3 μW/pixel for 40 s/matrix by lowering the digital voltage and resizing the flip flops)

8 LVDS

Counter

Amplifier

Comparator

Latch

Ramp gen.

HVPixelM2 chip

Pixel matrix


Noise measurement and 55Fe spectrum (HVPixelM2)

50 60 70 80 90 100 110 120 130 140 150 160 1700.0

0.2

0.4

0.6

0.8

1.0

~

nu

mb

er o

f sig

na

ls

ADU

55Fe, 1 pixel, 76 ADU, (1660e) Noise 1.1 ADU (24e)

Noise: 24eDKS used

55Fe1660e


High-energy beta spectra (HVPixelM2)

0 1000 2000 3000 4000 5000 6000 7000 80000.0

0.2

0.4

0.6

0.8

1.0

~n

um

be

r o

f sig

na

ls

signal amplitude [e]

Noise, 1 pixel (21e)

60Co, 1 pixel (1700e)

60Co, 2 pixels (1800e)



0 1000 2000 3000 4000 5000 6000 7000 80000.0

0.2

0.4

0.6

0.8

1.0

~n

um

be

r o

f sig

na

lssignal amplitude [e]


22Na, 1 pixels (1900e)




60Co betas (about 10% higher signals than MIPs)Seed signal: 1700eCluster signal: 2250eNoise: 21eSeed SNR: 81Cluster signal/seed noise: 107

55Na betasSeed signal: 1900eCluster signal: 3300eNoise: 21eSeed SNR: 90Cluster signal/seed noise: 157

Estimated MIP seep pixel SNR 70


0 2000 4000 6000 8000 10000 120000.0

0.2

0.4

0.6

0.8

1.0

n

um

be

r o

f sig

na

ls

signal amplitude [e]



High-energy beta spectra (HVPixelM2)


Radiation tolerance

• We expect a good tolerance to non-ionizing damage thanks to the small drift distance and high drift speed in the depleted area. Due to high dopant density the type inversion should occur at higher fluencies.

• Concerning the ionizing damage, we can benefit from the properties of the used deep submicron CMOS technology. In contrast to the most of the MAPS, we can rely on PMOS transistors inside pixels that are more radiation tolerant than NMOST.


Irradiation with protons (1015 neq/cm2, 300 MRad)

0.00 0.02 0.04 0.06 0.08 0.100.0

0.2

0.4

0.6

0.8

1.0

~ n

um

be

r o

f sig

na

ls

signal amplitude [V]

RMS Noise 0.5mv (12e)

55Fe 70mV (1660e)Room temperature

0.00 0.02 0.04 0.06 0.08 0.100.0

0.2

0.4

0.6

0.8

1.0

~n

um

be

r o

f sig

na

lssignal amplitude [V]

RMS Noise, 2.8mv (77e)

55Fe, 60mV (1660e)Temperature 10C

Irradiated with protons to 1015neq

55Fe spectrum and RMS noiseNot irradiatedRoom temperature RMS Noise 12 e

55Fe spectrum, RMS noiseIrradiated10C RMS Noise 77 e


Irradiation with protons (1015 neq/cm2, 300 MRad)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80.0

0.2

0.4

0.6

0.8

1.0

~

nu

mb

er

of

sig

na

ls

signal amplitude [V]

RMS Noise (40e)

55Fe x-ray spectrum (Peak: 1660e)

22Na beta spectrum (Maximum: 3750e)

SNR = 93


Summary

• We have developed a new pixel sensor structure (smart diode array) for high energy physics that can be implemented in a high voltage CMOS technology.

• The sensor has 100% fill-factor and can have in-pixel electronics implemented with p- and n-channel transistors.

• We have implemented the sensor structure in various variants:

• 1) Sensor with in-pixel hit detection and sparse readout,

• 2) Sensor with fast rolling-shutter readout and simple pixel electronics,

• 3) Hybrid sensor based on capacitive chip to chip signal transfer.

• We measure excellent SNR in all three cases.

• We have done a test-beam measurement with the first version of the frame readout detector with good results.

• The SNR of the second chip version is four times better.

• Excellent seed pixel SNR of almost 100 has been achieved.

• We have irradiated the chips with neutrons, protons and x-rays to test radiation tolerance.

• After irradiation with protons up to very high fluence 1015 neq/cm2 and dose 300MRad, we have still very large SNR (>40) for high energy beta particles at nearly room temperatures (10C).


Outlook

• The engineering run in the used technology costs only 98k €

• By proper arrangement of the dices, we can obtain long monolithic multi-reticle sensors with 12cm length and 1cm width

• We would have 8 such modules per wafer and one engineering run could give us up to 48 modules

• We are confident that the sensor technology has achieved such a degree of maturity so that it can be considered as a good candidate for future particle physics experiments


Multi-reticle module

Reticle1

Chip1

Pads

Chip to chip connections

Chip to reticle edge distance = 80 um

Chip2

Chip1

Chip2

Reticle2

2.0 cm

Module

Very long low-cost pixel modules with (almost) no insensitive area can be producedReticle-reticle connections can be made easily by wire bondingInstead of wire-bonding, an extra metal layer can be used as well


Multi-reticle module

Carrier

Module (length. 12 cm, width 1cm, the figure is not scaled)

Pads for power and IO signals

chip to chip connections

Chip (reticle 3)

Interaction region

Large sensitive area without material

Chip (reticle 2)

Very low-mass only silicon modules are possible as well (similar to DEPFET module for Belle II)


SDA long module

12 cm (one half of the module shown)

1 cm


Sensor types

• Frame RO type 1: (for ILC) (Scaling of the existing PM design)

Half module size 1x6cm Pixel size 40x40μm Pixels 250x1500 RO time 80μs/matrix Resolution 8bit/pixel Power 900mW/module (150mW/cm2) Data output width 96 bits @ 400Mbit

• Frame RO type 2 (in-pixel DKS and binary readout): (for Belle II, ILC...)(new Design)

Half module size 1x6cm Pixel size 40x40μm Pixels 250x1500 RO time 10μs/matrix Resolution 1bit/pixel Power 900mW/module (150mW/cm2) Data output width 96 bits @ 400Mbit

• Continuous RO type (in-pixel hit-detection): (for LHC, Belle II...) (Scaling of the existing design plus new readout periphery block)

Half module size 1x6cm Pixel size 40x80μm Pixels 250x750 Time resolution: 50-100ns Power 1000mW/module (167mW/cm2)


Sparse RO typ

Pixel matrix (250x250)

RO

RO

Pixel matrix (250x250)64

2cm - chip

1.2cm

6cm - moduleDO DO

Wire bond

chip1 chip2 chip3


Sparse RO typ

A

FB

C

L

DAC

125 wires

Pixel 1 Pixel 2 Pixel 3

Deep N-Well Deep N-WellDeep N-Well

A

FB

C

L

DAC

125 wires

Deep N-Well Deep N-WellDeep N-Well

350nm: 80μm – 125 lines

180nm: 40μm – 125 lines


Sparse RO typ

col adr,TS

col/row adr,TS

Res

Pix

Wr,RdLIFO

LdHitPriHit

NextData

LdData

PriData

DataOut

Ck

NextHit HitOut

CkHitOutSync

DataOutSync

Hit processing units

Data processing units

Buffers - LIFO

Pixels


Time walk for 5μW pixel amplifier

Y0

(m

V)

M 0(89.99ns)M 0(89.99ns)M 0(89.99ns)

Output of the Pixel amplifier

600e

1200e

1800e


Time walk for 5μW pixel amplifier

Y0

(m

V)

M 0(89.99ns)M 0(89.99ns)M 0(89.99ns)M 0(89.99ns)M 0(89.99ns) M 1(137.4ns, -41.82m V)

Output of the Pixel amplifier

50ns time walk


• Thank you!

Particle pixel detectors in high-voltage CMOS technology

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