IEICE TRANS. ELECTRON., VOL.E85–C, NO.5 MAY 20021079

PAPER Special Issue on Advanced Sub-0.1µm CMOS Devices

Characteristics of MOSFET with Non-overlapped

Source-Drain to Gate

Hyunjin LEE†a), Nonmember, Sung-il CHANG†, Jongho LEE††,and Hyungcheol SHIN†, Regular Members

SUMMARY A MOSFET structure with non-overlappedsource-drain to gate region is proposed to overcome the chal-lenges in sub-0.1 µm CMOS device. Key device characteristicswere investigated by extensive simulation study. Fringing gateelectric field through the dielectric spacer induces inversion layerin the non-overlap region to act as extended S/D region. Elec-trons were induced reasonably under the spacer. Internal physicsand speed characteristics were studied with the non-overlap dis-tance. The proposed structure had good subthreshold slope andDIBL characteristics compared to those of overlapped structure.key words: non-overlap, 50 nm MOSFET, SCE, extendedsource/drain

1. Introduction

Recently, MOSFET’s have been scaled down to sub-50 nm regime [1]. Ultra shallow source/drain (S/D)extension junction depth is inevitable to suppress so-called short channel effect (SCE) while keeping lowS/D parasitic resistance to guarantee current drivabil-ity. It has been reported that the current drivabilityof an MOSFET degrades as the overlap distance ofsource/drain extension to a gate decreases to less than15–20 nm [2]. However, the overlap distance of largerthan 15 nm cannot be applied to sub-50 nm device fab-rication. Therefore, research on the overlap distance inMOSFET design is needed. First, we begin by check-ing the device characteristics when the overlap distanceis negative (non-overlap) in conventional MOSFET’s.Figure 1 shows ID-VDS curves of a conventional 0.3 µmMOSFET with and without LDD region (non overlapdistance: 80 nm), respectively. The device without theLDD has a very low current driving capability due tothe very low electron concentration in the non-overlapregion. Then what will be occurred if the devices shrinkto sub-50 nm regime? It is expected that the electronconcentration under the dielectric spacer will be in-creased due to the scaled-down geometry. From therules of the generalized scaling, electric field intensityincreases as the device physical dimensions scales down,even if the supply voltage is reduced [3]. On the other

Manuscript received September 25, 2001.Manuscript revised January 18, 2002.

†The authors are with KAIST, Yusong-gu, Taejon, 305-701, Korea.

††The author is with Wonkwang University, Iksan, 570-749, Korea.

a) E-mail: hjlee@inca.kaist.ac.kr

Fig. 1 Simulated IV characteristics of conventional 0.3 µmLDD MOSFET with and without LDD. The MOSFET withoutthe LDD has a non-overlapped S/D to gate structure.

hand, the design approach adopting the non-overlapS/D to gate structure can be very useful in designingultra small size MOSFETs, because it has a positiveeffect on the SCE. For the suppression of short channeleffect, MOSFET with electrically induced source/drainextension region has been reported [4].

In this paper, we introduce a MOSFET with non-overlapped source-drain to gate structure to reduce theSCE in further device scaling down. The simulationwas done by using process [5] and device [6] simulators.Advanced physical models are used in device simula-tion.

2. Device Design

Figure 2 shows the schematic cross-section of the MOS-FET which has non-overlapped S/D to a gate structure.The MOSFET has 50 nm n+ poly-Si gate, 2 nm gateoxide and 1 nm buffer oxide under the nitride spacer.Here Lno represents the non-overlap distance betweenS/D and gate. The buffer oxide is used to relieve pos-sible problems from stress between the spacer and thesubstrate, and the process. Without the buffer oxideunder the spacer, the vertical E-field of the region isgreatly enhanced [7].

Fringing a gate electric field through the nitridespacer induces an inversion layer in the non-overlap re-gion, which acts as an extended S/D region. The elec-tron concentration under the spacer strongly depends

1080IEICE TRANS. ELECTRON., VOL.E85–C, NO.5 MAY 2002

Fig. 2 Schematic cross-section of MOSFET with thenon-overlap S/D to gate structure.

Fig. 3 Implanted indium contours from process simulation.

on the intensity of the fringing field and the non-overlapdistance (Lno).

Figure 3 shows the 2-D simulated doping profileof the implanted indium. An indium halo implanta-tion was applied to control short channel effects suchas punch-through current, DIBL and threshold voltageroll-off. The indium doping concentration is as high as5 × 1018/cm3 near the junction depth to suppress thepunch-through.

In this study, 50 nm NMOSFET is designed to havethe threshold voltage (VT ) of 0.3 V. We determined VT

using linearly extrapolation of the threshold voltage.In general, the VT is determined by depletion charge,which is influenced by maximum depletion width andsubstrate doping concentration, work function differ-ence between the gate and the substrate, and backbias. In MOSFET with non-overlapped S/D to gatestructure, the VT can be also affected by the Lno. Fig-ures 4(a) and (b) show the threshold voltage ratio ver-sus the Lno. The VT difference (VT,Lno-VT,Lno=10 nm)was normalized to that of the nitride spacer length of20 nm where Lno is 10 nm. Figures 4(a) and (b) showthe optimum process condition for the indium halo im-

Fig. 4 Threshold voltage versus non-overlap distance as pa-rameters of indium halo dose (a) and indium halo energy (b).(c) compares ID-VGS with VDS = 1.2 V of 50 nm MOS withLno = 10 nm. at given halo implantation energy of 30 keV,40 keV and 50 keV.

plantation. We consider triangle symbol gives optimumprocess condition, since the normalized VT changes themost smoothly, which means the VT is less affected bythe Lno. The y-axis value of about 0 indicates littlevariation of VT .

In Fig. 4(b), result for 50 keV indium halo energyshows less variation than that of 40 keV in the view ofVT variation. But Fig. 4(c) with the view of subthresh-old current at VDS = 1.2 V, as the implantation energyincreases the off-current is getting larger. Thus, the off-current is smaller for 40 keV than for 50 keV. From theFigs. 4(a), (b) and (c), the optimum process conditionof the halo implantation is the dose of 3–4× 1013 cm−2

and the energy of 40–50 keV. In this study, we use theprocess condition mentioned above and, as an example,

LEE et al.: CHARACTERISTICS OF MOSFET WITH NON-OVERLAPPED SOURCE-DRAIN TO GATE1081

a device with the spacer length of 20 nm (Lno = 10 nm)to show the internal physics.

S/D implantation was done after defining thespacer region which was formed after the halo implan-tation. In this case the length of the spacer is relatedto the non-overlap distance between S/D and gate. Todope the S/D, arsenic ions are implanted with the doseof 4 × 1014 cm−3 and the energy of 6 keV.

3. Results and Discussion

3.1 Device Characteristics with Lno

Figure 5 shows the vertical E-field in the non-overlapregion with 20 nm nitride spacer (Lno = 10 nm). Thefringing gate field through the nitride spacer inducesinversion layer in the non-overlap region to act as ex-tended S/D region. However, strength of the gate fring-ing field decreases significantly with the distance fromthe gate edge. It shows that there is a limited distanceof Lno to induce sufficient inversion layer.

Figure 6 shows electron concentrations along thechannel at different VGS from 0 V to 1.2 V and VDS

of 0.05 V with VGS step of 0.3 V. Electron concentra-tion below the spacer (Lno = 10 nm) increases as thegate bias increases. At VGS = 1.2 V, electron concen-tration of larger than 2 × 1019/cm3 is induced under

Fig. 5 Vertical E-field plot in the region below the nitridespacer.

Fig. 6 Electron concentration along the channel at differentVGS from 0 V to 1.2 V with 0.3 V step and at VDS of 0.05 V.

the spacer. Although there is no LDD region underthe spacer, electron concentration of the region can beacted as extended S/D region due to the fringing fieldthrough the nitride spacer. This figure shows that thegate bias controls inversion layer effectively in the re-gion below the spacer by the fringing E-field.

Figure 7 shows the minimum electron concentra-tion (A) in the region below the spacer and the concen-tration (B) in the channel versus a non-overlap distanceat VGS = 1.2 V and VDS = 0.05 V. As the non-overlapdistance increases, the gate fringing field effect is re-duced and electron concentration below the spacer isdecreased. According to the result, the device with theLno of 0 nm has no decrease in electron concentration.This result is inconsistent with that of [2].

Figure 8 shows the conduction band energy alongthe channel at different VGS from 0 V to 1.2 V with0.3 V step and VDS of 1.2 V. A small energy barrierexists in the non-overlapped region, and the barrier islowered as the gate voltage increases.

Figure 9 shows the on-current of 50 nm NMOS de-vice versus non-overlap distance at VGS − VT = 0.9 Vand VDS = 1.2 V. As the non-overlap distance in-creases, the Ion is degraded due to the increment ofeffective channel length. For example, the Ion at a Lno

of 5 nm is about 1 mA/µm, which is fairly reasonable.

Fig. 7 Electron concentrations in the regions below the spacerand the gate at VGS = 1.2 V and VDS = 0.05 V.

Fig. 8 Conduction band energy diagram along the channel atdifferent VGS from 0 V to 1.2 V with 0.3 V step and VDS = 1.2 V.

1082IEICE TRANS. ELECTRON., VOL.E85–C, NO.5 MAY 2002

Fig. 9 On current of 50 nm NMOS device versus non-overlapdistance at VGS = 1.2 V and VDS = 1.2 V.

Fig. 10 Subthreshold slope at VDS = 1.2 V and DIBLcharacteristics with the non-overlap distance.

It is noted that the Ion will be improved if the effectivechannel length is kept the same with the Lno. To keepreasonable turn-on current, the Lno needs to be smallerthan 10 nm.

Figure 10 shows the drain induced barrier lower-ing (DIBL) and subthreshold slope (SS) at VDS = 1.2 Vand VDS = 0.05 V versus the Lno. These results showthat the non-overlapped structure is effective in sup-pressing the SCE. The physics of the SCE can be un-derstood by considering the potential barrier, which isreferred to DIBL. When the Lno is about 10 nm, itshows smaller DIBL than that of overlapped structure(Lno < 0). It means the suppression of the SCE in thenon-overlapped structure. The subthreshold slope (SS)shows small value from the Lno of about 0 nm to 10 nm,which also represents one of the positive aspects of thenon-overlapped structure.

DIBL increases significantly due to the SCE, whenthe S/D to gate is overlapped (Lno < 0). For Lno largerthan 10 nm, the DIBL becomes degraded because ofpoor turn-on characteristics. The turn-on characteris-tics at low VDS (0.05 V) are degraded by the barrierpeaks (shown in Fig. 11(b)) under the nitride spacers.As the VDS increases to 1.2 V, the barrier around thedrain lowers as shown in Fig. 11(b), resulting in rela-tively better turn-on characteristics than VDS of 0.05 V.

Fig. 11 Conduction band energy diagram under the gate re-gion with VDS biases of 0.05 V and 1.2 V at a fixed VGS of 0 V.(a) Non-overlap distance of 10 nm. (b) Non-overlap distance of20 nm.

In this situation, the DIBL becomes large even thoughthe VT is high.

The SS is related to depletion capacitance, and in-creases with the Lno. As the Lno increases, the channelarea to be depleted by the vertical and fringing gatefield from the gate becomes wide, which in turn in-creases the depletion capacitance in the subthresholdslope equation. The SS then becomes degraded.

Figure 11 shows the conduction band energy alongthe channel with the Lno at given VDS biases of 0.05 Vand 1.2 V and VGS of 0 V. As the Lno increases from10 nm to 20 nm, the energy band diagram looks differ-ent. The energy band diagram for the Lno of 20 nmshows two peaks under both nitride spacers. As thedrain bias increases from 0.05 V to 1.2 V, the barrierunder the drain-side spacer lowers. The dominant fac-tor in controlling drain current is the barrier height,which should be lowered by the gate bias. Very smallDIBL of 30 mV/V and subthreshold slope of 80 mV/decwere obtained for Lno = 10 nm. According to these re-sults, it seems that the Lno of around 10 nm or less isreasonable.

Simulated IV characteristics are shown in Fig. 12.Figure 12(a) shows ID-VGS curves at VDS = 0.05 Vand 1.2 V. The on-current at VGS = VDS = 1.2 V is700 µA/µm. Even though the S/D is not overlapped tothe gate, reasonable IV characteristics were obtained.

In the PMOS, vertical E-field in the non-overlap

LEE et al.: CHARACTERISTICS OF MOSFET WITH NON-OVERLAPPED SOURCE-DRAIN TO GATE1083

Fig. 12 Simulated IV characteristics. (a) ID-VGS curves atVDS = 0.05 V and 1.2 V. (b) ID-VDS curves at VGS − VT = 0.3,0.6, and 0.9 V.

Fig. 13 Intrinsic gate delay versus the dielectric constant ofthe spacer as a parameter of the non-overlap distance.

region induces inversion layer with holes to act as theextended S/D region. We believe that the same storywill be applied to non-overlapped PMOS devices andneed some work.

3.2 Intrinsic Gate Delay

In Fig. 13, intrinsic gate delay versus the dielectric con-stant of the spacer is shown as a parameter of the Lno.As the Lno decreases, the gate delay is improved by ahigher drive current due to the lower S/D resistance.The gate delay increases as the dielectric constant in-creases due to the parasitic fringing gate capacitance.The minimum gate delay is decided from the drive cur-rent and the gate capacitance. When the increment of

Fig. 14 On-current, gate capacitance, and intrinsic gate delaytime versus dielectric constant.

Fig. 15 Schematic cross-section of the modified non-overlapMOS structure with dual spacer.

the gate capacitance is smaller than that of the currentwith the increase of dielectric constant, the minimumgate delay is achieved. As the Lno decreases, the intrin-sic gate delay is improved due to higher drive current.The DIBL and the SS, however, cannot be an optimumas shown in Fig. 10.

Figure 14 shows the drive current and gate capac-itance at VGS = VDS = 1.2 V, and intrinsic gate delayversus the dielectric constant of the spacer. As the di-electric constant increases the current is saturated withhigher rate than the capacitance. With Lno = 10 nm,the intrinsic gate delay time has minimum delay at thedielectric constant of 7.

To get a smaller gate delay, reducing gate capaci-tance is needed. The gate to drain and gate to sourcecapacitance is increased due to the overlap region be-tween the nitride spacer and the S/D region. Figure 15shows modified cross sectional view of MOSFET withthe non-overlapped S/D structure, where the spacerconsists of about 10 nm nitride and 10 nm oxide spacerregions. The oxide spacer overlaps with the S/D, bywhich the gate capacitance decreases a little, and therelative decreases of the capacitance becomes signifi-cant when the high-k spacer is applied instead of thenitride spacer.

Figure 16 shows the drive current and gate capac-itance at VGS = VDS = 1.2 V, and the gate delay ver-

1084IEICE TRANS. ELECTRON., VOL.E85–C, NO.5 MAY 2002

Fig. 16 On-current, gate capacitance, and intrinsic gate delaytime of modified non-overlap MOS device versus dielectric con-stant.

sus the dielectric constant of the spacer on the non-overlapped region. The gate capacitance of modifiedstructure is reduced, and the drive current is slightlychanged. The high-k spacer induces inversion layer inthe non-overlap region and the oxide spacer reducesgate capacitance effectively. The dielectric constant ofthe high-k spacer on the non-overlapped region is about20 for the minimum gate delay.

4. Conclusions

A new MOSFET structure with non-overlap S/D to n+

poly gate has been proposed and studied by simulation.A careful optimization of halo implantation was doneto suppress short channel effect. The propose structureshowed very good subthreshold slop and DIBL com-pared to those of the overlap structure. By controllingthe non-overlap distance, we could obtain reasonablespeed and on-current characteristics. We have also pro-posed a modified non-overlap MOS structure with dualspacers to reduce intrinsic gate delay. It was shownthat the utilization of high-k spacer in the MOS devicewith the dual spacer structure is very useful in reducingthe intrinsic gate delay while keeping good short chan-nel effect. Based on the results, we conclude reasonablenon-overlap distance is between 0 (just meet the gateedge) to 10 nm. The non-overlap structure also avoidsthe difficulty in forming ultra shallow S/D junction.Therefore, we consider that the non-overlap structureis suitable for further device scaling.

Acknowledgments

This work was supported by Tera Level Nanodevicesproject of MOST in 2001.

References

[1] R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D.Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy,and G. Dewey, “30 nm physical gate length CMOS transistorswith 1.0 ps n-MOS and 1.7 ps p-MOS gate delays,” ElectronDevices Meeting 2000, IEDM Technical Digest International,

pp.45–48, 2000.[2] S. Thompson, P. Packan, T. Ghani, M. Stettler, M. Alavi,

I. Post, S. Tyagi, S. Ahmed, S. Yang, and M. Bohr,“Source/drain extension scaling for 0.1 /spl mu/m and belowchannel length MOSFETs,” VLSI Technology, pp.132–133,1998.

[3] Y. Taur and T.H. Ning, Fundamentals of Modern VLSI De-vices, Cambridge Univ. Press, pp.168–169, 1998.

[4] S. Han, S. Chang, J. Lee, and H. Shin, “50 nm MOSFET withelectrically induced source/drain extensions,” IEEE Trans.Electron Devices, vol.48, no.9, pp.2058–2064, Sept. 2001.

[5] Silvaco International, ATHENA User’s Manual, version5.2.0.R, 2000.

[6] Silvaco International, ATLAS User’s Manual, version5.2.0.R, 2000.

[7] S. Chang, J. Lee, and H. Shin “GIDL currents in MOSFETswith high-k dielectric,” SSDM, pp.234–235, Sept. 2001.

Hyunjin Lee was born in Taejon, Ko-rea, in 1979. She received the B.S. degreein electrical engineering from the KoreanAdvanced Institute of Science and Tech-nology (KAIST), Taejon, in 2001, respec-tively, where she is currently pursuing theM.S. degree. Hers research interests in-clude device design of nanoscale CMOSdevices.

Sung-il Chang was born in Pusan,Korea, in 1978. He received the B.S. andM.S. degrees in electrical engineering fromthe Korean Advanced Institute of Scienceand Technology (KAIST), Taejon, in 1999and 2001, respectively, where he is cur-rently pursuing the Ph.D. degree. His re-search interests include device design andfabrication of nanoscale CMOS devices.

Jongho Lee received the B.S. degreein electronic engineering from KyungpookNational University, Taegu, Korea, in1987. He received the M.S. and Ph.D.degrees from Seoul National University,Seoul, in 1989 and 1993, respectively,both in electronic engineering. In 1983,he worked on advanced BiCMOS processdevelopment at the Interuniversity Semi-conductor Research Center (ISRC), SeoulNational University, as an Engineer. In

1994, he joined the School of Electrical Engineering, WonkwangUniversity, Iksan, Chonpuk, Korea, where he is now an Asso-ciate Professor. From 1994 to 1998, he was with ETRI as anInvited Member of Technical Staff, working on deep submicronSOI devices, device isolation, 1/f noise, and device mismatchcharacterization. From August 1998 to July 1999, he was withthe Massachusetts Institute of Technology (MIT), Cambridge, asa Postdoctoral Researcher, where he was engaged in research onsub-100 nm double-gate CMOS devices. His research interests in-clude sub-100 nm device technologies, nanocrystal memory, highperformance IC design, and Microsystems.

LEE et al.: CHARACTERISTICS OF MOSFET WITH NON-OVERLAPPED SOURCE-DRAIN TO GATE1085

Hyungcheol Shin received the B.S.degree (magna cum laude) and M.S. de-gree in electronics engineering from SeoulNational University, Seoul, in 1985 and1987, respectively, and the Ph.D. degreein electrical engineering form the Univer-sity of California, Berkeley, in 1993. From1994 to 1996, he was with Motorola Ad-vanced Custom Technologies, as a SeniorDevice Engineer. In 1996, he joined theDepartment of Electrical Engineering and

Computer Sciences at the Korea Advanced Institute of Scienceand Technology (KAIST), Taejon, in 1996 as an Assistant Pro-fessor and is now an Associate Professor. His current researchinterests include nano CMOS, CMOS RF modeling, and RF cir-cuits. He has published over 130 technical papers in internationaljournals and conference proceedings and also wrote one chapterin a Japanese book on plasma charging damage. 1993. Dr. Shinhas served as a Committee Member of several international con-ferences, including IEEE Silicon Nano-electronics Workshop andIEEE Symposium on Plasma-Process Induced Damage (P2ID).He is a Lifetime Member of IEEK and received the Second BestPaper Award from the American Vacuum Society in 1991. Healso received the Excellent Teaching Award from the Departmentof Electrical Engineering and Computer Sciences at KAIST in1998. In 1999, he received The Haedong Paper Award from TheInstitute of Electronics Engineers of KOREA (IEEK). He hasbeen listed in the Marquis Who’s Who in the World and TheOutstanding People of the 20th Century, 3rd edition. He willalso be listed in International Personality of the Year in 2001.