Paper - Design and Characteristics LDD

7/29/2019 Paper - Design and Characteristics LDD

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.D-27, NO. 8, AUGUST 1980359

Design and Characteristics of the Lightly DopedDrain-Source (LDD) insulated GateField-Effect Transistor

Abstruct-The LDDstructure,wherenarrow, self-aligned n- regionsare introduced between the channel and the n+source-drain diffusionsof an GFET to spread the high field at the drain pinchoff region andthus reduce the maximum field intensity, is analyzed. The design isshown, including optimization of the n- dimensions and concentrationsand the boron channel doping profile and an evaluation of the effectof the series resistance of the n- regionson device transconductance.Characteristicsof experimental devices are presented and compared tothose of conventional IGFETs. t is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channelthreshold effects can be achieved allowing operation at higher voltage,ag, 8.5 versus 5 V, with shorter source-dr ain spacings, e.% , 1.2 versus1.5pm. Alternatively, ashorter channel length could be used for agiven supply voltage. Performance projections are shown which predict1.7 X basic device/circuit speed enhancement over conventional struc-tures Due to the higher voltages and higher frequency operation, thehigher performance results in an ncrease in power which must be con-sidered in a practical design.

A I . NTRODUCTIONS THE DEMANDS on he GFET echnology have in-creased to achieve higher speed and areal density, morephysicalimitations have becomevident.evice/circuitdesigners must consider not only threshold voltage (VT) aria-tionswith device channel ength andwidth,punchthroughvoltage, junction breakdown voltage, and maximum gate elec-trode voltages, but also limitations mposed by hot-electroneffects [1]-[5], secondary mpact onization, which results nelectron njection into hesubstrate 6]-[8],and sustainingvoltages.Scaling [9]- [l 11, where all physicaldimensionsand thepowersupplyand hreshold voltagesare scaled down by afactor k, k


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1360 IEEE TRANSACTIONS ON EL ECT RON DEV ICES, VOL. ED-27, NO. 8, AUGUST 1980

-2oh91 5 1 I I I I.1 .2 .3 .4 . 5 .6 .7 .8 .9Distance (rm)(b1

Fig. 1. (a) L DD structure or 8.5-V power supply, to, =45 nm, xi =0.5 pm (n'), xi =0.3pm (n-), L = 1.2pm (minimum), ps (substrateresistivity) = 5 C2 . cm. b)Conventionalstructure or 5-V powersupply with design parameters the same as in Fig. l(a) except L =1.5pm (minimum) andps = 15 C2 . cm.it would require an extra masking step). The n- dimensionsand dopant concentration are determined by the desired m-provement in breakdown voltage, short-channel Vr falloff, andother electrical characteristics (Section 111). The n- ength isdefined as the distance between the n--p metallurgical junctionat the Si-SiOz interface and the position of the n+-p metal-lurgical junction at the interface if the n- implant were elimi-nated. The particular LDD device shown in Fig. l(a) has beenoptimized for an 8.5-V power supply by specifying a 45-nmgate nsulator, 0.5-pm n+ unction depth, 0.3-pm n- junctiondepth, 0.30-pm n- ength, 1.2 X lO"-~m-~ eak n- concen-tration, 5 4 cm substrate, and a channel implant to bring thesurfaceconcentration to 1X 10l6 ~ m - ~ .heconventionalMOSFET il lustrated n Fig. l (b) was designed with the sameprocess, butoperatesat5-V powersupply.Theminimumchannel ength is 1.5 pm for the conventional device and 1.2pm for the LDD device.The LDD structure can be fabricated (Fig. 2) using conven-tionalplanar ilicon-gate processing techniquesandopticallithography.Afterpatterning heSiOz-poly-Si-Si3N4-SiOZgatestack, he n+ source-drain is implanted (Fig. 2(a)). Apyrocatechal wet etch or plasma etch step undercuts the poly-silicon gate [17] by approximately 0.55 pm (Fig. 2(b)). Next

n' implant

(d)Fig. 2. L DD fabrication sequence. (a) Theself-alignedn source-drainas implanted. (b) The polysilicon gate is overetched by 0.55 pm. (c)A fteretchingSi02andSi3N4, he n- regions are mplanted. d)A fter he emaining process steps, he ini shed LDD structure isobtained.

theSi3N4 is stripped rom hepolysilicongateand he n-region is implanted (F ig. 2(c)). A fter drive-in and the remain-ing conventional processing steps, he inishedstructure isobtainedFig. 2(d)). Then- regions dopedbydouble-implantationof As' or P+ to providea latprofilewhichminimizes the n- region resistivity without increasing the peakconcentration. I t must be noted that the choice of As' versusP+ dependsonhe ubsequenthermal cycles.Unless theimplant is designed correctly, a polysilicon gate to n- regionunderlap ondition can develop in As' implanted devicessince, under certain conditions, the polysilicon oxidation rateis greater than the As diffusivity. I t is our experience that thepolysilicongate undercut, becauseof the small tolerance re-quiredon then- region length, is themost ritical tep.A lthough we have successfully fabricated experimental devicesusing the undercut technique, further work is needed to im-prove its reproducibility.The eduction nelectric-field ntensitydue to he LDDstructure is clearly llustrated n the two-dimensional simula-tion results of Fig. 3. The electric field at the Si-Si02 nter-face as a function of distance along the channel near the drainis plotted or a conventional and an LDD device, both withchannel engths of 1.5 pm. The bias conditions or the two-dimensional simulations are VDs=10V , VsuB=-2 V, V ~ SVT. Physical dimensions corresponding to the horizontal scaleare shown at the top of Fig. 3. The electric field in the con-ventional device peaks pproximately themetallurgicaljunction and drops quickly to zero n hedrain because nofield can exist n hehighlyconductive n+region.On theother hand, the electric field in the LDD device extends acrossthe n- region before dropping to zero at the drain. Since theareas under the two field curves in Fig. 3 are equal for a givenvoltage drop, he peak field in theLDD device-whichverynearly determines the junction avalanche breakdown voltage-


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OGURA etal.: LI GHTL Y DOPED DRAIN-SOURCE (L DD)NSULATEDATEET 1361LDD Conventional

Gate I- - - - -J

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.6Position AlongSurtace (rm)

Fig. 3. Magnitudeof theelectric field at he S i 4 0 2 interface as afunctionofdistance; L = 1.2 pm, VDS= 8.5 V , VGS = VT. Thephysical geometries for both devices are shown above the pl ot.must be lower than in the conventional device, as shown. Thedrain avalanche breakdown will occur when the peak electricfieldreachesapproximately 5.5 X l o5Vcm-' 18]. By ad-justing the drain voltage to obtain this critical electric ield,thebreakdown voltage of he1.2-pmchannel ength LDDdevice in Fig. l(a) was shown to exceedhebreakdownvoltage of a 1.2-pm conventional device by 6 V, even with ann- length of only 0.30pm.' TheI-V characteristics of experi-mentally fabricated conventional and LDD IGFET's with 1.2-pm channel lengths shown in Fig. 4 confirm the predictions ofthe two-dimensional simulations.The effect of varying the channel length and n- doping con-centration on the electric field strength and the resultant m-provement nhot-electronemission, mpact onization,andshort channel VT falloff will be discussed in the next section,where we will optimize the LDD device design using an 8.5-Vpower supply. n Section V , the performance of this devicedesign will be compared to a conventional IGFET.

111 LDD DEVICE DESIGNND CHARACTERISTICSA. DesignConsiderations

When an IGFET channel length is reduced, three major limi-tations must be considered: 1) drain breakdown voltage com-prising punchthrough,snapback,andsustaining voltages, 2)impact ionization in the drain pinchoff region which can leadto hot-electric njection nto the gate nsulator and electroncurrent into the substrate due to secondary impact ionization,and 3) short-channel VT falloff. InonventionalGFETdesign,parametersmay be adjusted to tradeone imitationfor another. For example, thinner gate oxides and shallowerjunction depths mprove short-channel V, falloff and punch-through voltages, but heydeteriorate avalanche breakdownvoltage, hot-electron injection, and impact ionization.The LDD structure introduces a new independent parameter-design of the n-region-which can relax all three limitations.The length and doping concentration of the n- region controlthe electric-field strengthanddistribution in thepinchoff'Measured by SEM.

Fig. 4. I -V characteristics of aconventional GFET upper)and anL DD IGF ET (lower); L =1.2pm. The 6-V breakdown voltage m-provement or he L DD device agrees with he two-dimensionalsimulations (note difference in hori zontal cales).

region independently rom he existing device parameters.However, i t must be noted that the n- region behaves as aseries resistance in the device which tends to degrade the per-formance advantage achieved by decreasing the channel lengthor ncreasing the power supply voltage. The R drop acrossthe n- regions must be significantly smaller than the powersupply voltage enhancement obtained by improving the break-down voltage to realize an appreciable net performance gain.B. Breakdown Voltage

Two mechanisms cause IGFET breakdown at high drain bias.Punchthroughreakdownccurs in short-channel deviceswhen hedraindepletion region extends o hesourceandlowers the source potential barrier sufficiently for electrons tobe emitted nto hedepletion region where hey are subse-quently accelerated to the drain [ 19 ] . In longchannel devices,the electric field at the drain metallurgical unction becomeshigh enough to cause avalanche breakdown before depletionreaches the source. The sustaining voltage phenomenon occurswhen the positive feedback rom hesubstrate IR drop for-ward biases thesource.Both avalanche andpunchthroughbreakdown are sometimes observed in the same device; theycan be separated because the former is accornpanied by sub-strate hole)current. ngeneral, GFET designs are limitedby avalanche breakdown, which will be discussed first.Avalanchebreakdown voltages (measured at I s U B =4 pAper micrometer hannelwidth) as a funct.ion of channellengthonexperimental LDD andconventional devices areshown by he solid ines n Fig. 5. The LDD deviceshaven- lengthsof0.42 *0.03pmandpeak n-concentrationsof 1.2 X 10l7*0.2 X 10'' ~ m - ~ .he deep channel dopingprofile used for LDD and the shallowprofile used for the con-ventional devices are plotted in Fig. 6. (The reason for usingdifferent profi les will be made clear in the discussion of short-channel VT falloff.) The experimental mprovement in break-


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1362 IEEE TRANSACTIONS ON ELE CTRON DEVICES, YOL. ED-17, Kg. X, A USUST 19BPExperimental D ataVS.SS=2 v

Avalanche BreakdownAi VGS VT +2V/ I Punchhrough? ? At VO S .25V

($-Shal low Channel ProtileDeep Channel Profile

Channel Length urn)Fig. 5. Experimental avalanche and punchthrough breakdown voltagesfor conventional and LDD I GFETs versus channel length. The uppercurve is for an LD D device with an n- peak concentration of 1.2 XIOl7 ~ r n - ~nd n- length of 0.4 pm Punchthrough breakdown wasmeasured at 4 pA/W/L. -- - - }CalculatedPulsed C.VProfilesData

- 1.8-1.6-0r2 1.4 -0.-c2 1 .2 -Q

0 1.0 - -Eg 0.8-E 08rn- -m

0.4 -

Conventional

O\O\ o\

0 0 0- - - - - - -.I .2 .3 .4 .5 . 6 .7 . 8 .9Depth (Ilrn)

Fig. 6. Channel doping versus depth rom the Si-Si02 nterface or aconventional IGFET and an DD IGFET.

down voltage at L =1.2 pm for LDD over conventional devicesis 8 V, which provides enough margin for the power supplyvoltage to be ncreased from 5 to 8.5 V while reducing thechannel length from 1.5 (minimum) to 1.2 pm.In order to quantify the design tradeoffs with the design ofthen- region,computer analyseswere performed. A handcalculation of avalanche breakdown voltage presents no diffi-culty for a simple p-n junction, but n an IGFET, the gate elec-trode constricts the electric field near the drain and rendersanalyticalcalculation of hebreakdown voltage intractable.Carrier densities and the positive eedback mechanism whichforward biases the source in short-channel IGFETs must alsobe accounted for. Consequently, two-dimensional simulationsandnumericalcurve-fi tting echniques have beenemployed[20]. I n Section I1 we used a critical electric field (5.5 X l o5V * cm-) to estimate the breakdown voltage. In this sectionwe will be more precise by numerically integrating the ioniza-

tion integral [21]I =dw exp [ , I wa, -. ap>dx dxI

wherea, =3.8X lo6cm- exp(-1.75 X I O6V. cm-/IEl)ap=2.25 X lo7cm- exp (-3.26 X IO6V cm-/IEl)

along a path extending from the pinchoff point o:f the inver-sion layer (x=0) to the n+ rain (x =W), vrlhere ( x , andaparethe onization rates for electrons and holes, respectively. Theelectric fields (E )were calculated by a two,-dime:nsional semi-conductor device simulation program n which tlhe generationtermsdue to impact onization were neglected in thecon-tinuity equations. Consequently, the two-dimensional simula-tion could not account for modifications to the eilectric fieldand positive feedbackdue to secondary carrier!;. Thiswaak-ness was minimized by biasing the gate just above VT so thatthe seed current available for impact ionization was negligible.Then I =1 is thecondition oravalanchebreakdown. Al-though we are now mposing a severe limitation on the rangeof gate voltages which can be simulated, in practice:, the brieak-down voltage at higher VG generally ollows the breakdownvoltage at VG =V, within 2 V.Avalanche breakdown voltagewas calculated at aixedchannel length, L =1.2prn, for conventional and LDD deviceswhile varying n- region design parameters. The effect of vary-ing the peak n- concentration for a fixed n- ength, 0.3pm,on breakdown voltage is plotted n Fig. 7(a). The breakdownvoltage is a linear function of the peak n- concentration in therange 0.5 X 1017 cm-3


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OGURA etal.: LI GHTL Y DOPED DRAIN-SOURCE (LDD)NSULATEDA TEET 1363

r 'x \

Xj =0.3pmn- Length=0 . 3 ~L=1.2pm

t.....5 1 o 1.5 2.0n- Peak Concentration (x10"cm-3)(a)

/-Peak n-e- Concentration =

6 -

0.1 0.2 0.3 0.4n- Length (Irm)

(b)Fig. 7. Simulated breakdown voltage improvement (over conventionalIGFET's) versus (a) n- peak concentration for L DD GF ET 's with afi xed n- ength, 0.3 pm; (b) n- ength for three n- concentrations:0.5x lo1', 1.5x 1017,and 2 x 1017~ m - ~ .channel V , falloff, which will be treated in Section 1114) willbecome the l imiting factor if the avalanche breakdown voltageis designed high enough. The LDD structure tself, however,provides an improvement in the punchthrough voltage. Fig. 8il lustrates this improvement qualitatively. In Fig. 8 equipoten-tial contours from two-dimensionally simulated cross sectionsof two MOSFET's wi th he same channeldopingprofilesunder dentical bias conditions (Vs=0V, VD=8.5 V, VG=VT, V& =-2) areuperimposed. he roken contoursrepresent a conventional IGFET withL =1.8 pm and the solidcontours represent an LDD IGFET with L =1.3pm and n-length of 0.25 pm. Other design parameters are as in Fig. 1.The distances 1 and I between opposite sides of the 0-V equi-potentials as they arc from source to drain are equal in Fig. 8,which indicates a similarpunchthrough voltage for each device.A quantitative simulation (not shown here) in which the drainvoltage was ramped up until lo-'' A/pmwidthofpunch-through current was obtained, showed a 0.5-pm channel lengthadvantage for an LDD device with a 0.45-pm n- length. The

Convention Device Gate, L =1.8pmI LD D DeviceGale, =1.3pm

3

- 1. 421

0- 1

Fig. 8. Equipotential contours for a 1.8-pmconventional IGFET and a1.3-pm L DD I GFET under identical bias conditions (Vs=0V, VD=8.5 V, VG=VT, VSUB =-2 V). Both substrate material (15 s2 * cm)and channel boron profi le are identical. The distances 1 and l ', whichare equal, show qualitatively the superior punchthrough behavior ofLDD IGFET's. Note that the equipotentials are pushed into the n-drain region in the LDD device.channel-length advantage for L DD arises principally because,as shown n Fig. 8, the equipotentials have been pushed intothe drain n- region; the shallow n- junctions also contributeto the punchthrough improvement.Experimental data on punchthrough voltage areshown bythe dashed ines n Fig. 5 for LDD and conventional devices.The conventional devices were abricated with two differentchannel doping profiles (Fig. 6) and the punchthrough voltagecorresponding to eachprofile is plotted.Only hedeeperprofile was used for L DD devices. With the deep boron profilea 50-percent margin above the power supply voltage exists forboth an 8.5-V LDD and a 5-V conventional device design witha 1.2-pm channel ength. The shallow profi le, which is moretypicalofcurrent5-V designs, has a 50-percent margin atabout 1.5-pm channel length.C Short-Channel Effect on Threshold Voltage

The LDD structure alleviates the falloff in threshold voltage(V,) that accompaniesa eduction in channel ength.Thedepletion of the n- region (similar to the punchthrough volt-age argument made using Fig. 8), the use of a deeper boronprofile,and the shallow n- region areall actors in the im-provement.The boron profilesare hown in Fig. 6. Thechoice of profi les is made from considerations of breakdownvoltages,substratesensitivity (bodyeffect), andcircuitper-formance, as well as V , falloff. The shallow profile is typicalof present5-V designs. Experimentaland wo-dimensionalsimulated threshold voltages, defined as the gate voltage whichgives 40 nA of drain current normalized to W/L =1,are pro-vided in Fig. 9(a), (b) as a function of channel length. Experi-mentaldata agree wi th he simulation esultsexcept or avertical shift due to the process uncertainty.In heconventionaldevice, the thresholdcurves, both forVDs=0.1 and 5 V , fall off rather steeply while the L DD curvefor V D ~0.1V is flat. Even with VDs=8.5 V, the VT fall-off is better than that for conventional GFET's at 5 V. The


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1364 IEEE TRANSACTIONS ON EL ECTRON DEVICES, VOL. ED-27, NO. 8, AUGUST 1 9 8 0- esian ValueB y 20 Simulation

Conventional Device15ncm Shallow ProfileV.," =2v

1 2 3 4Channel Lengthbm)(a)

P i Ds=o'lv1 2 3 4

Channel Length rm)(b)

Fig. 9. Simulatedandexperimental hreshold voltageversuschannellength or (a)aconventional IGFET, (b)an LDD IGFE T.Threecurves are shown corresponding to: 1) VDS=0.1 V, IDS=40 nA/WIL, 2) VDS=VDD, IDS=40 nA/W/L, 3) VDS=VDD, DS=4 PA/WIL. VT corresponds to IDS=40nA/W/L n the upper curves, and4 pA/W/L in the curves labeled "L ow Current Margin."low current thresholds, defined at DS =4 PA /W/L,also showan mprovementwith he LDD structure.The lowcurrentvoltage margins shown in Fig. 9are typical of the requirementfor dynamic circuit design. Consequently, the LDD thresholdvoltage (1 .O V) with VS =0.1V at a typical channel ength(1.7pm) can be designed to be about the same as the conven-tional device threshold (0.9V) with VDs=0.1 V at L =2.0pm even though the power supply voltage s increased from5 to 8.5V.Thesubstratesensitivity curves of heexperimentalLDDandconventional devices areshown n Fig. 10. The highersubstrate sensitivity of the LDD device is tolerable because ofthe higher operating voltage.D. n- Design and I-V Characteristics

The n--regionprofileand esulting series resistance is thefinal design parameter tobe discussed. A box-like n- profile isspecified to reduce the resistance without increasing the peakconcentration-whichwouldeducehe device breakdownvoltage. The0.3-pm unctiondepth was chosen to improveshort-channel V , falloff; in practice, a deeper junction is diffi-cult to attain using As as the dopant. A double n- implant wasspecified toachieve this concentration profile, which s plottedin Fig. 11as a function of distance from the Si-SO2 interface.The sheet resistance of the n- diffusion as a function of thepeak concentration is plotted in Fig. 12.The procedure for calculating the proper n- parameters willbe outlined or a specific example n which a power supplyincrease from 5 to 8.5V and a channel length reduction from

2.0 - o LDD ata For =2 . 2 ~x ConventionalData For L =2 . 5 ~ o_---

* LD D 4 - 2 0 Simulatione -

ll " l " 1 1 " ' l1 2 3 4 5 6 7 8 9 1 0

vS.SUB (v )Fig. 10. Threshold voltage versus source-to-substrate bias or GF ET'swith 5-s2 .cm substrates and shall ow channel doping profil es. (Theprofiles are shown in Fig. 6. ) Both two-dimensional simulations anddata are shown.

Simulated Profile

E

Depth (urn)Fig. 11. LDD n- mpurity concentration versus distance rom the Si-Si02 nterface.

8I

0.5 1.0 1.5 2.0n- Peak Concentration (x1O"cm-J)

Fig. 12. Sheet resistance (R, ) ofn-diffusionsand n- concentrationversus total n- implant dose.1.5 pm is desired.First, the increase nbreakdown voltageneeded is determined to be 6V by choosing the requiredmargin. Then the minimum channel length is determined (1.2pm) by selecting an appropriate n- length and peak concentra-tion to achieve both the breakdown voltage improvement andthe necessary short-channel VT falloff specif ication. Now thechoice of n- length and peak concentration is not unique be-


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OGURA etal.: LI GHTL Y DOPED DRAIN-SOURCE (LDD)NSULATEDA TEET 1365ABVDs=6V /L = . 2pm / x"/

0.1 1-.5 1 o 1.5n- Peak Concentration (xlO"cm-')(a)

I ABVDs=6V

0.5 1 o 1.5n- Peak Concentration (xlO"cm-')(b)Fig. 13. (a) n- ength versus n- peak concentration for a 6-V improve-ment nbreakdown voltage at L =1.2pm. b) Series esistance(normalized to W=1pm) versus n- peak concentration for a 6-Vimprovement in breakdown oltage at L =1.2 pm.cause a longer/shorter length and a higher/lower peak concen-tration could be selected to obtai n the same breakdown volt-age and short-channel V, falloff specif ication. But only onechoice of the parameter set (n- length, n- peak concentration)will minimize the source-drainseries esistance while at thesame time providing the required breakdown voltage improve-mentandshort-channel V, falloffspecification. To find it,the n- length and the n- series resistance are plotted as func-tions of the n- concentration whileholding the breakdownvoltage constant (Fig. 13(a), (b)). The minimum n Fig. 13(b)is the smallestpossible series resistance (1.2 kQ pm)whichwill providea6-V mprovement n breakdown voltage.Thecorresponding n- concentration (9 X 10l6 ~ m - ~ )s then readfrom the horizontal axis, and Fig. 13(a) is used to obtain thecorresponding n- length (0.25pm).Due to process uncertainties, the n- length and peak concen-tration were increased in experimentaldevice designs abovethe level specified by the optimization procedure. When then- length and concentration are ncreased, Fig. 7 shows thatthe breakdown voltage is less sensitive to absolute variationsin the n- length. LDD devices were fabricated with a channellength of 1.2 pm , an n- length of 0.42 k 0.03 pm and a peakconcentration of 1.2 X 1017+_ 2 X lo" cm-3 to get the same6-V breakdown voltage improvement used to optimize heseries esistance, For theseparameters, the series esistanceis predicted to increase to 1.4 kS2 - pm from heoptimum1.2kQ * pm. Themeasured series resistance 1.2 kS2 pm)was actually somewhat better than predicted, but well withinthe uncertainty n the measurement of the n- region engthand impurity profile.The grounded source I-V characteristics of a conventionaldevice and an LDD device, both wi th channel lengths of 1.2pm, were shown n Fig. 4. The LDD device had an n- resis-

I Hardware ResultsL=2.1um Vo =6.5V

v, = 5 v

2.0 -

1 2 3 4 5 6 7 8-va s (V )

Fig. 14. I -V characteristics of a Conventional device and of LDD de-vices showing the degradation of transconductance when 1.2 and4. 5k n .pm series resistances are added to the source/drain. T he channellength is 2.1 pm.tance of 1.2 kQ - pm and an n- length of 0.3 pm. The sensi-tivityof the I-V characteristics to he series resistance isil lustrated in Fig. 14 forhreeexperimental devices: 1) aconventional device, 2) an LDD device with 1.2-ki2 * pmresis-tance, and 3) an LDD device with 4.5-k!2 * pm resistance. A2.1-pmchannel ength was chosen to approximateaworstcase (long-channel) device with nominal channel length of 1.7pm, which determines the worst case circuit performance. Thedegradation of transconductance due to the 1.2-kQ pm resis-tance is less than 5 percent. The degradation for 4.5 kS2 - pmis about 20 percent or less.E. Hot-Electron Emssionand Impact Ionization

Hot electron emission into the IGFET gate insulator and theresultant threshold voltage instabil ity is well understood, butrecently a new potential problem n dynamic RAM'S relatedto hot electrons has been reported; namely, the njection ofelectrons into the neutral bulk region due to secondary impactionization nitiated by holes in the pinchoff region [6]-[8].The presence of free electrons in sufficient quantity in the ub-strate may result in the degradation of stored voltage acrossnearby RA M cells since the diffusion engthofelectrons isgreater than 100 pm in typical sil icon substrates [22]. We willbriefly discuss these effects for the L DD device structure.The substrate current is a good measure of the level of hot-electron emission since nearly all of the holes created by im-pact onization are swept nto the substrate. n Fig. 15, theexperimental maximum substrate current (Fig. 17 shows theexistenceof a 'maximum substrate current or a given VDS)is plotted as a function of channel engths for a conventionalIGFE T at VDS=5 and 8.5V and for an LDD IGFET with ann- length of 0.4 pm and peak concentration of 1.2 X 1017cm-l at VDs=8.5 V. At the same drain bias condition, theLDD devices showgreater han 30X reduction nsubstratecurrent over conventional devices. At 5-Vdrainbias, theconventional devices deliver the same substrate current as theLDD devices at 8.5 V. This comes as no surprise in view of the


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E 366 IE EE T RANSA CTIONS ON EL ECT RON DEVICES, VOL. ED-21, NO. 8 , AUGUST 1980

'. -- - ConventionalLDD n- Length I 0 . 4 p nn- Peak Concentration P 1.2 x 10" cm-a\'\'\*''\**-- - - - D,=0.5V9- - -- --,--

\

I 1 2 3 4 5Channel Length km )

Fig. 15. Maximum substrate current versuschannel ength oracon-ventional GFET and an LDD IG FE T with n- ength =0.4 bm, n-peak concentration =1.2 X l O I 7 cmV 3.electric-fieldreduction in the L DD structure. t canalso beseen, from Fig. 3, that the position of the peak electric field sshiftedaway rom hechannel region in heLDDstructurewhere it does less harm in terms of hot-electron injection intothe gate insulator.In a related experiment, the substrate electron current wasmeasured by employinga large MOS capacitor biased intodeepdepletionnearawide GFET. An n+ diffusion buttedagainst the capacitor was positively biased and connected to anammeter to continuouslymonitor heelectroncurrent ntothecapacitor.Thecurrentat he n+ diffusion contact wasmeasured as a functionof he gate voltage of henearbyIGFET or severalvalues of the drain voltage. The substratecurrent was measured at he same time.Theexperimentalsetup is shownn Fig. 16. Both onventional nd DDIGFET 's with 1.7-pm channel engths abricated on denticaltest sites were used as electron sources.Themeasured ubstratecurrentandelectroncurrentareplotted n Fig. 17 as a functionof VGS with V'S fixed at8.5 V . The electron current plotted n Fig. 17represents onlythe fraction collected by the capacitor. The fact that the elec-tron current curve has a shape similar to the substrate (hole)current curves provides evidence of secondary mpact oniza-tion and free-electron injection from the drain pinchoff regioninto hesubstrate. Fig. 18 shows the peakelectroncurrentmeasured at the n+ iffusion contact as a function of the drainvoltage for conventional and LDD I GFET's. At the same drainvoltage, LDD devices inject fewer electrons nto the substratethan conventional devices; but comparing conventional devicesat V& =5 V to L DD devices at VDs=8.5 V, a slight advan-tage is seen for conventional devices.

IV . PEFORMANCEROJECTIONSThe higher operating voltage and shorter source-drain spac-ing of the L DD device results in a higher transconductance andlower intrinsic gate source-drain overlap capacitances than the

Collector Capacitor DeviceL =1.7pm350q-nx 7 0 0 p m W = 1 2 5 x 4 p mI lo

Fig. 16. Experimental etup ormeasurement of substrateelectroncurrent.

r Device,.----- =1.7pmI .,ConventlonaiSubstrate ', W =500pm

V D s = 0 . 5 VHole Current \VS.SU0 =2 v

\\

Collected By Capacitor\-

tL " " " ' 1

1 2 3 4 5 0 7 0VGS (v)Fig. 17. Substrate urrent ndelectron urrentntohe oll ectorcapacitorversus VGS with VDS=8.5 V foraconventionalandanLDD device.

Source Device5 W =500pmi 00m

- v o s = 3 . 5 ~-$ 300

500 - L = 1 . 7 p m-.- VS.SU0=2 v0h

Uu-0'i 20 0 - n- Length e 0.4pmgaE 10 0 -

n- Peak Concentratlon P-a512 4 6 a 10

vQ S (v )Fig. 18. Peak electron current nto the col lector capacitor versus drainvoltage for conventional and L DD IG FET's with L =1.2bm.


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OGURA etal.: LI GHTLY DOPED DRAIN-SOURCE (LDD)NSULATEDATEET 1361conventional device and, herefore, results n astercircuits.Inorder to evaluate theperformanceenhancements,circuitsimulationsweremade usingASTA P with heappropriatedevice models E231 which are it to the experimental devicecharacterization.Theclockcircuit of adynamic RAM waschosen for the analysis. Static circuits will experience equiva-lent performance enhancements.For the 8.5-V LDD design, the channel length was chosen tobe 1.7 k 0.5 pm and the n- resistance to be 1.4kSl - pm. Forthe5-Vconventional device design, the channel ength was2.0? 0.5p. Fornominal device lengths (i.e., 1.7and 2.0p),he performance enhancement or the LDD devicewas1.5X. For heworst case channel engths (i.e., 2.2 p forLDD and 2.5 pm or the conventional device), the enhance-ment was calculated to be 1.7X. The variation in performanceratio occurs primarily because of velocity saturation and short-channel ransconductanceeffectswhicharemoresignificantfor the 8.5-V LDD design. I n practice, the performance of theslowest chips determine the performance specifications, hencethe larger ratio (1.7X) is of interest.

Calculations were also done or a 5-V conventional deviceusing the deep boron profile with a 5-Sl * cm substrate with achannel ength of 1.7 f 0.5 pm. No significantperformanceadvantage was seen due to the increased substrate sensitivity,verifying that the shallow boron profile is a proper design.Since ac power is proportional to CV2/T,he power dissipa-tion is considerably larger for the LDDdesign due to the highervoltage and higher performance. Therefore, power imitationsand power-delay tradeoffs of a particular design must be con-sidered in evaluating the net performance improvement.V. DISCUSSION ND CONCLUSIONS

I t has been shown that the LDD structure improves break-down voltage, hot-electron emission, and short-channel thresh-old effects to allow a design at 8.5 V with a minimum source-drain spacing of 1.2p while a conventional device s limitedto5 V and 1.5 pm. Experimental devices have been made toverify the designs; however, the reproducibility of the processdescribedhas not beendemonstrated.Further echnologydevelopment is necessary. The resulting DD ircuits areprojected to be almost two times faster. The power, of course,increases because of the higher voltage and speed, and mustbe considered in chip designs.An additional advantage of LDD is that the increased supplyvoltage increases the stored charge in a dynamic memory cell

byabout 1.7imes.This anallow maller cells withoutsacrif icing signal voltage to thesense amplifier.The design conceptsandapproachdescribed n hispapercanalso be applied to the designof anLDD device with areducedsource-drainspacing for use with ascaledprocess(smaller dimensions)whilekeeping thepowersupplycon-stant, e.g., at 5 V. Thiswouldhelp to alleviate the factorssuch as subthresholdcurrents, IR drops,and RC timecon-stants which cause departures from dealized scaling.

REFERENCES[ l ] T. H. Ning, P. W. Cook,R. H. Dennard, G. M. Osburn, S. E.Schuster,and H. N. Y u, 1 pmMOSFETVLSI technology:Part V -Hot-electrondesignconstraints, IEEE J . Solid-stateCircuits, vol. SC-14, pp. 268-275, Apr. 1979.[2] P. E. Cottrell, R.R. Troutman,and T. H. Ning, Hotelectronemission inn-channel GFET s, IEEE J . Solid-StateCircuits,[3] T. H. Ning, C. M. Osburn, and H.N. Y u,Emissionprobabilityof hot electrons from sil icon into silicon dioxide, J . Appl. Phys.,[4] S. A. Abbas and R.C. Dockerty, Hot-carriernstabilitynIGFETs, Appl. Phys. Lett., vol. 27, pp. 147-148, 1975.[5] H. Hara, Y . Okamoto,and H. Ohnuma, A new nstabili ty nMOS transistors caused by hot electron and hole njection fromdrain avalanche plasma into gate oxide, J apan. J . Appl. Phys.,[6] J . M atsunaga and S. K ohyama, Evidence formpact-ionizedelectron njection in substrateofn-channel MOS structures,Appl. Phys. Lett., vol. 33, pp. 335-377, 1978.[7] P.K. Chatterjee, VLSI Dynamic MOS design constrains due todrain nducedprimaryand econdary mpact onization, inIEDM Tech. Dig., pp. 14-17, 1979.[8] S. K ohyama, S. Mimura, and H. I izuka, Non-thermal arriergenerationn MOS structures, n 11th Con8 on Solid-state[9] R. H. Dennard,F. H. Gaensslen, H.N. Y u, V. . Rideout, E.Devices-Tokyo,p. A-2-2, 1979.Bassous, and A. L eBlanc,Designof on implanted MOSFETswithverysmallphysicaldimensions, ZEEE J . Solid-State Cir-cuits,vol. SC-9, pp. 256-268, Oct. 1974.[lo] R. H. Dennard, F. H. Gaensslen, E. J . Walker, and P. W. Cook,1pmMOSFETVLSI technology:Part 11-Device designs andcharacteristics for high-performance ogic applications, IEEE J .Solid-state Ci rcuits,vol. SC-14, pp. 247-255, Apr. 1979.[ l l ] H. N. Yu, A. Reisman, C. M. Osburn,and D. . Critchlow, 1pmMOSFETVLSI echnologyPart -Anoverview, IEEE J .Solid-state Cir cuit, vol. SC-14, pp. 240-246, Apr. 1979.[12] K. Saito,T. Morase, S. Sato,and U. Harada, Anew hortchannelMOSFETwithightlydopeddrain, DenshiTsushinRengo Taikai (in Japanese), p. 220, Apr. 1978.[13] T. Y amaguchi, M. L. Lust, S. Ragsdave, and S. Sato, Submicronchannel MOS-IC technology, n ZSSC Dig. Tech. Papers, pp.

[14] P. E. Cottrell and E. M. Buturla, Steady state analysisof ield

V O~.C-14, pp. 442-455, A pr. 1979.V O ~.48, pp. 286-293, 1977.

V O ~. , pp. 1103-1112, 1970.

82-83, 1979.effect transistors via the finite element method, in IE DM Tech.Dig., pp. 51-54, 1975.151 D. A. Antoniadis, S. E. Hansen, and R. W. Dlutton, SUPREM II -Aprogram for IC rocessmodeling and imulation,StanfordElectronics L ab. Tech. Rep. 5019-2, 1978.161G. W. Mahoney, A. J . J imenez, H. Quassemzadeh, T . R. Scott,W. T. Weeks, and D. A. Mehta, A statistical analysis program forcomputer-aidedircuitesign,n Dig. Tech. Papers (IEEESoutheast-Conf.), p. 01-1, 1973.171 K. Ohta, K. Y amada, K. Shimizu,and Y . Tarui,Aquadruplyself-aligned MOS (SQA MOS): A new short channel high speedhigh density M OSFET for VLSI, n ZEDM Tech. Dig., pp. 581-584. 1979.[18] A. Grove, PhysicsandTechnology of SemiconductorDevices.New Y ork: Wiley, 1967, p. 193.[19] R. R. Troutman, VL SI l imitations romdrain nducedbarrierlowering, IEEE J . Solid-state Ci rcuits, vol. SC-14, pp. 383-391,Apr. 1979.[20] T. Toyabe, K. Yamaguchi, S. Asai, and M. S. Mock,Anumeri-cal model of avalanche breakdown n MOSFETs, IEEE Trans.Electron Devices, vol. ED-25, pp. 825-832, J uly 1978.[21] S. M . Sze, Physics of SemiconductorDevices. New Y ork: Wiley,1969, p. 113.[22] H. F.Wolf, Siliconemiconductor Data. Oxford, ngland:Pergamon, 1969.[23] H.N. K otecha, F. H. De La Moneda, and K. E. Beilstein, Char-acterization of short and narrow channel effects for CADI GFETmodel, inZSSCC Dig. Tech. Papers, pp. 42-43, 1977.

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