3DPackaging

Magazine on 3DIC, TSV, WLP & Embedded die Technologies

ISSUE N°24AUGUST 2012

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F r e e s u b s c r i p t i o n o n www.i-micronews.com

InDUSTry rEVIEWEquipment makers say tools are ready for initial volumes

of 2.5D/3DIC production

CoMPAny InSIGhTSekisui Chemical:

Reliability innovation in large size & fine

pitch WLCSP

AnALyST CornErThe place of

“middle-end” in the future landscape

of 2.5D / 3DIC chip-to-package

manufacturing

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Jean-Christophe Eloy,President & CEO,

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Jeff Perkins,President, Yole Inc.

grandepub_invensemse_v3_Mise en page 1 29/08/12 10:06 Page1

E D I T o r I A L

TAIWAN: The country of "virtual IDMs"and 2.5D/3DIC investments?

If you’ve paid attention to recent investments announced by major IC packaging subcontractors in Taiwan, it’s clear that "middle-end" infrastructure is entering a new phase of growth. Last year, the #6 oSAT player in the world, Powertech Technology Inc (PTI), was the first major packaging subcontractor in Taiwan to announce a significant investment of $400M into new middle-end infrastructure. The new factory will primarily serve memory and logic customers with flip-chip copper pillar wafer bumping services, but will also support Fan-in WLCSP customers, as well as 3DIC & TSV packaging. recently, Advanced Semiconductor Engineering (ASE) and Siliconware Precision Industries (SPIL), the world's leading packaging and testing houses, have set higher capex budgets for 2012 -- with heavy emphasis on expanding capacity for high-end packaging processes targeting advanced communications chips, such as wafer-level packaging, copper pillar bumping, through-silicon-vias (TSV) and 3DIC packaging. ASE has budgeted $800M million in capex for 2012, with 30% to be invested solely in new equipment for flip-chip packaging, while SPIL estimates capex of $580M in 2012, a 50%+ jump compared to 2011.

It’s clear that Taiwan is likely to be strongly impacted by the move towards the 2.5D/3DIC business. Indeed, sensing that the development pace in the "More Moore" SoC area will fade as soon as the chip industry attains sub-28nm technology nodes, Taiwan Semiconductor Manufacturing Corporation (TSMC) is pushing aggressively toward the integration of chip packaging and assembly & test into its internal service offering. Today, TSMC is able to propose to its semiconductor chip customers a real "Virtual IDM" ecosystem which is currently being vertically integrated from front-end to back-end. This bold move into the chip packaging business by the #1 wafer foundry in the world has led to questions about the state of the traditional “oSAT versus wafer foundry” model in the IC industry. As a result, major Taiwanese packaging and test subcontractors such as ASE, SPIL and PTI are being pushed to redefine their role in the game by forging stronger collaborations with other wafer foundries (namely UMC and Global Foundries) and by following-up with significant investments in the back-end assembly & test area. These investments will be necessary to support a viable supply chain for the successful market commercialization of 2.5D /3DIC packaging technologies.

TSMC's entry into the IC packaging space will lead to a global push from the entire Taiwanese industry to invest in 2.5D/3DIC before the rest of the world does. This evolution, driven by a single company, will have many benefits for different players: fabless chip companies in the near future, as the supply-chain supporting the emergence of these complex 2.5D/3DIC modules will be developed broadly, and supported by multi-source parties; in a shorter term, equipment suppliers as these investments will be capital-intensive in terms of adoption of new advanced tools such as thermo-compression flip-chip bonder equipment.

This issue of 3D Packaging is fully dedicated to equipment and materials manufacturers for advanced packaging.

Jérôme Baron, Business Unit Manager, Advanced Packaging, Yole Développement

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A U G U S T 2 0 1 2 I S S U E N ° 2 4

PLATInum PArTnErS:

…TSMC's entry into the IC packaging space will lead to a global

push from the entire Taiwanese industry to

invest in 2.5D/3DIC before the rest ofthe world does...

• SEMICON TaiwanSeptember 5 to 7 – Taipei, Taiwan • SEMICON Europaoctober 9 to 11 – Dresden, Germany • MEPTEC: Roadmap for multi die integration - Known good dienovember 14 to 15 – Santa Clara, CA

E V E n T S

For more information, please contact S. Leroy (leroy@yole.fr)

A U G U S T 2 0 1 2 I S S U E N ° 2 4

GoLd PArTnErS:

INDUSTRY REVIEW 6 • Equipment makers say tools are ready for initial volumes

of 2.5D/3DIC production

• The rest of the needed TSV infrastructure develops as well

COMPANY INSIGHT • Sekisui Chemical: reliability innovation in large size & fine pitch WLCSP 12

• PVA TePla: Lessons learned from chip packaging 18

YOLE ASKS

• JSr packaging materials for 3dIC: a closer look 14

• Shinkawa TCB solution 16

• Cicor: 3d Packaging with the 3d-mId technology 20

ANALYST CORNER 22• The place of “middle-end” in the future landscape of 2.5d / 3dIC

chip-to-package manufacturing

WHAT’S INSIDE? 26• nemotek wafer-level camera

EVENTS REVIEW 28

C o n T E n T S

4 3 D P a c k a g i n g

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Please visit our website to discover the last top stories in Advanced Packaging:

> Hybrid Memory Cube draf t specifications issued by HMC consortium

> Major OSATs to expand capacities for 3DIC and Advanced Packaging technologies

> Awaiting a TSMC announcement on the Apple A6 processor: A closer look

(Courtesy of EV Group)

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• Nov. 14:Thin wafer handling

& processing

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3 D P a c k a g i n g6

Equipment makers say tools are ready for initial volumes of 2.5D/3DIC production

Equipment suppliers say chip makers are now buying some tools to aim for volume TSV production next year. Cost and yield of new

bond/debond processes still remains an issue in the minds of many, but even there new higher throughput tools and open platforms are making progress. The rest of the process flow, on which equipment suppliers have been working with customers for the last two to three years—and which is based on more established front-end technologies—looks reasonably ready for initial volume levels, though of course still has to climb the usual learning curve to get to real maturity for full industrial production of multi thousands of wafers per month. Equally encouraging is progress on the rest of less visible but vital enabling infrastructure, such as industry standards, design-to-manufacturing communication, and visibility towards a roadmap for scalability for next generation products.

The equipment makers of course say they’re ready. “In the last 2-3 years, every equipment maker has jumped on the 3D bandwagon and prepared themselves, so the transition for equipment is behind

us,” argues Thorsten Matthias, EV Group director of business development. “3DIC is happening now, the train is moving. Some companies are moving into production now and that will force other companies to adapt. All the unit processes are well qualified. The integration processes are qualified.”

“The industry is now raising its head from its development focus and looking 1 to 1.5 years out for cost effective production rates,” says rudolph Technolgies’ rajiv roy, VP business development, noting how attention has moved from r&D to high volume metrology issues.

Common platform and better throughput ease bond/debond, but challenges remain

Though the bond/debond process remains the least mature step, suppliers say new higher throughput tools, the open ZoneBond platform for room-temperature debonding, and rethinking the process flow to work around the steps most likely to cause yield issues from debonding.

Progress on higher throughputs, lower costs, metrology and industry infrastructure starts to move TSV technology into the fab.

Applied Materials and the Institute of Microelectronics (IME) Centre

of Excellence in Advanced Packaging.(Courtesy of Applied Materials)

“The main request we were getting from customers was for throughput. Past systems were really geared for R&D and pilot production, but there is a real need now for high volume manufacture,” says Matthias, noting EVG’s new platform that can bond/debond up to 40 stacks per hour, 2x to 3x the throughput of previous tools, thanks to a new handling architecture with a faster robot, and up to nine process modules instead of four. Also key for volume production is integrated metrology for better process control, to assure uniform adhesive thickness for controlled back grinding and reveal. The system scans the entire wafer with both optical and IR sensors, to inspect for layer thickness on both transparent and opaque layers, and for bonding defects and wafer warp and bow. Wafers found to have temporary bonding defects can be easily removed and re-bonded without much loss.

Another big step is the open ZoneBOND system, invented by Brewer Science, which treats the carrier to reject the adhesive coating in the central region, and accept it only around the edges. The adhesive on the edges can then be easily removed, by chemical or other methods, allowing the wafer to be lifted off on a film carrier at room temperature, without the thermal budget issues of the heat-based approaches. The process can be used with different adhesives and different tools, instead of each adhesive requiring its own specific process. “Now with ZoneBOND there can be competition among suppliers to develop better materials, and users can have a choice of the best suited material for a particular product,” he says. “We are seeing lots of movement in ZoneBOND, with real purchases for HVM now.” Although he notes that thermal slide-off processes are also ramping into high volume. “From my point of view, debonding is not the show stopper,” says Matthias. “We do still need better adhesives and more varieties, but now that we have standardized open platforms, there is room for different materials.”

Sesh Ramaswami, Applied Materials managing director, silicon systems group, 3D IC TSV and packaging, suggests there’s still some learning curve, for taking the unit processes of temporary bonding/de-bonding from development/pilot to high volume production capability. Applied Materials has been working with the industry ecosystem on processing bonded wafers on glass and silicon carriers in its integrated development line since 2008 to help move the industry along. “Some adhesive systems have made good progress recently, but we collectively need more work to get the appropriate technology working in an integrated manner at the right material cost and equipment throughput,” he says. “But the industry is coming to consensus that room temperature debonding is the must-have solution, and I am confident that there is enough work going on at many locations that good solutions will emerge.”

Yoshinobu Mitano, VP and general manager of Tokyo Electron’s 3DI Division notes that TEL’s recently introduced tools bring its high volume semiconductor production platforms to the specialty bonding/debonding niche, with established coating and baking, high-speed wafer transfer and inline macro inspection technologies. He concurs the key challenge remains room-temperature adhesive solutions.

Rethinking the process flow to optimize yield and throughput

Another possible path to more efficient HVM, Matthias points out, is now starting to appear from chip makers optimizing the whole process to limit the handling of thinned wafers and the steps most likely to cause yield problems. Instead of processing each die separately and then stacking them, Texas Instruments, for example, has reported an approach that attaches completed die to a partially processed wafer, which is patterned and thinned but still on the carrier, not yet released or bumped. The whole die-on-wafer-on-carrier stack is then overmolded to create a fairly rigid unit, which can then be de-bonded from the carrier and further processed like a standard wafer. The bumps are not added until the very last step, eliminating the potential for damaging them in the rest of the process. An approach like Tezzaron’s MEMS-like permanent bonding

of wafer-to–wafer stacks before thinning and backside processing also avoids all debonding issues.

There may be possibilities for bonding more chips at once as well. Initial processes will likely be chip-to-wafer, argues Matthias, for more flexibility in selecting die, and more flexibility in designing the process flow, although wafer-to-wafer remains the eventual goal for some products. Though the throughput and alignment of placing chips on the wafer has been limited,

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“We are seeing lots of movement in ZoneBOND, with real purchases for HVM now,”says Thorsten Matthias, EV Group.

Applied Materials and the Institute of Microelectronics (IME) Centre of Excellence in

Advanced Packaging.(Courtesy of Applied Materials)

EV Group’s newly-configured EVG®850TB/DB automated temporary bonding and debonding system built for high-volume 3D IC and TSV manufacturing. Equipped with an in-line metrology

system, this new HVM system doubles throughput of EVG’s previous-generation TB/DB tool to up to 40 stacks per hour. (Courtesy of EV Group)

matthias figures alignment will probably be possible down to about 2µm at high throughput. The process could be speeded up by first temporarily tacking all the chips or even multiple chip levels in the stack across the wafer, then bonding the whole wafer at once.

Suppliers say recent progress makes TSV process largely ready for initial production

Applied Materials reports that work on both TSV unit processes and integration to optimize tradeoffs between processes over the last several years has brought most of the via-making steps up to production readiness. ramaswami reports work with customers and consortia has improved etch rates by 30%-

50% with good sidewall quality, and improved throughput and reduced materials usage for physical vapor deposition (PVD) step coverage for quality barrier and seed. Executives at their recent analyst event said Applied had won some two-thirds of the TSV equipment decisions to date in its core etch, barrier/seed, plating and CMP offerings.

For the 5µm critical dimensions, 50µm depth vias (“5x50µm”) are typically used as a nominal structure for via-middle applications and 10x100µm dimensions are used for interposers. ramaswami reports Applied is working on the next stage of the roadmap, for 2 to 3µm dimensions, and in the last three years has qualified new materials and processes that have made copper protrusion

of the via much less of an issue than before. he notes there is more work to be done on grain size and texture for the next generation, although fill rates have improved by 20 to 30% and the TSV creation cost is down 30% to 40% from two or three years ago, for the via-middle scheme.

Tokyo Electron has been building up an integrated via process flow as well, with some innovative approaches at each step. Mitano notes TEL’s deep silicon etch system uses higher plasma density that he says improves mask selectivity and increases the etch rate to 15µm/min, to cut costs by about 30%. It uses vapor deposition polymerization (VDP) for the isolation step, with a batch furnace system for high throughput, at a claimed

step coverage close to 100%, better than conventional chemical vapor deposition (CVD). TEL says the VDP system also allows direct deposition of the copper seed layer, eliminating the usual Ti/Tin or Ta/Tan sputter barrier layer and its associated cost. The company is currently working on integrating PVD and plating technology from recently acquired nEXX Systems into its TSV flow. The nEXX electro plating tool processes two vertical wafers back to back in each 8-inch wide process cell, and can combine up to 20 of these modules on one tool, for what it claims is twice the throughput of some other plating tools. Mitano reports customer purchases for r&D continue, but are also entering the leading edge of pilot production.

Customer interest in metrology and inspection moves towards speed and process control for production

Interest in metrology and inspection is also apparently moving towards process control for higher yields, typical of technologies moving towards volume production, and bringing more traditional front-end approaches into the back end. roy reports rudolph is engaged with two of the top three oSATs on software that, in front-end fabs, uses metrology and inspection data to see how via depth and bump heights vary across wafers and across lots, to track trends and yields for run-to-run automated process control of their etching and plating processes. Suppliers also report more interest in faster approaches for production, whereas the speed didn’t much matter in the r&D stage. “People are now beginning to take an interest in faster options for inspection and metrology as their processes get more under control,” says roy, noting potential options such as inspecting only for voids that really matter at the top and bottom of the via with something other than x-ray tomography.

rudolph has added via depth metrology to its macro defect inspection tool, and a white-light-based system at lower cost than Ir to see through the wafer for alignment for bonding after back grinding and via reveal. other special lighting identifies oxides left on top of the nail that will prevent good contact. roy says full-wafer 2D 5µm nail reveal inspection, and 3D sampling, can be done at 20 wafers per hour.

There’s also progress on the inspection of the ever increasing numbers of ever smaller re-distribution layers, at10µm widths and spacing now, pushing towards 5µm, and getting up to 5 million or even 10 million bumps per wafer. Measuring the location, size, and height of each of those millions of bumps is several gigabytes of data, requiring a transition to a 64bit Windows operating system. And the processes are still too immature to go to sampling shortcuts. “We’re determining the difference between 4.5µm and 5.0µm bumps that all have to make contact between the die and the substrate, so there’s little room for error,” notes roy. rudolph has gone to laser triangulation for precise 3D inspection, improving throughput by making the spot smaller and scanning faster. optical and software filtering block reflection to allow reading both the top of the bump and the surface of the wafer as the bumps get closer together.

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8

TSV formation

Wafer thinning technologies Wafer handling

Wafer test / Final test

Dicing

Bonding / Assembly

“People are now beginning to take an interest in faster options for inspection and metrology as their processes get more under control,” says rajiv roy, rudolph.

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3DIC tool-box: synthesis of key challenges(Source: 3DIC & TSV Business Update report, August 2012, Yole Développement)

I S S U E N ° 2 4 A U G U S T 2 0 1 2

Lack of established materials, however, does slow metrology design. “We may get sample wafers to inspect and be told not to assume that the Sio2/Sin films after etch or reveal will be the actual materials used, which makes it very difficult to effectively model the index of refraction needed by the metrology system,” notes roy.

Also key to volume adoption: pathfinding tools and a path to scaling to the next generation

What’s really needed most now, argues Sitaram Arkalgud, SEMATECh Director of Interconnect, are better path finding tools, modeling and simulation tools with some sort of analysis cockpit, to enable device makers to take design inputs, technology inputs, and cost inputs to run quick estimations of different scenarios to find where there is the killer app of performance vs cost, and then go after the reference flow to get a better handle on the costs, performance, power and yields.

Then the industry needs to have some visibility into the path to scale to the next node going forward, always an important part of the cost/performance calculation for investing in a new semiconductor technology and new product family. SEMATECh has focused on direct copper-to-copper bonding as a key technology for scaling down the TSVs. Arkalgud says they’ve demonstrated good bonds of unpatterned blanket copper at 200°C at ~3wph, better than the current 400°C at 0.5 wph process. The simpler equipment required for the lower temperature could potentially reduce cost of ownership by 2X.

Impact on supply chain

The development of a volume TSV industry will likely shake up the supply chain to a degree. one clear change underway is the involvement of chip designers at fabless companies and IDMs directly with equipment and materials suppliers who once talked only to foundries and manufacturing fabs. “I have had far more communication with directors of packaging for fabless companies,” says roy. “It’s a totally different level of engagement. They are not taking anything for granted. They want to know what equipment will be used, how inspection and yield management software will be used, what are the issues they will face in reaching their yield and cost goals to enable particular applications.”

The disruptive technology is also bringing front end companies and what were once front-end technologies increasingly into the back end flows and customers. Applied sees chip interconnect technology coming together with back end bumping, and requiring more focus on chip-to-package interactions for temperature and stress. Applied has recently opened a development facility in Singapore to accelerate technology development, adding dedicated packaging tools and a team able

to act on feedback from the field as the industry ramps into production. “This will help move the industry forward,” says ramaswami.

TSV technology may also move niche suppliers from the MEMS and compound semiconductor sector into mainstream memory and logic markets. The DrIE and bonding companies that have perfected these technologies already for other industries argue that they have an advantage. “We were not a player in the memory market but now we are,” says Matthias. “It will be hard for the big companies to catch up in these areas.”

But most of the TSV process steps are based on quite mature existing front end semiconductor technologies, and the conservative industry is likely to stick with the familiar as much as possible to reduce risks, except perhaps for metrology. “In metrology the door is open wide for new entrants,” suggests roy. “There all bets are off.”

Paula Doe for Yole Développement

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Sitaram R. Arkalgud, Director of Interconnect, SEMATECHSEMATECh’s Interconnect program focuses on new interconnect technologies for tomorrow’s advanced computer chips. Arkalgud has more than 18 years of r&D and manufacturing experience in areas within the chip industry. Prior to joining SEMATECh, Arkalgud served as Infineon’s director and Project manager of the mrAm development

Alliance between Infineon and IBm. He also worked as a technology officer and product manager for Infineon.

Dr. Thorsten Matthias, Head of Business Development, EV GroupMatthias is responsible for overseeing all aspects of EVG’s worldwide business development. Specifically, he is focused on 3d integration, mEmS, LEds and a number of emerging markets. Prior to this role, Matthias was director of technology of EV Group north America in Tempe, Arizona. he began his career with EVG in 2002 as the product

manager for the SmartView wafer bonding alignment system. Matthias received his doctorate degree from Vienna University of Technology with a thesis in solid-state physics in 2002.

Sesh Ramaswami, Managing Director, Strategy Silicon Systems Group, Applied MaterialsMr. ramaswami has more than 25 years of semiconductor industry experience. over the past 15 years at Applied Materials, he has had varied technical and business experience in product management and product development and advanced materials development.

Prior to joining Applied materials in 1994, he had thin film process development responsibilities for seven years at Advanced Micro Devices and four years at national Semiconductor.

Rajiv Roy, Vice President of Business Development and Marketing Director for Final Manufacturing, Rudolphroy was President of STI following 18 years in business development and inspection applications at T.I. he has several patents and papers related to inspection. he has an mA, marketing and mS in Computer Science from the univ. of Texas and a BSEE from

Indian Institute of Technology, Kanpur.

2D defect detection is a reality for high volume manufacturing. This example shows nail reveal defects. Challenges include warped bonded wafer chucking, aligning on the wafer with no fiducials on the back-side after grind, and correlating front to back-side. (Courtesy of Rudolph)

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The rest of the needed TSV infrastructure develops as well

Bringing a radical new technology into volume production takes more than just the right process equipment. It also takes

development of the wider infrastructure that typically supports industrial production—from running the initial products to really figure out the volume manufacturing issues, to bridging the communications gap between fabless chip designers and manufacturing technologists to match process to product needs, to forging industry manufacturing standards to bring down costs.

The announcement of real products is of course the best indication of 3D technology approaching readiness for volume production. Most encouraging recent development is now having two potential front runner products, says Sitaram Arkalgud, SEMATECh director of interconnect, pointing to the FPGA products on 2.5D interposers and wide I/o memory. “This first true high volume runner should really teach the market a lot about cost and impact a lot of the ecosystem,” he notes. “The Xilinx FPGA announcement highlighted the benefits for one technology, so people could see how they might be able to use it,” concurs Sesh ramaswami, Applied Materials managing director, silicon systems group, 3D IC TSV and packaging. And the potentially very high volume wide I/o memory expected to start production next year would be a major step, perhaps 2 or 4 3D DrAM stacks in reasonable wafer volume, projected as possible by the end of 2013.

Also crucial is that the design community is talking to the process equipment guys, something the semiconductor industry in general has long talked about but seldom actually done. ramaswami notes that it is crucial to continue active discussion between the design and the process equipment communities. “The designers need to know what the processes can do, and the process community needs to know whether the designers can make use of the process solutions under development,” he says, noting that bridging this gap is important to drive adoption of TSV technology for specific applications.

“The fabless companies have been one of the major driving forces accelerating the adoption of 3D, who’ve brought all the parties to one table, pushing standards and forcing players to a solution. They’ve taken a major role in building the

supply chain and accelerated the development,” concurs Thorsten Matthias, EV Group director of business development. Another enabler is the major progress that’s starting to be made in industry standards. “one huge help was JEdECs recent standard for wide I/o DrAM format and pitch, so companies at least no longer all have different layouts. That’s the most significant step in recent memory,” quips rajiv roy, rudolph Technologies VP business development. Also important has been the progress in developing SEMI manufacturing standards for 3D packaging, which is forging consensus for common solutions for basic infrastructure, such as thin wafer transport, material property characterization in 3D stacks, and metrology, now getting the needed broad industry involvement of leading players to drive this forward.

SEMATECh has focused on pushing development of standards as one of the most useful efforts it can make for its chip making members to help develop the industry, putting effort into working with the various organizations across the flow from design (Si2) to process (SEmI) to product (JEdEC) to help make sure that the parts all work together. It is supplying its staff experts to the committees, supplying wafer banks as needed, and maintaining a public wiki that tracks all the 30-some standards efforts underway, that’s getting 50-60 unique hits a day (www.wiki.sematech.org). “We’re helping to grease the skids,” says Arkalgud.

Paula Doe for Yole Développement

There’s encouraging progress on communication between design and manufacturing, and on industry standards for 3D manufacturing.

“The designers need to know what

the processes can do, and the process

community needs to know whether

the designers can make use of the process

solutions under development,”

explains Sesh ramaswami,

Applied Materials.

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C o M P A n y I n S I G h T

Reliability innovation in large size & fine pitch WLCSP

WLP market

Wafer-level Chip-Scale-Package (WLCSP) has been widely used for mobile phone applications, such as analog, wireless connectivity, CMoS image sensors, and others. Especially, WLCSP is increasingly used to package wireless basebands or rF transceivers resulting in sizes larger than 5 x 5 mm2. Wireless handsets increasingly shift to smartphones, which require many functions and advanced features in a size -limitedly confined environment. moreover, 4G high speed communication services like Long-Term-Evolution (LTE) started, imposing high data bandwidth between the silicon components inside the phone. WLCSP combines the advantages of low parasitic high bandwidth Ios with miniaturization. Therefore, it is perfectly adapted to the phone evolution. however, any package change has to conform to the challenging reliability standards.

Let’s take the example of baseband integrated circuits: they are getting larger due to the multi mode LTE requirements for smartphones. on the other hand, the battery capacity on LTE smartphones needs to be made larger due to the very level of power consumption of LTE web browsing, and large batteries mean a constrained space for component assembly. So the challenge in this case is “how to package size-increasing LTE baseband ICs with WLCSP without compromising the assembly reliability so as to reduce the board assembly area for the battery”? Sometimes, in order to ensure the package assembly area, some small WLP devices are integrated into one large size WLCSP which has more I/o pads. In larger size WLCSP, due to the difference in coefficient of thermal expansion (CTE) between the silicon die and PCB, more thermal stress is generated on the outermost solder joints. In addition, the solder ball

pitch of WLCSP devices tends to decrease as well and thermal reliability is a great concern due to the smaller solder joint area. underfill is a way of improving the reliability, but board assemblers are reluctant to use underfill to keep the possibility to rework the packages and assembly. The reduction of the use of underfill material is also one of the motivations. Moreover, there can still be reliability issues with underfilling, due, for example, to improper underfilling between all the solder bumps. The development of high reliability WLCSP solutions without underfill for increasing die sizes becomes critical. Key parameters to achieve this are adequate material selection and design rules.

Plastic cored solder ball

A unique plastic cored solder ball (PCSB) developed by Sekisui Chemical Co., Ltd., brand-named ‘Micropearl SoL’, gives mainly two advantages for packages by the size-controllable and stress-absorbent flexible plastic core, stand-off controllability and high reliability. Thanks to the high reliability, it has been used commercially for WLCSP for analog devices and for CBGA. It has over ten year’s history in various markets, proving that there are no significant differences of usage or of properties such as electric performance between the PCSB and the solid solder balls. recently the target applications have expanded. PCSB has been evaluated not only for WLCSP but also for 3D-PKG, such as PoP designed for application processors and 3D-WLP designed for CMoS sensors, since plastic core is very effective in keeping a high and controlled stand-off height between the die and the PCB. moreover, PCSB is being strongly demanded in large size Si-BGA designed for rF modules and CBGA designed for image sensors.

Hiroya Ishida, Chief Engineer,Sekisui Chemical

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Cu

Core

SnAg solder

Ni

(a) Conventional Type

Ni Barrier layer

Doped metal-X

Cu

Core

SnAg solder

Ni

(b) Advanced Type

Figure 1: Illustrations of PCSB. (a) Conventional PCSB, (b) Advanced type PCSB.(Courtesy of Sekisui Chemical)

new plastic cored solder ball must achieve the larger size package design than ever, which enables to integrate functions into 1 package.

Some packages mounted with PCSB require the same assembly performance without solder paste on the PCB side during the package rework process. Throughout this rework process, a defective package is removed from the PCB and a bare package is re-assembled without solder paste, due to the difficulties of re-printing it on the PCB. In this case, we recommend the thicker solder type of PCSB, which, unfortunately, showed lower reliability than the conventional solder thickness PCSB, since it decreases the joint flexibility. Thus, reliability of the thicker solder PCSB solution needs to be improved.

Sekisui recently developed an advanced type of PCSB in order to achieve higher reliability and high assembly performance without solder paste in large size packages. Figure 1 shows a conventional PCSB and an advanced type PCSB including two new technologies. The Nickel barrier layer is expected to prevent copper diffusion and improves the reliability. The doped metal-X on the solder surface is incorporated into the solder, which is useful to form a finer intermetallic compound (IMC) in the electrode interface. The finer IMC has good anchor effect to the solder connection, which is also expected to improve reliability.

Board level temperature cyclingreliability in large size & fine pitch WLCSP

Sekisui evaluated board level temperature cycling (TC) reliability performance of PCSB with a large size Fan-in WLCSP (10.2mm x 10.2mm) of fine pitch (0.3mm ball pitch). Daisy chain was used for this PCSB characterization. The die thickness was 300um. The solder bump UBM size was 150um, it was electroplated Cu. Ball mounting was conducted in two rows of peripheral. The dimensions of the PCB were 132mm x 77mm x 1mm. The PCB consists of FR-4 material. The PCB pad design was solder-mask-defined (SMD). The solder ball pad size and the solder mask opening size were 250 and 200um, respectively. The PCB surface finish was organic solderability preservation (OSP). PKG assembly was conducted using an SAC305 solder paste.

In experiments, we conducted board level TC with different layouts of PCSB, in addition to metal-based solder balls. In the only thicker solder type of advanced PCSB, package assemblies were conducted without solder paste. Table 1 shows the PCSB layouts used in this test.

TCT was conducted in accordance to JEDEC specification JESD22-A104D (Condition G). The temperature cycle range was from -40°C to 125°C. The Weibull plots of the test results and failure modes are shown in Figure 2. The TC reliability of the advanced PCSB is over 300% higher than traditional solder spheres SAC305.

Conclusion and roadmap

The new PCSB technology achieved excellent reliability without underfill even with large size and fine-pitch WLCSP devices, and proved that it enables design layouts which could never have been realized before. In addition, the thicker solder type version of PCSB allowed for package assembly without solder paste and showed excellent reliability as well, which widens up possibilities of WLCSP usage. Sekisui pursues PCSB technologies continuously so that it enables highly versatile packaging design. In addition, monthly production capacity will be strengthened from current billions of pieces. Thanks to the increasing production volumes, cost competitiveness will be reinforced. Sekisui is looking for partners to collaborate with a new package creation.

www.sekisuichemical.com

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Hiroya Ishida, Chief Engineer, Sekisui Chemical He has more than 9 years of experience in developing metal coated plastic core for LCD and the semiconductor industries. He is in charge of product design and marketing research. Recent his interest is the development of high reliable plastic cored solder ball, in order to enable larger size package design.He has ME degree in chemistry from Tokyo Institute of Technology, Tokyo, Japan.

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Figure 2: Temperature cycling test Weibull plot. (Courtesy of Sekisui Chemical)

PCSB Type Solder Type Diameter Core Cu Solder PKG assembly

Conventional 200-20 Conventional 200µm 150 µm 5 µm 20 µm using solder paste

Advanced 200-20 Conventional 200µm 150 µm 5 µm 20 µm using solder paste

Advanced 210-30 Thicker 210µm 140 µm 5 µm 30 µm without solder paste

Table 1: Layout of plastic cored solder ball (PSCB). (Courtesy of Sekisui Chemical)

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JSR packaging materials for 3DIC:a closer look

We recently had the opportunity to speak to James Chung, JSr program manager and take ”A Closer Look” at their offerings for advanced packaging.

Yole Développement: James before we start, how about a little background on your career and what your role is today at JSR.

James Chung: I first worked as an engineer in the nuclear industry doing projects for Department of Energy and nASA after my graduation from University of Illinois at Urbana-Champaign. In graduate school at UCLA, I majored in physical chemistry. I started my 6 year semiconductor career at Intel as a lithography process development engineer. I then moved to South Korea doing business development at Cheil Industries. Since 2010, I have been at JSr focusing on packaging and display technologies.

YD: 2.5/3D is currently a very active area. James exactly what are JSR’s product offerings for a 3D TSV process flow?

JC: We currently offer photosensitive ELPACTM

WPr dielectric materials and ELPACTM THB thick photoresists for plating but we also have other materials such as temporary bonding and permanent bonding materials under development. our thermal slide temporary bonding materials are

in the final stages of development and we are also actively working on developing non-thermal slide temporary bonding materials since the market is demanding other types of de-bonding materials as well. We are also developing new permanent adhesives for 3D applications.

YD: What other applications are your thick resists and the permanent dielectrics finding acceptance in?

JC: our acrylic based negative tone THB resists, which are available in the thickness range of 5 – 90 um, are seeing use in applications including rDL wiring, copper pillars, and bump plating. We also have THB products that are designed for micro bumps to give better adhesion by providing ~1um undercut so that when Cu pillars are formed, they have ~1um of foot around the bottom of the pillars. Although we traditionally have only provided negative tone THB products, we have been developing chemically amplified positive tone photoresists and sampling at IDMs. We expect these products to be in the market in the near future.

our WPr permanent dielectrics have seen application in WLCSP where high resolution, low residual stress, low cure temperature, and low shrinkage are needed. As higher performance becomes necessary for passivation and rDL applications, we see more and more companies moving to high performance epoxy type materials and we expect this trend to continue as 3D WLCSP proliferates. We also have new WPr products under development that will provide better characteristics such as higher elongation and lower residual stress than our current WPr products. Whether for fan-in, fan-out, or rDL for TSV applications, we feel our THB and WPr products are well positioned to take advantage of the industry’s transition to materials that enable 3D WLCSP.

YD: We have heard that JSR is developing a temporary bonding adhesive and a permanentadhesive for stacking chips. What can you tellus about these products?

JC: We have been actively involved in developing temporary bonding materials for several years. As you know, there are different types of bonding/

Japan Synthetic rubber (JSr) was established in 1957 to produce rubber for automobile tires. In the mid 1970s JSr entered the electronics materials market. Although traditionally known for its front end semiconductor processing and LCd fabrication materials, JSr has been making inroads into the packaging industry of late.

James Chung,Program Manager,JSR Micro

JSR products for typical 3D process flow. (Courtesy of JSR Micro)

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de-bonding techniques and depending on which technique is employed, the materials being used are different. In our opinion, thermal slide debonding technique will be the first technology utilized in the mass production because of the industry’s familiarity with it and its ease of implementation.

JSr’s thermal slide debonding materials, exemplified by TA-S101 and TA-S102 utilizes dependence of shear strength on temperature. During the debonding process, asthe temperature of the temp adhesive increases, the shear strength decreases to the point where the separation of the processed device wafer and carrier wafer can be accomplished without causing damage to the structures on the device wafer and carrier wafer. our materials are designed with a debonding temperature to be ~ 20 degrees above the bonding temperature.

however, as you know, there is no clear leading technology in this area and we are also developing materials for other debonding techniques since the market demands other material types as well. The area of temporary bonding technology development is very dynamic and in order for a technique to be successful, collaborative efforts will be required between IDMs, oSATs, materials, and equipment companies. JSr is actively involved with other companies on such programs. Also in development are permanent adhesives that can serve the function of underfill. These may be photosensitive or thermo-compressive only. These may be photosensitive or thermo-compressive. Like temporary bonding materials, this area of development is also very fluidic and we are investigating different techniques and trying to understand the direction in which the overall trend is headed.

www.jsrmicro.com

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JSR thick resists ELPACTM THB. (Courtesy of JSR Micro)

Type Grade Viscosity Thickness Application remarks

negative

THB-111n 500mPa-s 5-15 µm Cu wiring Commercial

THB-126n 1,750mPa-s 20-40 µm Au-bumpCu wiring Commercial

THB-129n 1,750mPa-s 20-40 µm Cu pillarmicro-bump

Micro bump(new grade)

THB-151n 3,900mPa-s 30-70 µm Solder-BumpCu pillar Commercial

THB-160n 6,000mPa-s 40-90 µm Cu pillarmicro-bump

high thicker grade

(new grade) An increasing number of polymeric materials are used in WLP applications

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Polymeric Materials

for 3DIC & WLP Applications

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Shinkawa TCB solution

Yole Développement: Although a known equipment manufacturing company for the semiconductor industry, Shinkawa never actually supplied any TCB flip chip bonders. Can you please explain to our readers the histroy of Shinkawa as an equipment supplier, and how you intend to prenetrate the competitive market of flip chip bonders today ?

Kazuhiro Fujisawa: Shinkawa Ltd. was founded in 1959 at the western part of Tokyo, Japan. We introduced the first fully-automatic wire bonder in the world in 1977 and since then, we have been leading the industry as an assembly equipment manufacturer in the semiconductor industry. As for flip chip bonders, we developed a model for LCd drivers in 2003 and achieved bonding accuracy of +/-2um. In 2008, we officially announced entry into the TCB flip chip bonder market. It was the time when many PKG diversified, mainly in the mobile and tablet-related products, and there was a high prospect of adopting the flip chip process into 2.5D and 3D. We are now focusing on the TCB process and aiming at market penetration with a high precision flip chip bonder. under the TCB process, highly-precise alignment technology and very fine force control plays a vital role in successful bonding. We had established such technologies as our core competencies though wire bonders and flip chip bonders for LCd drivers, and we received a good reputation from the market. When it comes to wafer thinning, we have thin die pick-up capability down to 30um by utilizing our own die bonder technology for memory devices. Shinkawa is now taking a new step into TCB flip chip bonding with our combined technologies as an assembly equipment manufacturer.

YD: Regarding the 3D vertical stacking of integrated circuits, do you expect the "chip to chip" (C2C) or the "chip to wafer" (C2W) to prevail ?

KF: nCF (non Conductive Film) is the premise of C2W process. It is difficult to dispense liquid agents like nCP (non Conductive Paste) and CUF (Capillary underfill) onto wafers without any extrusion to adjacent dies, due to the small gap between dies. on the other hand, conventional technologies of nCP and CUF dispensing are possible in the C2C process. however, C2C requires preliminary die sorting which is disadvantageous in terms of productivity and production cost. Simply put, the improvement of film materials will determine the practical use of C2W and C2W becomes commercially viable. We understand that nCF yield and productivity issues are improving as nCF technology advances. Therefore, we assume that C2W will become the mainstream process in the future.

YD: Thermo compression bonding (TCB) is gaining traction across the industry. Can you please explain to us why ?

KF: There are three reasons. The first one is that the high bandwidth demands of high-speed processors mandate changing from wire bonding to a flip chip process. Mobile processors and DrAM fall under this category. The second reason is that these devices will migrate to the TCB process as it is cheaper than the conventional C4 process in terms of material cost. The third reason is that there are demands from current C4 to convert into a TCB process. Processors for PC, GPu, and large-scaled FPBGA fall under this category. It is widely known that die stress occurs due to the CTE mismatch between substrate and dies during C4 mass reflow, which can lead directly to die damage. Under these circumstances, the stress-friendly TCB process is being implemented for some devices to replace the C4 process.

YD: Some industry players argue that Non Conductive Paste (NCP) adhesive does not allow yet for optimal yields. What is your opinion of what the ultimate TCB flow will be, with respect to underfills ? Do you work upfront with underfill material suppliers ?

KF: Though we noticed some of those opinions, we still think that nCP will become the C2S mainstream process in most of the devices. on the other hand, we suppose that the high-pin count devices will go for TCB and CuF in order to increase

Shinkawa has released new Flip Chip Bonder for TCB process which is based on Shinkawa unique technologies proven by Wire Bonder, die Bonder and CoF Bonder.

Kazuhiro Fujisawa, Assistant General Manager, Flip Chip Technology Department, Shinkawa Ltd

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TCB FC bonder - Model LFB-1100. (Courtesy of Shinkawa)

bonding reliability. nCF will be used for C2W. In light of these circumstances, we decided to employ a modular system design for our machine, which enables our customers to choose whatever configuration they like. They have the option to use our in-house developed pre-dispenser and CUF, but have the option also to combine with their own specified modules.our modular system gives our customers high flexibility in order to deal with various processes and needs. The TCB flip chip process, especially as it extends to C2W technology, requires close collaboration between equipment and material makers. We have begun to exchange technical information with our material suppliers and seek to expand into extended collaboration.

YD: Which applications, in your opinion, are first going to massively adopt TCB ? Will we see high volume TCB for chip to substrate flip chip bonding before assembly of the 3D silicon stacks ?

KF: In our opinion, the first application will be mobile-related. We take it that the C2S process will remain predominant over 3D silicon stacks at the first stage. A short while

later, a large market will develop for memory cube and 3D stacked processor products. Then the C2W process will be applied to memory cube technology. DrAM and PC processors and peripheral devices will be the last to show up as a C2S process. There are many predictions about timing and it is difficult to foresee specifically but we suppose that the overall trend will follow as stated above.

YD: What added features differenciate a good TCB bonder from a C4 flip chip bonder ?

KF: There are several key technologies in order to succeed with a TCB bonding process: 1) highly accurate positional alignment

technology at sub-um level.2) Fine Z-force control.3) rapid heat-up and cool down technology.4) Auto tracking function of z-height positional

deviation during heat-up expansion and cool down contraction.

5) Traceability to realize stable bonding quality by process monitoring control.

6) Coplanarity adjustment system for tool and bonding stage.

7) nCP contamination detection on tool.

YD: Where do you locate the market of flip chip bonders - and more specifically to TCB bonders - on a scale ranging from high-end and high value to high volume commodities ?

KF: TCB will be applied for devices such as high-speed processors and their peripheral devices including memory. For example, processors for automotive applications do not require such high-speed processing as PC or mobile and wireless. A conventional wire bonder process will do for these devices.

www.shinkawa.com

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Kazuhiro Fujisawa, Assistant General Manager, Flip Chip Technology Department, Shinkawahe has worked on the semiconductor equipment electronics and software engineering more than 30 years. In the age of LoC package DrAM, he contributed to the spread of SEMI SECS wafer mapping. He had a responsibility of the world first conventional die bonder for 300mm wafer, which was released on '2001. he has been in charge of TCB FC bonder development from '2008.

C

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186X132.pdf 2012/8/2 10:36:58 PM

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Lessons learned from chip packaging

Beyond its use in resist ashing applications, the single wafer microwave (MW) plasma technology paves its way into typical chip

packaging processes on wafer level, where dies are no longer placed on, and wire bonded to substrates or leadframes, but stacked and populated on interposers or processed wafers with known good die. In chip packaging, plasma is used as a mean to pre-condition the die and carrier to achieve high yield and reliability for subsequent processes. MW plasma with its ability for chemical surface modification is common standard in chip packaging today when oxide removal of contact pads prior wire bonding, surface activation prior mold or prior Flip Chip underfill is required. In this context a growing field of interest is the plasma oxide removal for thermo compression bonding (TCB) to improve Sn-Cu wetting, reliable bump interconnection and electrical yield as well as for improved Cu-Cu bonding.

With lessons learned from chip packaging on oxide removal of bond pads for copper wire bonding, PVA TePla is one of the few companies in the world that can merge typical semiconductor packaging process requirements with front end equipment design for wafer level processes with its stringent demands on particle count, scalability and a strong focus on cost of ownership.

Typical flip chip processes require plasma prior underfill to facilitate better flow and adhesion, thus improving yield and reliability by preventing void formation and delamination (Fig. 1). The chemistry behind is based on hydrophilic surface modification which happens within seconds of exposing the wafer / die surfaces to radicals by forming new chemical groups thus giving the surface a polar nature and providing optimum adhesion properties in low pressure plasma. Under prolonged plasma treatment the process will create volatile reaction products, such as water vapor and carbon combinations amongst others. These volatile combinations will be evacuated from the wafer environment via the chamber exhaust. The benefit of dry chemical cleaning is that all accessible surfaces will be exposed to the chemical reaction. This is particularly interesting since the chemically active radicals need to penetrate gaps / stand-off down to 10µm as required in today’s 3D IC developments at leading research centers[1]. The efficiency of mW plasma can be accounted to the higher electron density when comparing different plasma generation technology frequencies.

In substrate and lead frame applications the same process applies to improve flow and adhesion of mold compound. Whereas in the substrate and lead frame world batch systems are typically used to meet the throughput demand, processing populated 200 or 300mm wafers with mounted die will require single wafer handling and plasma treatment (Fig. 2) for yield and reliability enhancement in volume production.

The GIGAfab A is equipped with a unique planar MW plasma source, providing high electron / radical density. In standard configuration it is equipped for cleaning and activation process gases such as Ar,

With the introduction of the plasma system GIGAFab A200/300 photoresist removal and descum technology for 3D IC and Wafer Level Packaging (WLP), field data at customer installations confirmed the expectation on throughput and uniformity for wafer bumping and rDL processes.

Helge Luesebrink, Head of Packaging Technologies, Business Unit Plasma Systems, PVA TePla

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Figure 1: Bump area of a flip chip device under the silicon die. (Courtesy of PVA TePla Analytical)

o2, and Arh2 mixtures. For etching and ashing in combination with Chemraz-seals, fluorinated process gases can be applied achieving high removal rates over a wide temperature range. The modular platform allows configuring the system for 200 or 300 mm wafers using open cassette as well as FoUP or SMIF load stations. The wafer chuck with lift pins for loading is thermoelectrically controlled from rT to 250°C. Plasma preconditioning becomes a must when interconnect reliability and yield is at stake.

References:[1]http://www.imec.be/ScientificReport/SR2011/1414090.html

www.pvatepla.com

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Helge Luesebrink, Head of Packaging Technologies, Business Unit Plasma Systems, PVA TePlahe received his Dipl. Ing. in polymer engineering in 1995 from the Polytechnical u., Wuerzburg, Germany, and his mBA in International Business in 2000 from Long Island U., ny, USA. he has held several management positions with semiconductor equipment manufacturers in the US, Asia and Europe and has published on optoelectronics, packaging and next generation lithography in Laser + Photonics, Solid State Technology Magazine, European Semiconductor, Journal of nanoscience, as well as numerous conference and seminar papers and presentations.

Figure 2: Single wafer conditioning in microwave plasma.(Courtesy of PVA TePla)

3D TSV chip market expected to grow 10 times faster

than semiconductor industry by 2017!

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3DIC & TSV Interconnects 2012 Business

Update

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3D Packaging with the 3D-MID technology

3D packaging Package on Package (PoP) or System in Package (SiP) are key technologies to realize high

functional integration into the smallest space. But PoP or SiP deals with packaging on chip level only. The chip itself has to be assembled to a substrate and this substrate in his turn has to be connected electrically and also mechanically to his environment. The solution for the 3D assembly und 3D connectivity is offered by the 3D-MID Technology (MID = Molded Interconnect Devices).In This Article the 3D-MID Technology and its benefits for mEmS packaging will be explained.

The 3D-MID technology, which is already applied in several connectivity solutions, is coming in increasing use for MEMS integration. 3D-MID allows miniaturization by the integration of mechanical and electronic functions in one part and so much more compact construction and much greater function density can be achieved. More and more applications involving electrical and electro-optical circuits are made using 3D-MID technology. Typical targeted applications are: Sensor packaging, LEd packaging, security casings, rFIDs and Antennas There are several possibilities to manufacture 3D-MID products, however, the 2S (Two Shot Molding) and LDS (Laser Direct Structuring) processes are the most widespread 3D-MID processes. hundreds of millions of mobile phone antennas are manufactured by 2S and LDS processes per year. In addition to the manufacturing of antennas, which consist only in 3D substrates (without electronic assembly), the 3D-MID technology, thanks to its capability to integrate mechanical and electrical functions in one module, unfolds its real strengths in applications with electronic assembly like MEMS packaging as well as LEDs.

3D-MID process steps

Injection molding

Plastic parts acting as substrates can be manufactured by a single shot injection mold (for the LDS process) of plastic material doped with a metal-complex. Material choice is done according to application requirements (e.g. Temperature, SMT capability etc.).

Two shot injection molded parts composite of tow plastic components, the first one can be plated (doped with Palladium), while the other material is inert and cannot be plated.

Laser structuring

After the injection molding the structuring of the layout on the plastic parts takes place by laser. A laser ray activates on the one hand the doped metal complex in the plastic material and on the other hand ensures a keying of the plastic materials on the structured areas.

Plastic debris emerging by the laser ablation process must be removed from the surface before metallization. otherwise debris can lead to over metallization of the surface.

Further treatment of the laser structured area is needed, if bonding or flip-chip on the final surface is required (ultrasonic- or thermo-mechanical stamping or Co2-cleaning). Such a treatment is need for smoothing rough areas/pads intended to be bonded.

Chemical plating

Standard layers for chemical plating are Cu/ni-P/Au. other layers are also possible. The plating process is the most sensitive process step in the 3D-MID manufacturing chain. More than 80 parameters have to be monitored and controlled, most of them even continuously. Bath parameters have to be adapted according to material type and part geometry. Electronic assembly

Electronic assembly on 3d-mId is similar to the PCB electronic assembly. Soldering, conductive adhesive, bonding and flip-chip are possible. A combination of mId on PCB or PCB on mId is also possible.

The greatest challenge in comparison with the PCB electronic assembly is the 3d positioning and fixing of the electronic components on the 3d-mId

The trend toward miniaturization and functional integration in the electronic industry is unbeaten.

Nouhad Bachnak, Director 3D-MID technology, Cicor

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3D magnet field sensor (Courtesy of Cicor)

during the assembly process. Sofisticated 3D-MID assembly machines are available on the market and the development in this sector is proceeding apace.

The high temperature during the soldering process is another challenge which has to be taken in consideration because of the different CTE (coefficient of thermal expansion) of the plastic subrtrate and the metall layer. however, this poses no problem provided the individual steps in the process are optimally adjusted with one another from design and molding making through laser structuring and metallization to the final assembled product. 3D-MID products used e.g. in automotive applications fulfill the highest automotive standard regarding reliability, withstanding the toughest environmental tests (> 1000 temperature cycles from -40°c up to 150°C).

Main drivers of the 3D-MID

The main drivers of the 3D-MID technology are: • miniaturization: opportunity to solve space

problems, e.g. in applications for automotive, medical, mobile application like mobile phones

• rationalization and system simplification: reduction of process steps, number of parts and mounting time

• Functionality: new additional functions possible due to various functional integration options, design flexibility and precision provided by 3D-MID

Benefits and potential useof 3D-MID

Following Figure displays the range of possibilities for using 3D-MID technology

Due to its capabilities regarding miniaturization and system simplification, the 3D-MID technology offers a real opportunity for MEMS applications. In particular for packaging, where positioning tolerances and the mechanical and electrical connection to the environment lead to high challenges, the 3D-MID technology provides the right packaging solution.

www.cicor.com

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Nouhad Bachnak, Director 3D-MID technology, Cicormr. Bachnak works since more than 5 years in the area of 3D-MID technology. he studied mechanical engineering at the St. Petersburg State Polytechnical University in russia and at the Luebeck University of Applied Sciences in Germany. mr. Bachnak started his professional career as development engineer in the automotive suppliers industry at Siemens VDo, followed by professional stations as project manager at Tyco Electronics and r&D Manager at Smith Group. Since 2011 mr. Bachnak is responsible for the world-wide 3D-MID activities of the Cicor group.

Cicor 3D-MID technology demonstrator (Courtesy of Cicor)

The Electronic Components and Technology Conference (ECTC) invites you to submit an abstract for presentations

and/or Professional Development Courses (4 hours). As the premier event in the semiconductor assembly industry, ECTC addresses new developments, trends, and applications for 3D integration, TSV, WLP, flip chip, materials, and other

integrated systems packaging topics.

We welcome previously unpublished, non-commercial abstracts in areas including, but not limited to:

Advanced PackagingApplied Reliability

Assembly & Manufacturing TechnologyElectronic Components & RF

Emerging TechnologiesInterconnections

Materials & ProcessingModeling & Simulation

Optoelectronics

Abstract submissions and Professional Development Course proposals for the 63rd ECTC are due by October 8, 2012. To submit, visit:

www.ectc.net

The 63rd ECTC

Call for Papers is now open!

Conference Sponsors:

May 28-31, 2013

The Cosmopolitan Hotel of Las Vegas

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A n A L y S T C o r n E r

The place of “middle-end” in the future landscape of 2.5D / 3DIC chip-to-package manufacturing

The sea change of finally bringing 3d into mainstream production will mean major challenges and opportunities for the supply

chain, as companies figure out where best to focus investment in this increasingly expensive value chain, and how to best organize the increasingly complex handoff from design to fab to assembly and test when few companies can do it all on their own. We expect the traditional pure play IDM vs pure play fabless/foundry/oSAT business models to become increasingly unsustainable in this ever more complex 2.5D/3DIC world.

IDMs may initially have the advantage as they develop and control the entire TSV flow in house, but with the increasing costs of building leading edge production facilities at 28nm nodes and below, plus the cost of developing all the increasingly complex new middle-end and back-end, assembly and test technologies, very few companies will have the product volume by themselves to generate a profitable return on that investment. To change the paradigm, more IDM fabs will get into the foundry business to keep these expensive facilities full, or will go fablite and outsource some of their production. Samsung LSI has been fabbing

Apple’s A4 to A5 processors entirely from wafer to die to package processing, and will be ready to support the more advanced middle-end processing 2.5D interposer and 3DIC packaging as well as soon as their foundry customers decide to move to this technology. Some IDM chip makers like SK-hynix and even Intel may look at opening complete front-end to middle-end to back-end processing services to some carefully selected outside customers as well, as the integrated production for big fabless customers like an Apple, Qualcomm or Broadcom could bring a lot of critical mass production volume in to their leading edge factories. With latest semiconductor fabs operating at 28nm and below costing almost $6 billion now, even the biggest players need more volume of good design wins to ramp production successfully and keep the fab full. now that Samsung and TSMC are offering end-to-end processing services from front-end, middle-end to back-end, the other players may have to follow the same integration strategy or reconsider their position in the value chain.

other IDMs may move into this integrated foundry business on a smaller scale. For markets such as ASICs for networking, automotive or industrial applications, it may make a lot of sense for some

As first 2.5d/3dIC high performance server and gaming applications start to come to market next year, launching the 3d TSV platforms toward a $38B rampup over the next five years, the supply chain will have to re-think its business models to compete smartly in this changing landscape.

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A U G U S T 2 0 1 2 I S S U E N ° 2 4

Jérôme Baron, Business Unit Manager Advanced Packaging,Yole Développement

Emerging 2.5D / 3DIC open ecosystems of “virtual IDMs”(Source: 3DIC & TSV Business Update report, August 2012, Yole Développement)

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IDMs like STMicroelectronics to provide moderate volume foundry production to this type of outside customers, supported by their internal CMoS and 3DIC lines in France as well as their specialty back-end processing in house.

Foundries, meanwhile, are figuring out how to integrate 3D TSV and 2.5D interposer processes and assembly, whether in house or by close cooperation with partners. TSMC has invested in its own high volume packaging capacity with latest in flip chip thermal compression bonding tools to become a full end-to-end supplier. As Apple has been trying to develop the supply chain to decrease its dependence on competitor Samsung, TSMC could get the next generation Apple business with this fully integrated 2.5D / 3DIC integration platform.

OSATs stake out claim on TSV business too

other foundries will need to find ways to collaborate more closely with oSATs to offer a “virtual Idm” solution, finding ways to work together to manage the hand off—and the sharing of the value and sharing the responsibility for module ownership and yield loss--no matter who does the middle-end steps. The oSATs meanwhile have been working to build up their own expertise in the increasingly more complex 2.5D/3DIC module assembly. The foundry/oSAT collaborative supply chains that draw upon the expertise of both the traditional fab and assembly field players appears in fact to be the choice of many of the first TSV products recently announced: Xilinx has said the most difficult issue for their FPGA- on- interposer was which manufacturing supply chain to use, but ultimately decided to maintain their relationships with both the foundry and the oSAT, and split manufacturing between TSMC and Amkor. Sony’s next game station logic-on-interposer will reportedly similarly be fabbed by Global Foundries, and packaged by a collaborating oSAT (probably ASE, StatsChipPAC, SPIL or again Amkor).

But collaboration isn’t easy. Though shipping the thin wafers from one production site to the other while they’re still bonded to carriers makes them relatively robust, it can be hard to determine whether a yield problem is from the bonding in one factory or from the de-bonding in the other, when the two companies have separate technologies and competing interests.

Some oSATs like ASE in Taiwan are developing their own 2.5D interposer substrate and 3DIC assembly technologies, but other packaging contractors may not all be able to match the high investment capabilities of the leading IDMs and wafer foundries now also going after this advanced packaging business. Most oSATs will have to be much smarter and focused in their investment, or perhaps find ways to serve systems makers directly with specialty, differentiating integrative packaging technology. nevertheless, the oSAT industry could potentially take over a significant part of the foundries’ 2D-SoC business, which is currently actually slowing down its pace of development and now moving to 3D-SiP integration of heterogeneous functions. The oSATs could potentially provide a more economically viable option for the assembly and re-integration of those 3D-SoC partitioned dies, by putting them on an 2.5D interposer substrate, for example.

Meanwhile, fabless companies such as Qualcomm, Broadcom, LSI Corporation or CISCo will need to add more processing expertise of their own, by working more closely not only with the foundries and oSATs, but even with equipment and materials suppliers as well, so they can best match designs to manufacturing process capabilities and standards to meet their cost versus performance goals.

With both the large front-end fabs and the major back-end assemblers adding competing middle-end 2.5D and 3DIC capabilities, we see only limited room for pure-play players offering only middle-end processes to be successful. Indeed, the intensely competitive middle-end space is almost a zero margin business, and is likely to remain low margin, as the major front-end and back-end players are supporting this new space to attract users to the rest of their much higher margin processing offering. In other words, wafer

foundries will integrate middle-end processes to their services, but will always make most of their margins in the profitable front-end area, while packaging subcontractors will also extend their offering to the middle-end in order to secure their business in the very profitable 2.5d / 3dIC back-end assembly and test business.

Taken alone, the back-end assembly and test space represents a clear opportunity for sustainable growth for major oSATs suppliers of this emerging 2.0 advanced packaging industry. By 2017, we estimate that the global 3D TSV semiconductors packaging, assembly and test market will reach about $9 billion market value. About $3.8B of this business will be from middle-end wafer processing activities, such as TSV etching, filling, wiring (BEoL or rdL), bumping, wafer-level assembly and wafer inspection. Meanwhile, the back-end assembly and test of such complex 3DIC modules will reach an impressive market value of $5.7 billion, including interposer substrate value, as well as assembly steps such as dicing; underfilling; die pick, flip & place; molding; final testing and BGA balling.

It is very unfortunate for start-up companies that this middle-end segment alone is unlikely to be a profitable business without tight integration with either the front-end or the back-end processing. We expect fully vertically integrated models such as emerging at Samsung and TSMC or collaborative models between wafer foundries and oSATs to emerge as the most successful solution.

www.yole.fr

Place of “middle-end” in the future landscape of 2.5D / 3DIC chip to package manufacturing

(Picture of value chain distribution by 2017)(Source: 3DIC & TSV Business Update report, August 2012, Yole Développement)

Jérôme Baron is leading the semiconductor packaging market research at yole Développement. he has been following the 3D packaging market evolution since its early beginnings at device, equipment and material levels. he was granted a Master of Science degree from InSA-Lyon in France.

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Nemotek wafer-level camera

The reflow compatibilities of WLCs provide a big advantage over traditional camera modules, since they can partake in the same

reflow soldering process used for assembling the other electronic components on a board. Nemotek Technologie

Founded in 2008, nemotek Technologie manufactures customized WLCs for portable applications. nemotek provides design, manufacturing and testing services for WLCs, as well as for Wafer-Level Packaging (WLP) and Wafer-Level optics (WLo).nemotek’s Wafer-Level Packaging and Wafer-Level optics products use technologies licensed by Tessera.nemotek operates a 12,000m² facility in Morocco, including a Class 10 clean room. Wafer-level camera

The camera is a fixed-focus VGA module integrating a Wafer-Level Packaged CMoS Image Sensor and Wafer-Level optics. The camera module is provided in a 3.7x3.3x2.4mm 21-pin package, compatible with reflow soldering.The WLP CIS die and the WL-optics die are integrated at the die-level using die attach.

The final stack is encapsulated into an epoxy resin.

Wafer-Level Packaging

The Wafer-Level Packaging is based on Tessera’s Shellcase® MVP solution. The Shellcase process was used in the previous Wafer-Level Camera we analyzed (the omnivision oVM7692), but it employed a redistribution of the CIS pads to the back side through the edge of the die, using a “T-contact” (Tessera Shellcase rT process). This time, redistribution is realized using Through-Silicon Vias (TSVs) to connect the bond pads of the die and the BGA interface on the rear face of the package.

The TSV manufacturing process used is very different from the typical TSV process, since tapered holes are etched into the Silicon wafer, as opposed to high aspect ratio holes. Therefore, the holes are made with low-cost/high-throughput equipment, instead of expensive DrIE equipment. In the same fashion, the TSVs are insulated with a thick, low-cost polymer deposited by electrophoretic deposition process, instead of thin Silicon oxide deposited by PECVD.

The lead used to connect the pads of the CIS with the solder balls consists of an aluminum/copper conductive layer and a nickel/phosphorus plating layer. The lead penetrates through the bond pad to form a circumferential edge contact.The CIS is protected by a glass carrier, sealed with an epoxy bonding process. Wafer-level optics

The wafer-level optics is a single wafer element, reflow compatible, based on Tessera's optimL™ solution. Two lenses made with a UV curable polymer are manufactured on a borosilicate glass wafer with a replication process. A plastic tool (likely

Wafer-Level cameras (WLCs) continue to gain in popularity, bolstered by the need for low-cost/small-size camera phones.

W h A T ’ S I n S I D E ?

"Nemotek’s wafer-level packaging and wafer-level

optics products usetechnologies

licensed by Tessera,"

explainsromain Fraux.

Nemotek wafer-level camera.(Courtesy of System Plus Consulting)

WLC encapsulated with epoxy resin.(Courtesy of System Plus Consulting)

Wafer-Level Packaging cross-section.(Courtesy of System Plus Consulting)

Glass carrier

Cavity Cavity wall (Epoxy)

Encapsulation(Epoxy)

TSVCIS

Solder ball

Polymeric passivation

Lead

200 µm

Romain Fraux,Electronics Cost Engineer,System Plus Consulting

romain Fraux is Project Manager for reverse Costing

analyses at System Plus Consulting. Since 2006, romain is in charge of costing analyses of MEMS devices, Integrated Circuit and electronics boards. He has significant experience in the modeling of the manufacturing costs of electronics components.romain has a BEng from Heriot-Watt University of Edinburgh, Scotland and a master’s degree in Microelectronics from the University of nantes, France.

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Polydimethylsiloxane - PDMS silicone) molded into a master is used to imprint the polymer lenses. Each master can be used to make a large number of PDMS tools, and each PDMS tool can be used to imprint a large number of lenses.

The lenses are covered with a thin anti-reflective coating (ArC). The two sides of the glass wafer also hold an Ir filter (consisting of layers of Titanium oxide sandwiched with layers of Silicon oxide) and an aperture made of Chromium layers.

The lenses wafer is separated from the image sensor by a Fr-4 spacer wafer (Glass-Fiber-reinforced Polymeric resin) which is etched using a standard, PCB-like mechanical drilling process.

Cost structure

The main benefit of working with nemotek is that it is a “one-stop shop” which provides a complete solution, from optics to packaging, thus eliminating overhead related to multiple subcontractors.

on the downside, nemotek uses optics and packaging technologies licensed by Tessera, and has to pay royalties for these.

To wrap things up, the complete Wafer-Level Camera assembly cost (without the CMoS Image Sensor) is close to 30 cents, which is very competitive compared to other previously-analyzed technologies from ST, Toshiba and omnivision. The Wafer-Level Packaging of the CIS remains the main cost driver, with ~50%.

www.systemplus.fr

Wafer-level optics cross-section.(Courtesy of System Plus Consulting)

CIS WLP Cost + Royalties

49%

WL-Optics cost + Royalties

30%

CIS/WLO Assembly &

Housing Cost 9%

Final test + Scrap (Omnivision)

11%

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Lens #2

IR filter

Lens #1

AP layer

Imaging Area with micro-lenses

Bumps

Glass wafer #2

FR-4 Spacer

Cavity

TSV Glass Wafer #2 (carrier wafer)

Housing

Wafer-level Optics

Wafer-level Packaging

CMOS Image Sensor

Nemotek WLC structure & cost breakdown. (Courtesy of System Plus Consulting)

FR-4 FR-4

FR-4 FR-4

Lens #2

Lens #1

Glass wafer with lenses &IR filters

WLP CIS

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E V E n T r E V I E W

62nd ECTC addresses microelectronics industry needs

The conference kicked off on May 30th with 16 professional development courses, as well as a special session on the changing role

of the Packaging Foundry chaired by raj Pendse of STATS ChipPAC; a panel session co-chaired by rolf Aschenbrenner of Fraunhofer IZM and ricky Lee of the hong Kong University of Science and Technology and this year’s CPMT President on the booming market in Power Electronics; and the 2012 inEMI north America roadmaps session. A student reception hosted by Eric Perfecto of IBm provided conference insights for future professionals.

over the next three days, 348 technical papers were featured in 36 oral and five interactive poster sessions, including a student poster session. The best attended sessions of the conference were those on 3D/TSV; over 63 papers/posters covered new developments, trends, and applications for 3D integration, TSV fabrication, modeling and materials. Wednesday’s ECTC luncheon keynote speaker Gregg Bartlett of GLoBALFoundrIES brought the foundry perspective on the challenges faced in continuing to scale digital technologies while meeting future silicon nodes memory bandwidth

and power demands. The evening’s ECTC Plenary session, chaired by Christopher Bower of Semprius, covered the expanding markets and emerging technologies of photonics, and the Thursday night CPMT seminar chaired by Kishio yokouchi of Fujitsu Interconnect Technologies and Venky Sundaram of Georgia Tech addressed advances in coreless package substrate and material technologies.

The ECTC is the flagship conference of the IEEE - CPMT Society, which sponsors the Thursday

luncheon and awards ceremony. The IEEE CPMT award was given to mauro J. Walker of motorola (retired) for his extensive contribution and leadership in packaging.

All conference photos are posted on Flickr.

Abstracts are now solicited for next year's conference which will be held May 28-31, 2013, at the new Cosmopolitan hotel in Las Vegas, nevada, USA.

www.ectc.net

The 2012 Electronics Components and Technology Conference (ECTC), held in San diego and chaired by david mcCann of GLoBALFoundrIES, had the second highest attendance in its history with over 1,200 attendees from 25 countries. In addition, 83 exhibitors showed their latest technologies.

Student interactive posters were well attended. (Courtesy of ECTC)

Women in engineering table at the CPMT luncheon. (Courtesy of ECTC)

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29

E V E n T r E V I E W

Packaging solutions for new technologies

The presentations will shed light on recent application specific packaging technologies, processing and manufacturing related

technologies which can be leveraged as key enablers for cost efficient electronic devices and systems.

The Advanced Packaging conference is divided into four sessions: Technologies, materials, Processes and Packages. on Tuesday, 9 october, Markus Brunnbauer, Wafer Level Packaging Manager at Intel Mobile Communication, will give the starting signal with his keynote. he will talk about “The Evolution of Packaging in Future Systems” -comparing the current trends in packaging and checking their matching against the upcoming challenges caused by the emerging systems.

Subsequently Thorsten Matthias will speak about “Room Temperature Debonding – An Enabling Technology for TSV and 3D Integration”. The Business development manager of the EV Group introduces “LowTemp ZoneBond” as a revolutionary breakthrough in thin wafer processing. It enables room temperature debonding, which is independent from the properties of the temporary adhesive. As it is independent of the material, a standardization of the debonding process and debonding equipment is enabled.

Johann Liu, Professor and head of SMIT Center from the Chalmers University of Technology Goteborg, will give his lecture on “Chemically Vapor Deposited Carbon NanoTubes for 3D Stacking Integration”. The most common method to fill TSVs is electroplating copper, whose reliability is however a serious concern. Therefore the need to find alternative materials for TSV filling is strong. Carbon nanotubes (CnTs) are supposed to be a promising material for building future interconnects due to their many attractive properties. CnTs are mechanically flexible and resilient and have very low thermal expansion.

The technology sessions will be concluded by Juergen Wolf from All Silicon Integration Dresden at Fraunhofer IZM. he focuses on “3D Integration – Approach to Multifunctional Systems in

Packaging”. heterogeneous system integration is one of the most significant strategic key topics for future system integration and requires cost efficient and reliable packaging solutions. Besides the progress in silicon technology following “Moore s law” there is an increasing demand for highly miniaturized complex system architectures which results in advanced System in Package (SiP) solutions. Currently different approaches are in the development, which result in complex 3D architectures. The main aim is to provide cost efficient packaging solutions, which meet application specific requirements with short time to market. Juergen Wolf will highlight some major aspects and current status of 3D integration approaches and will present some potential solutions for different market segments.

For more details on the Materials, Processes and Packages Sessions please visit www.semiconeuropa.org. register until 30 September and profit from the early bird price.

The Advanced Packaging Conference at SEMICon Europa is the perfect platform for managers, engineers and technicians from the whole spectrum of the semiconductor industry. The conference will review the Technologies, Materials, Processes and Equipment that are being developed in Europe and elsewhere to spearhead the take up of these advanced packaging needs. SEMICon Europa 2012 will take place in Dresden / Germany from 9–11 october.

www.semiconeuropa.org

Advanced Packaging is one major topic at SEMICon Europa 2012. year by year, the Advanced Packaging conference will give the opportunity to learn more about most important microelectronics applications developments which enable novel, advanced packaging solutions to be the key drivers in system integration of electronic devices.

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Beginning in 1998 with Yole développement, we have grown to become a group of companies providing market research, technology analysis, strategy consulting, media in addition to fi nance services. With a solid focus on emerging applications using silicon and/or micro manufacturing, yole Développement group has expanded to include more than 50 associates worldwide covering MEMS, MedTech, Advanced Packaging, Compound Semiconductors, Power Electronics, LED, and Photovoltaics. The group supports companies, investors and r&D organizations worldwide to help them understand markets and follow technology trends to develop their business.

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