Outline Design of Frequency Divider - cycho
2
D. Lim ISSCC 2007 / SESSION 30 / BUILDING BLOCKS FOR HIGH-SPEED TRANSCEIVERS / 30.3 Outline Motivation Design of a mm-Wave Static CML Frequency Divider in 65nm SOI CMOS Implementation & Measurement Extraction of Circuit Parameter Variability Conclusion Design of Frequency Divider Design concerns: fF 20 GHz 30 2 1 2 , , , , W R L Diff tot P tot P L tot P Diff m SO C C C C C C R C g f L A. Bandwidth: C. Inductive peaking: pH 330 1 . 3 , 2 tot P L C R L B. Voltage swing: 230 V 1 P - P R C R SW P P L Motivation Reduced VCO tuning range Signal power loss through interconnect Reduced operation range of frequency divider Process variation of the frequency divider must be carefully considered in an early design stage. CMOS Sub Divider PFD Charge Pump LPF f REF Frequency Divider (/2) VCO Layout and Die Photo GND GND GND GND RF OUT CLK CLKB VDD VDD Stab inductor Divider Core OP load resistor Area-minimized layout for reduced parasitic Divider Schematic VBIAS CLK CLKB Q1 Q2 Q3 Q4 R5 R6 R1 VDD R2 R3 R4 Q5 Q6 Q9 Q10 Q7 Q8 Q11 Q12 Q13 OUTPUT (90GHz) C1 C2 CC CB L C Bias-tee Master Latch Slave Latch L1 L2 L3 L4 Inductive peaking Selected Technology Cross-section of a 65nm SOI CMOS: f T 330GHz SUBSTRATE CA POLY Si SiO 2 BOX 8t M10 M9 M6 M5 M4 M1 4X 2X 1X Cu BEOL FEOL 2t 1t M7 M8 8X 4t See Digest page 542 30.3 Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS 1 Massachusetts Institute of Technology, Cambridge, MA, 2 IBM, Hopewell Junction, NY A static CML divide-by-2 frequency divider is integrated in 65nm SOI CMOS. The maximum operating frequency is 90GHz while dissipat- ing 52.4mW. The self-oscillation frequency is 92GHz with 0.57pJ switching energy. Measurement of self-oscillation frequency at multiple bias conditions enables estimation of the variation in threshold voltage, capacitance, and resistance. Daihyun Lim 1 , Jonghae Kim 2 , Jean-Olivier Plouchart 2 , Choongyeun Cho 2 , Daeik Kim 2 , Robert Trzcinski 2 , Duane Boning 1 446 • 2007 IEEE International Solid-State Circuits Conference 1-4244-0852-0/07/$25.00 ©2007 IEEE.
Transcript of Outline Design of Frequency Divider - cycho
D. Lim
ISSCC 2007 / SESSION 30 / BUILDING BLOCKS FOR HIGH-SPEED TRANSCEIVERS / 30.3
Outline
MotivationDesign of a mm-Wave Static CML Frequency Divider in 65nm SOI CMOSImplementation & MeasurementExtraction of Circuit Parameter VariabilityConclusion
Design of Frequency DividerDesign concerns:
fF20
GHz302
12
,
,,
,
WRLDifftotP
totPLtotP
DiffmSO
CCCCCCRC
gf
L
A. Bandwidth:
C. Inductive peaking:pH330
1.3,
2totPLCRL
B. Voltage swing:
230V1 P-P
RCRSW PPL
Motivation
Reduced VCO tuning rangeSignal power loss through interconnectReduced operation range of frequency dividerProcess variation of the frequency divider must becarefully considered in an early design stage.
CMOS SubDivider
CMOS SubDivider
PFDPFDChargePump
ChargePumpLPFLPF
fREF
FrequencyDivider (/2)FrequencyDivider (/2)
VCO
Layout and Die Photo
GN
DG
ND
GN
DG
ND
RF
OU
T
CLK
CLK
BVD
D
VDD
Stab
indu
ctor
Div
ider
Cor
e
OP loadresistor
Area-minimized layout for reduced parasitic
Divider Schematic
VBIAS
CLKCLKB
Q1 Q2 Q3 Q4
R5 R6
R1
VDD
R2 R3 R4
Q5 Q6
Q9 Q10
Q7 Q8
Q11 Q12
Q13
OUTPUT
(90GHz) C1
C2
CCCB L
C
Bias-tee
Master Latch Slave Latch
L1 L2 L3 L4Inductivepeaking
Selected Technology
Cross-section of a 65nm SOI CMOS: fT 330GHz
SUBSTRATECA
POLYSiSiO2 BOX
8tM10
M9
M6M5M4
M1
4X
2X
1X
CuBEOL
FEOL
2t
1t
M7M8
8X
4t
See Digest page 542
30.3 Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS
1Massachusetts Institute of Technology, Cambridge, MA, 2IBM, Hopewell Junction, NY
A static CML divide-by-2 frequency divider is integrated in 65nm SOI CMOS. The maximum operating frequency is 90GHz while dissipat-ing 52.4mW. The self-oscillation frequency is 92GHz with 0.57pJ switching energy. Measurement of self-oscillation frequency at multiplebias conditions enables estimation of the variation in threshold voltage, capacitance, and resistance.
Daihyun Lim1, Jonghae Kim2, Jean-Olivier Plouchart2, Choongyeun Cho2, Daeik Kim2, Robert Trzcinski2, Duane Boning1
446 • 2007 IEEE International Solid-State Circuits Conference 1-4244-0852-0/07/$25.00 ©2007 IEEE.
Self-Oscillation of Frequency Divider
Self-oscillation of Frequency Divider
90O shift
1 2 3 4
RL -1/gmLCP
gm*VIN+_
VIN
+
_VOUT
mL
mD
P
pppp
mmmmSO
gg
CR
CCCCgggg
L
1
44321
4321
D QB
Ck
Back-Propagation-of-Variation
l
l
TH
SO
SO
SO
l
l
TH
l
l
TH
BCBCBC
BCBCBC
BCBCBC
SO
SO
SO
DDBIAS
DDBIAS
DDBIAS
llTHSO
CRV
fff
S
CRV
SCRV
fff
VVfVVfVVf
CRVf
3
2
11
333
222
111
3
2
1
3
2
1
),(),(),(
Frequency deviation as a linear combination of parameter deviation
Sensitivity is a function of bias conditions.
Sensitivity is calculated from circuit simulation with nominal parameters.
Pseudo-Inversion of sensitivity matrix
Input Sensitivity Curves
70 75 80 85 90 95 100-40
-30
-20
-10
0
10
Frequency (GHz)
Min
imum
Inpu
t Pow
er (d
Bm
)
1.6V 1.0V1.8V 1.5V2.0V 1.5V2.2V 1.5V
VDD VBIAS
Correlation Between Circuit Parameters
-0.10
0.1
-1000
100-10
-5
0
5
10
RL ( )
C p(fF)
( R L, C)=
-85%
VTH(V)
( RL, VTH)= 23%
( C, VTH)= -26%
3 =21%3 =20%
3=2
2%
Inductive Peaking and Layout Alternatives
0 20 40 6024
26
28
30
32
34
36
38
Die Number
Sel
f-O
scill
atio
n Fr
eque
ncy
(GH
z) Divider 1 Parasitic-awareDivider 2 Area-optimizedDivider 3 (Ind. Peaking)
Summary & Conclusion
A 90GHz 2:1 static CML frequency divider is implemented in 65nm SOI CMOS.The divider operates up to 100.2GHz for a 4.87dBm differential input with 52.4mW.Process variation is highly systematic across a wafer with more than 90% cross correlation between wafers.The variation of circuit parameters and their correlation are estimated using the sensitivity analysis.
Systematic Wafer-to-Wafer Variation
0 20 40 6028
30
32
34
36
38
40
42
Die Number (sorted)
Sel
f-O
scill
atio
n Fr
eque
ncy
(GH
z)
Cross Corr. > 95%
© IEEE / ISSCC 2007 VISUALS SUPPLEMENT • 447
30
