Optimizing Time to Bug - Amazon S3...Keynote © Mentor Graphics Corporation 5 HF, SemIsrael Expo,...

Keynote

© Mentor Graphics Corporation

HF, SemIsrael Expo, Dec 20191

Harry FosterChief Scientist Verification

2020 Vice Chair Design Automation Conference

November 2019

Optimizing Time to BugDon’t Panic!!!


INDUSTRY PULSE

Keynote




Worldwide IC Market Growth

-9%

19%

35%

-33%

2%

16%

28%

8% 9%4%

-6%-10%

33%

1%

-4%

5%7%

-2%

3%

25%

14%

-15%

6%9% 11%

15%

-40%

-30%

-20%

-10%

0%

10%

20%

30%

40%

50%

98 99 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19F 20F 21F 22F 23F

IC M

ark

et

Ch

an

ge

Year

Source: IC Insight, Mid-Year Update to McClean Report 2019 (July), A Complete Analysis and Forecast of the Integrated Circuit Industry

HF, SEMIsrael, November, 20193


Keynote




Largest IC Product CategoriesExpected decline in the DRAM an NAND flash memory markets


$99.4

$53.8

$59.4

$27.3 $23.6

$62.0

$52.5

$40.6

$25.4$22.2

$-

$20.0

$40.0

$60.0

$80.0

$100.0

DRAM PC/Server MPUs NAND Flash Special Purpose Logic Cellular MPUs

IC R

evenue (

$M

)

2018

2019F

Source: IC Insight, Mid-Year Update to McClean Report 2019 (July), A Complete Analysis and Forecast of the Integrated Circuit Industry


IC Market by System Type ($)

55.6%51.3%

45.0%36.7% 36.6% 34.6%

18.5%22.0%

29.3%37.2% 36.4%

35.7%

13.0% 12.9% 12.2% 12.5% 11.0%11.2%

4.7% 6.3% 6.5% 7.1% 8.0% 9.8%

8.2% 7.5% 7.0% 6.5% 8.0% 8.7%

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

1998 2003 2008 2013 2018 2023F

Perc

ent

Share Computer

Communications

Consumer

Auto

Other


Source: IC Insight, June Update to The McClain Report 2019

Keynote






What’s really driving complexity?


Keynote




Disruptive Trends in the Global DatasphereLooking Back 30 Years


Computing

Performance

Networking

VAX 11/780

MicroVAX II


Disruptive Trends in the Global DatasphereReshaping everything!


Computing

Performance

Networking

Communication

Power

Security

Safety

Machine Learning1 ZB = 1 Billion Gigabytes

Keynote




Disruptive Trends Require Change


c1920

c1940

1876

c1900c1850

c1150

c1950

c1960

1972 c1990

c1980c2000

2007

?

“Change is inevitable. Growth is optional.” John C. Maxwell

“I'm in favor of progress; it's change I don't like.” Mark Twain

“The world as we have created it is a process of our thinking. It cannot be changed without changing our thinking.”

Albert Einstein


HOW ARE WE DOING?

Keynote




How are we doing?Number of Required Spins Before Production

0%

10%

20%

30%

40%

50%

1 (FIRST SILICONSUCCESS)

2 3 4 5 6 7 SPINS or MORE

Desi

gn P

roje

cts

Number of Required ASIC Spins Before Production

2012

2014

2016

2018


Source: Wilson Research Group and Mentor, A Siemens Business, 2018 Functional Verification Study


How we doing?Non-trivial Bug Escapes into Production

0%

5%

10%

15%

20%

25%

30%

35%

0 1 2 3 4 5 6 or More

Desi

gn P

roje

cts

Non-trivial FPGA Bug Escapes into Production

2016

2018



84% of FPGA design projects have non-trivial bugs escape into production

Keynote




2018 FPGA Verification Technique Adoption and Bug Escapes

61%

57%

46%

30%

77%

65%

59%

37%

0% 10% 20% 30% 40% 50% 60% 70% 80%

Code Coverage

Functional Coverage

Assertions

Constrained-Random

Percentage Adoption

Bug Escapes

No Bug Escapes




Cost of fixing bugs increases over time!Need to optimize the time for finding and fixing the next bug!


Requirements Design & Development Unit Testing System Testing Release Production

Cost

of

Repair

Source: Semiconductor Engineering, When Bugs Escape, July 26th

Keynote



Restricted © 2019 Mentor Graphics Corporation

The conversations you don’t want to have…

17

You’re two months into system qual testing There’s an intermittent data corruption

It didn’t occur until high-temp stress It’s hard to reproduce, and sims don’t catch it

“Why didn’t you catch this?”

“We need a review, now”

“Book travel, get to the lab”

“This is costing us $x per day!”

“Will this be metal only?”

“Let’s find all the issues”

“Tiger team! Call the experts!”

Firmware isolates the issue to your block

“We’re missing the market window”

“The project will be canceled!?”



OPTIMIZING TIME TO BUG

Keynote



Restricted © 2019 Mentor Graphics Corporation

ASIC: Where Verification Engineers Spend Their Time


13%

19%

21%

44%

3%Test Planning

Testbench Development

Creating Test and Running Simulation

Debug

Other



The BUZZ … Regression Efficiency


One Idea

�� = �(�

��)

Conclusion:

Make your simulator faster

Further Developed Idea

�� = �(

� ∗ ��)

Remove Redundancies

Make each cycle do more work

Make your simulator faster

20

Automate to spend more time

bug hunting

Use goals for more effective

bug hunting

Keynote




Declarative Specifications Open New Possibilities

Most SoC tests are directed – limits automation and analysis

A declarative description enables automation and analysis

Declarative tests let thetool do the work



Formal Counter Examples Put You Right In the Pitch!


Formal

0 1 2 3 4 5

req

ack

Example intended behavior

Keynote




ASIC: Formal Technology Adoption

0%

5%

10%

15%

20%

25%

30%

35%

40%

Formal property checking Automatic formal verification

Desi

gn P

roje

cts

ASIC: Adoption of Static Techniques

2012

2018




FPGA: Formal Technology Adoption

0%

5%

10%

15%

20%

25%

Formal property checking Automatic formal verification

Desi

gn P

roje

cts

FPGA: Adoption of Static Techniques

2012

2014

2016

2018



Keynote




Summary

Major changes are underway in both the Systems & IC worlds

Data has become the worlds most valuable resource— Changing the way we think about computing, networking, and communication

Computer architectures are no longer driven by performance alone— Performance per watt is a key driver in the IoT eco system

Low-power, security, safety, and AMS are common requirements— From the enterprise to the edge sensor device

The next big wave in verification solutions has emerged

to address…— Growing verification complexity

— Growing design requirements

— Growing Analog/Mixed-Signal requirements

— Scaling verification for embedded systems

— System-level verification metrics

— Unifying verification process across multiple engineers


© Mentor Graphics Corporationwww.mentor.com

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