Opti FIR Report

7/30/2019 Opti FIR Report

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SUBMITTED BY:


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To Whom It May Concern

This is to certify thatNameshavesuccessfully completed their project on:

VHDL code for VMC in VHDL

With all its functionalities during the winter training coursefromSemiconductor Technologies, Vedant theirworkwas authenticand conduct was diligent & sincere. The

project satisfies the norms of the company and was

developed under the guidance ofMs. Anupam Maurya &Mr. Amit Chandra.

Certificate is awaited

CERTIFIED BY:

Ms. Anupam Maurya Mr.Sachin Kr. Kanodia

2

Semiconductor TechnologiesVEDANT

VLSI DESIGN EDUCATION AND TRAINING LUCKNOW CENTRE


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(Project Guide) (Head)

ACKNOWLEDGEMENT

No academic endeavor can be single handedlyaccomplished. This work is no exception.

At the outset, we would like to record our gratitude to

Mr. Sachin Kr.Kanodia for initiating us into this training.

We sincerely acknowledge our thanks to our project

guide Ms. Anupam Maurya & Mr. Amit Chandra for their

valuable suggestions and time to time consultation.

Last, but not the least, we would like to thank all the

staff of VLSI Design Department, Semiconductor Laboratory

(SCL), Vedant, Lucknow especially Ms. Charu Agarwal for

their kind cooperation and assistance during our training

period.

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PREFACE

The evolution of Very large scale integration (VLSI) technology has

developed to the point where millions of transistors can be integrated

on a single die or chip where integrated circuits once filled the role

of subsystem component partitioned at analog-digital boundaries.

They now integrate complete systems on a chip by combining both

analog-digital functions. Complementary metal oxide semiconductors

technology has been the mainstay in mixed signal implementations

because it provides density and power savings on the digital side,

and a good mix of components for analog design.

Due in part to the regularity and granularity of digital circuit computer

aided design (CAD) methodologies have been very successful in

automating the design of digital systems given a behavioral

description of the function desired. Such is not the case for analogcircuit design. Analog design still requires a hands on design

approach in general. Moreover many of the design techniques used

for discrete circuits are not applicable to the design of analog /mixed

signal VLSI circuits. It is necessary to examine closely the design

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process of analog circuit and to identify those principles that will

increase design productivity and the designers chances for success.

CONTENT Page no.

SEMICONDUCTOR TECHNOLOGIES 06

VEDANT 08

INTRODUCTION TO VLSI 09

INTRODUCTION TO VHDL 12

IEEE LIBRARIES 13 INTRODUCTION TO FIR 14

VHDL CODE 15

SYNTHESIS REPORT 24

BIBLIOGRAPHY 71

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SEMICONDUCTOR TECHNOLOGIES-

VEDANTAN ISO 9001:2000 CERTIFIED INSTITUTION

Semiconductor Technologies has always been in sync withthe future. It has understood and appreciated the needs ofIndia, its people and its ever-growing industry. Over the lastsix 20 years tell the saga of VEDANT contribution in leadingthe national effort in the vital areas of microelectronics.

M/s Semiconductor Technologies-VEDANT is Indiaspremier VLSI Design & Embedded System Designorganization since 2002. While VEDANTis Indias pioneer inthe field of VLSI Design & Embedded System Design andTesting. VEDANT is providing Education & Training on VLSIDesign & Embedded System Design through state-of-the-art lab facilities, equipped with the Industry Standard tools.

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VLSI Design / Embedded Systems Design Engineer designsuch Silicon chipsmaking a career in VLSI Design / ESD ishighly respected & rewarding one. Furthermore we wouldlike to bring in your notice that VEDANT is a member ofIndian Semiconductor Association as well. Semiconductor

Technologies-VEDANT (Now an ISO 9001: 2000 CertifiedInstitution) is center for the training crafted in VLSI/ESDeducation module followed with VLSI Design software alongwith the FPGA programming & 8051 Microcontroller kit.

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VEDANT

VEDANT (VLSI design and training) is one of the prestigious

projects of SCL, a pioneer with vertically integrated facility in

the country.

SCL VEDANT program covers the complete spectrum of VLSI

design inclusive of front end, back end and provides of

exposure to the IC fabrication process. Industry standard CAD

tools are used for the purpose of training backed up by project

work under the guidance of experts.

VEDANT (LUCKNOW CENTER) is the institute, whichprovides training in VLSI design to students. The working

environment is concentrated on front-end design process. It runs

two programs PG diploma in VLSI designing of four months

and certificate course of two months. It also provides Summer &

Winter Training in VLSI Design orEmbedded System.

It has an advanced lab which is equipped with latest industry

standard Electronic Design Automation (EDA) and FPGA tools

and 8051 Development Kits inclusive of

Model Sim 6.0a

Xilinx tools8


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FPGA Kit

8051 Development Kit

Keil Software

Flash Magic (Rom burning)

INTRODUCTION TO VLSI

For any given design, if the architecture of the fixed LSIand VLSI blocks suit the application then the design time isconsiderably shortened. When a one-chip microprocessor isnot quite suitable, micro programmable architectures canoften provide sufficient customization.

Micro programmable architectures, such as bit-slice,allow a closer control over the architecture but not totalcontrol. The basic building blocks are still designed by thechip manufacturer for generic applications. Bit-slicearchitectures include interruptible sequencers and 32-bit

ALUs.The customization of the bit-slice modules to an

application is done through customer-designed module

interconnection, the implemented commands and theirsequences. The commands or instruction set is called themicro-program for the design.ASIC (VLSI, VHLSI)

The 1980s saw the acceptance of ASICs ( ApplicationSpecific Integrated Circuits), VLSI devices large enough toallow designers to implement architectures that were suitedto solving the design problem rather than forcing onearchitecture to solve everything. It was the natural extension

to the bit-slice architectures, where some control ofarchitecture was possible through microprogramming butwhere the basic building blocks were fixed designs.

Not far behind the ASIC and ASIC developments,multimedia and design integration saw a need to incorporateanalog functions into digital systems. For years the trend hadbeen away from analog design as a chosen career and now

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there was a shortage of design engineers. First camemassive re-training of internal staff as companies struggledto cope. Then came the creation of ElectricallyProgrammable Analog Circuit (EPAC) and related devices.

Application- specific solutions also includes the

standard product mix where the market for a device is solarge that product are developed specific to a massapplication. PCI controllers is an example where oneinterface controller is targeted to handle the interface formany devices and device types, the control problem tailoredto the device via programming.

The application-specific customization of the designsolution allows the designer to have the creative power of agate-level breadboard design while keeping the productionadvantages of VLSI.

Over the years, there has been an evolution of theuniversal building blocks used by logic circuit designers. Inthe mid-1960s, there were SSI gates; NAND, NOR, EXOR,and NOT or INVERT. In the early 1970s, MSI blocks,registers, decoders, multiplexers, and other blocks madetheir appearances. In the late 1970s, ALUs (arithmetic logicunits) with on-board scratchpad registers, interrupt

controllers, micro program sequencers, ROMs/PROMs, andother LSI devices up to and including a complete one-chipmicroprocessor (control, ALU and registers) became readilyavailable. (And from this the PC was born.)

SSI (small scale integration) is defined here to includechips containing approximately 2-10 gates. MSI (mediumscale integration) is used for chips containing 20-100 gates.LSI (large scale integration) ships contain 200-1000 gates,

with the upper limit continually extending as VLSI (very largescale integration) became a reality. In the mid-1980s, ASIC(application-specific integrated circuits) ranged from 1000gates to 20,000 gates (bipolar technology) or 200,000(CMOS technology).

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INTRODUCTION TO VHDL

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Excel VHDL is a user friendly windows based packagewhich encapsulates the powerful Simily VHDL engine.

A typical VHDL source file contains zero or more designunits. Examples of design units are entity, architecture,package, etc. When a VHDL source file is compiled, theresults of successful compilation are stored in a library .So,in effect; the design units contained within the VHDL sourcefile are placed in a library.

A design unit that has been compiled into one librarycan reference other designs units in any other library throughthe use of clauses and library statements.

In VHDL, the current working library is always calledwork. When using a VHDL compiler or simulator, there isalways a concept of a current working library. If no particularlibrary is specified as a current working library, the currentworking library is assumed to be work. You can associatethe work library with any other library.

There are two kinds of design units: Primary andSecondary design units. The design units of type entity,package and configuration are primary design units. Designunits or type architecture and package body are secondarydesign units. Secondary design units are always associatedwith a primary design unit. Secondary units typically containthe implementation of their primary units.

SIMPLE RULES TO REMEMBER

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All primary units in a given library must have unique names. Note:VHDL language actually allows the entity to have the same name, asone of its configurations but VHDL Similar requires that all primaryunits have unique names in a given library. All secondary units for agiven primary unit must also be named uniquely. A primary designand its associated design unit must both reside in the same library.

IEEE LIBRARIES

There is a VHDL standard library with a special name std. Thislibrary and its contents (the packages standard and textio) are built

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into the tools and cant be controlled. This also means that you canthave user defined library called std.

The other IEEE libraries are stored I lib folder of the installationdirectory. The source code is present in IEEE folder and the compiledcode is present in the IEEE.SYM folder. You may view the source

code folder to see the definitions for use in your code.

Introduction to Optimized FIR

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VHDL Generation of Optimized FIR Filters:- This workproposes an VHDL generation software for optimized FIR filters.In this paper a near optimum algorithm for constant coefficient FIRfilters was used. This algorithm uses general coefficientrepresentation for the optimal sharing of partial products in

Multiple Constants Multiplications (MCM). The developed toolwas compared to Matlab FDA toolbox. Synthesis results show thatour tool is able to produce significantly better hardware than FDAtoolbox, doubling the speed and reducing the silicon area by 75%.The software produces a generic VHDL output, synthesizable toASIC or FPGA.

FIR FILTER DESIGN:- In digital circuits, a FIR (Finite ImpulseResponse) filter can be viewed as a functional block, as shown inFigure 1-

Figure 1: Transposed form of a 4 taps FIR filter implementation.TheMCM block is shown inside the striped line rectangle.whereNis the number of coefficients (or taps) of the filter,Xis theinput signal, Ythe output signal, Y[n] the current output sample

andHrepresents the filter coefficients.

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CODE for Optimized FIR Filter

------------------------TOP MODULE OF OPTIMIZED FILTER---------------------

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library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_SIGNED.ALL;

entity TOP_MODULE isPort ( RST,CLK : in STD_LOGIC;

X : in STD_LOGIC_VECTOR (15 downto 0);yout : out STD_LOGIC_VECTOR (31 downto 0);

cout : out STD_LOGIC);

end TOP_MODULE;

architecture Behavioral of TOP_MODULE is

COMPONENT sixteenbit_fa1 isPort ( a : in STD_LOGIC_VECTOR (31 downto 0);

b : in STD_LOGIC_VECTOR (31 downto 0);yout : out STD_LOGIC_VECTOR (31 downto 0);cout : out STD_LOGIC);

end COMPONENT;

COMPONENT mult16 isPort ( a : in std_logic_vector(15 downto 0);

b : in std_logic_vector(15 downto 0);prod : out std_logic_vector(31 downto 0));

end COMPONENT;component dealy isPort ( rst,clk : in STD_LOGIC;

din: in STD_LOGIC_VECTOR (31 downto 0);yout : out STD_LOGIC_VECTOR (31 downto 0));

end component;

type coefficients is array (15 downto 0)of std_logic_vector(15 downto 0);

constant k:coefficients:=("0000000000000010","0000000000000001","0000000000000011",

"0000000000000100","0000000000000101","0000000000000110",

"0000000000000111","0000000000001000","0000000000001001",

"0000000000001010","0000000000001011","0000000000001100",

"0000000000001101","0000000000001110","0000000000001111",

"0000000000010000");

type mcmblock is array (15 downto 0)of std_logic_vector(31 downto 0);signal mcm:mcmblock;

type addition is array (16 downto 0)of std_logic_vector(31 downto 0);signal add:addition;

type addition1 is array (15 downto 0)of std_logic_vector(31 downto 0);signal add1:addition1;

SIGNAL C : std_logic_vector(15 downto 0);

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BEGIN

m1:for i in 0 to 15 generatea1: mult16 PORT MAP(x,k(i),mcm(i));end generate m1;

--add1(0)'0');

m111:for i in 0 to 15 generate

B0: sixteenbit_fa1 PORT MAP (MCM(i),add1(i),ADD(i+1),C(i));c0:dealy port map (rst,clk,add(i+1),add1(i));

end generate m111;

yout


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entity sixteenbit_fa1 isPort ( a : in STD_LOGIC_VECTOR (31 downto 0);------15 TO 0

b : in STD_LOGIC_VECTOR (31 downto 0);--15 TO 0yout : out STD_LOGIC_VECTOR (31 downto 0);--15 TO 0cout : out STD_LOGIC);

end sixteenbit_fa1;

architecture Behavioral of sixteenbit_fa1 is

signal s: std_logic_vector(31 downto 0);--15 TO 0signal carry1: std_logic_vector(32 downto 0);--16 TO 0

COMPONENT FAPORT(a : IN std_logic;

b : IN std_logic;cin : IN std_logic;sum : OUT std_logic;cout : OUT std_logic);

END COMPONENT;

begin

carry1(0)


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end Behavioral;

---------VHDL code for array multiplier

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mult16 isPort ( a : in std_logic_vector(15 downto 0);---7 T0 0

b : in std_logic_vector(15 downto 0);---7 T0 0prod : out std_logic_vector(31 downto 0));-----15 T0 0

end mult16;

architecture Behavioral of mult16 is

constant n:integer :=16;---8

subtype plary is std_logic_vector(n-1 downto 0);type pary is array(0 to n) of plary;signal pp,pc,ps:pary;

begin

pgen:for j in 0 to n-1 generatepgen1:for k in 0 to n-1 generatepp(j)(k)


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addlast:for k in 1 to n-1 generate

ps(n)(k)


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SIGNAL ADD12,ADD13 : std_logic_vector(0 to (31));SIGNAL ADD14,ADD15 : std_logic_vector(0 to (31));

begin

MCM_BLOCK: MCM_BLOCK_LOOP GENERIC MAP (M)PORT MAP (X,mcm0,mcm1,mcm2,mcm3,mcm4,mcm5,mcm6,mcm7,

mcm8,mcm9,mcm10,mcm11,mcm12,mcm13,mcm14,mcm15);

PROCESS(CLK,RST)

BEGIN

IF RST='1' THEN

YOUT'0');

ELSIF CLK'EVENT AND CLK='1' THEN

ADD0


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mcm8,mcm9 : out std_logic_vector(0 to (31));mcm10,mcm11 : out std_logic_vector(0 to (31));mcm12,mcm13 : out std_logic_vector(0 to (31));mcm14,mcm15 : out std_logic_vector(0 to (31)));

end mcm_block_loop;

architecture Behavioral of mcm_block_loop is

------------------------------coefficient declaration-------------------------------

constant k0 : std_logic_vector(0 to(m)):="0000000000000010";constant k1 : std_logic_vector(0 to(m)):="0000000000000001";constant k2 : std_logic_vector(0 to(m)):="0000000000000011";constant k3 : std_logic_vector(0 to(m)):="0000000000000100";constant k4 : std_logic_vector(0 to(m)):="0000000000000101";constant k5 : std_logic_vector(0 to(m)):="0000000000000110";constant k6 : std_logic_vector(0 to(m)):="0000000000000111";constant k7 : std_logic_vector(0 to(m)):="0000000000001000";constant k8 : std_logic_vector(0 to(m)):="0000000000001001";constant k9 : std_logic_vector(0 to(m)):="0000000000001010";constant k10: std_logic_vector(0 to(m)):="0000000000001011";constant k11: std_logic_vector(0 to(m)):="0000000000001100";

constant k12: std_logic_vector(0 to(m)):="0000000000001101";constant k13: std_logic_vector(0 to(m)):="0000000000001110";constant k14: std_logic_vector(0 to(m)):="0000000000001111";constant k15: std_logic_vector(0 to(m)):="0000000000010000";

begin

-----------------------------------------------mcm_block_description---------------------

mcm0


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SYNTHESIS REPORT OF OptimizedFIR

Release 8.2i - xst I.31

Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.

--> Parameter TMPDIR set to ./xst/projnav.tmp

CPU : 0.00 / 0.88 s | Elapsed : 0.00 / 1.00 s

--> Parameter xsthdpdir set to ./xst

CPU : 0.00 / 0.88 s | Elapsed : 0.00 / 1.00 s

--> Reading design: TOP_MODULE.prj

TABLE OF CONTENTS

1) Synthesis Options Summary

2) HDL Compilation

3) Design Hierarchy Analysis

4) HDL Analysis

5) HDL Synthesis

5.1) HDL Synthesis Report

6) Advanced HDL Synthesis

6.1) Advanced HDL Synthesis Report

7) Low Level Synthesis

8) Partition Report

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9) Final Report

9.1) Device utilization summary

9.2) TIMING REPORT

======================================================

===================

* Synthesis Options Summary *

======================================================

===================

---- Source Parameters

Input File Name : "TOP_MODULE.prj"

Input Format : mixed

Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "TOP_MODULE"

Output Format : NGC

Target Device : xc3s50-5-pq208

---- Source Options

Top Module Name : TOP_MODULE

Automatic FSM Extraction : YES

FSM Encoding Algorithm : AutoFSM Style : lut

RAM Extraction : Yes

RAM Style : Auto

ROM Extraction : Yes

Mux Style : Auto

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Decoder Extraction : YES

Priority Encoder Extraction : YES

Shift Register Extraction : YES

Logical Shifter Extraction : YES

XOR Collapsing : YESROM Style : Auto

Mux Extraction : YES

Resource Sharing : YES

Multiplier Style : auto

Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES

Global Maximum Fanout : 500

Add Generic Clock Buffer(BUFG) : 8

Register Duplication : YES

Slice Packing : YES

Pack IO Registers into IOBs : auto

Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed

Optimization Effort : 1

Keep Hierarchy : NORTL Output : Yes

Global Optimization : AllClockNets

Write Timing Constraints : NO

Hierarchy Separator : /

Bus Delimiter :

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Case Specifier : maintain

Slice Utilization Ratio : 100

Slice Utilization Ratio Delta : 5

---- Other Optionslso : TOP_MODULE.lso

Read Cores : YES

cross_clock_analysis : NO

verilog2001 : YES

safe_implementation : No

Optimize Instantiated Primitives : NO

use_clock_enable : Yes

use_sync_set : Yes

use_sync_reset : Yes

======================================================

===================

======================================================

===================

* HDL Compilation *

======================================================

===================Compiling vhdl file "D:/anupam MAURYA/anu maurya/fir_filter/opti.vhd"

in Library work.

Architecture behavioral of Entity top_module is up to date.

Architecture behavioral of Entity dealy is up to date.

Architecture behavioral of Entity sixteenbit_fa1 is up to date.

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Architecture behavioral of Entity fa is up to date.

Architecture behavioral of Entity mult16 is up to date.

======================================================

===================* Design Hierarchy Analysis *

======================================================

===================

Analyzing hierarchy for entity in library

(architecture ).

Analyzing hierarchy for entity in library (architecture

).


(architecture ).


).


).

Building hierarchy successfully finished.

======================================================

===================

* HDL Analysis *

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======================================================

===================

Analyzing Entity in library (Architecture

).

Entity analyzed. Unit generated.

Analyzing Entity in library (Architecture ).


Analyzing Entity in library (Architecture

).






======================================================

===================

* HDL Synthesis *

=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit .

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Related source file is "D:/anupam MAURYA/anu

maurya/fir_filter/opti.vhd".

WARNING:Xst:646 - Signal is assigned but never used.

WARNING:Xst:1780 - Signal is never used or assigned.

WARNING:Xst:1780 - Signal is never used or assigned.Summary:

inferred 224 Xor(s).

Unit synthesized.

Synthesizing Unit .



Found 32-bit register for signal .

Summary:

inferred 32 D-type flip-flop(s).

Unit synthesized.

Synthesizing Unit .



Found 1-bit xor3 for signal .

Summary:inferred 1 Xor(s).

Unit synthesized.

Synthesizing Unit .

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Unit synthesized.

Synthesizing Unit .






Unit synthesized.

======================================================

===================

HDL Synthesis Report

Macro Statistics

# Registers : 16

32-bit register : 16

# Xors : 4352

1-bit xor2 : 2561-bit xor3 : 4096

======================================================

===================

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======================================================

===================

* Advanced HDL Synthesis *

======================================================

===================

Loading device for application Rf_Device from file '3s50.nph' in

environment C:\Xilinx.

======================================================

===================

Advanced HDL Synthesis Report

Macro Statistics

# Registers : 32

Flip-Flops : 32

# Xors : 4352

1-bit xor2 : 256

1-bit xor3 : 4096

======================================================

===================

=========================================================================

* Low Level Synthesis *

======================================================

===================

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Optimizing unit ...

Optimizing unit ...

Optimizing unit ...

Mapping all equations...

WARNING:Xst:1291 - FF/Latch is unconnected in

block .


block .


block .

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block TOP_MODULE, actual

ratio is 4.

Final Macro Processing ...

======================================================

===================

Final Register Report

Macro Statistics

# Registers : 32

Flip-Flops : 32

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======================================================

===================

======================================================

===================* Partition Report *

======================================================

===================

Partition Implementation Status

-------------------------------

No Partitions were found in this design.

-------------------------------

======================================================

===================

* Final Report *

======================================================

===================

Final Results

RTL Top Level Output File Name : TOP_MODULE.ngr

Top Level Output File Name : TOP_MODULEOutput Format : NGC


Keep Hierarchy : NO

Design Statistics

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# IOs : 51

Cell Usage :

# BELS : 131

# LUT2 : 9# LUT2_D : 5

# LUT2_L : 1

# LUT3 : 20

# LUT3_D : 7

# LUT3_L : 7

# LUT4 : 55

# LUT4_D : 9

# LUT4_L : 12

# MUXF5 : 5

# VCC : 1

# FlipFlops/Latches : 32

# FDC : 32

# Clock Buffers : 1

# BUFGP : 1

# IO Buffers : 50

# IBUF : 17

# OBUF : 33

======================================================

===================

Device utilization summary:

---------------------------

Selected Device : 3s50pq208-5

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Number of Slices: 65 out of 768 8%

Number of Slice Flip Flops: 32 out of 1536 2%

Number of 4 input LUTs: 125 out of 1536 8%

Number of IOs: 51Number of bonded IOBs: 51 out of 124 41%

Number of GCLKs: 1 out of 8 12%

======================================================

===================

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS

ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO

THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------------------

-----------------------------------+------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+CLK | BUFGP | 32 |

-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

----------------------------------------

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-----------------------------------+------------------------+-------+

Control Signal | Buffer(FF name) | Load |

-----------------------------------+------------------------+-------+

RST | IBUF | 32 |

-----------------------------------+------------------------+-------+

Timing Summary:

---------------

Speed Grade: -5

Minimum period: 7.614ns (Maximum Frequency: 131.334MHz)

Minimum input arrival time before clock: 7.866ns

Maximum output required time after clock: 15.068ns

Maximum combinational path delay: 15.419ns

Timing Detail:

--------------

All values displayed in nanoseconds (ns)

======================================================

===================

Timing constraint: Default period analysis for Clock 'CLK'

Clock period: 7.614ns (frequency: 131.334MHz)

Total number of paths / destination ports: 1030 / 32-------------------------------------------------------------------------

Delay: 7.614ns (Levels of Logic = 5)

Source: m111[14].c0/yout_13 (FF)

Destination: m111[14].c0/yout_17 (FF)

Source Clock: CLK rising

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Destination Clock: CLK rising

Data Path: m111[14].c0/yout_13 to m111[14].c0/yout_17

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------

FDC:C->Q 6 0.626 0.912 m111[14].c0/yout_13

(m111[14].c0/yout_13)

LUT3_D:I2->O 2 0.479 0.804

m111[14].B0/g1[13].f0/cout1_SW0 (N995)

LUT4_D:I2->O 1 0.479 0.740

m111[14].B0/g1[14].f0/cout1_SW0 (N1019)

LUT4:I2->O 16 0.479 1.221

m111[14].B0/g1[12].f0/cout1_SW1 (N1035)

LUT2:I1->O 1 0.479 0.740 m111[14].B0/g1[16].f0/cout1_SW4

(N1098)

LUT4:I2->O 2 0.479 0.000

m111[14].B0/sixteenbit_fa1_014_xo1 (yout_17_OBUF)

FDC:D 0.176 m111[14].c0/yout_17

----------------------------------------

Total 7.614ns (3.197ns logic, 4.417ns route)

(42.0% logic, 58.0% route)

=========================================================================

Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'

Total number of paths / destination ports: 697 / 32

-------------------------------------------------------------------------

Offset: 7.866ns (Levels of Logic = 6)

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Source: X (PAD)

Destination: m111[14].c0/yout_17 (FF)

Destination Clock: CLK rising

Data Path: X to m111[14].c0/yout_17Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:I->O 4 0.715 1.074 X_13_IBUF (X_13_IBUF)

LUT3_D:I0->O 2 0.479 0.804

m111[14].B0/g1[13].f0/cout1_SW0 (N995)

LUT4_D:I2->O 1 0.479 0.740

m111[14].B0/g1[14].f0/cout1_SW0 (N1019)

LUT4:I2->O 16 0.479 1.221

m111[14].B0/g1[12].f0/cout1_SW1 (N1035)

LUT2:I1->O 1 0.479 0.740 m111[14].B0/g1[16].f0/cout1_SW4

(N1098)

LUT4:I2->O 2 0.479 0.000

m111[14].B0/sixteenbit_fa1_014_xo1 (yout_17_OBUF)

FDC:D 0.176 m111[14].c0/yout_17

----------------------------------------


(41.8% logic, 58.2% route)

======================================================

===================

Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'


-------------------------------------------------------------------------

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Source: m111[14].c0/yout_1 (FF)

Destination: cout (PAD)

Source Clock: CLK rising

Data Path: m111[14].c0/yout_1 to cout

Gate Net


---------------------------------------- ------------

FDC:C->Q 2 0.626 0.804 m111[14].c0/yout_1

(m111[14].c0/yout_1)

LUT4_D:I2->LO 1 0.479 0.159 m111[14].B0/g1[1].f0/cout1

(N1166)

LUT3:I2->O 4 0.479 0.802 m111[14].B0/g1[2].f0/cout1

(m111[14].B0/carry1)

LUT4_D:I3->O 5 0.479 1.078 m111[14].B0/g1[4].f0/cout1

(m111[14].B0/carry1)

LUT4:I0->O 1 0.479 0.976 m111[14].B0/g1[8].f0/cout1

(m111[14].B0/carry1)

LUT4:I0->O 1 0.479 0.976 m111[14].B0/g1[24].f0/cout1

(m111[14].B0/carry1)

LUT4:I0->O 1 0.479 0.704 m111[14].B0/g1[28].f0/cout1

(m111[14].B0/carry1)

LUT4:I3->O 1 0.479 0.681 m111[14].B0/g1[31].f0/cout1(C)

OBUF:I->O 4.909 cout_OBUF (cout)

----------------------------------------


(59.0% logic, 41.0% route)

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======================================================

===================

Timing constraint: Default path analysis



Source: X (PAD)

Destination: cout (PAD)

Data Path: X to cout

Gate Net


---------------------------------------- ------------

IBUF:I->O 3 0.715 1.066 X_0_IBUF (X_0_IBUF)

LUT4_D:I0->LO 1 0.479 0.159 m111[14].B0/g1[1].f0/cout1

(N1166)

LUT3:I2->O 4 0.479 0.802 m111[14].B0/g1[2].f0/cout1

(m111[14].B0/carry1)

LUT4_D:I3->O 5 0.479 1.078 m111[14].B0/g1[4].f0/cout1

(m111[14].B0/carry1)

LUT4:I0->O 1 0.479 0.976 m111[14].B0/g1[8].f0/cout1

(m111[14].B0/carry1)

LUT4:I0->O 1 0.479 0.976 m111[14].B0/g1[24].f0/cout1(m111[14].B0/carry1)

LUT4:I0->O 1 0.479 0.704 m111[14].B0/g1[28].f0/cout1

(m111[14].B0/carry1)

LUT4:I3->O 1 0.479 0.681 m111[14].B0/g1[31].f0/cout1

(C)

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OBUF:I->O 4.909 cout_OBUF (cout)

----------------------------------------


(58.2% logic, 41.8% route)

======================================================

===================

CPU : 427.25 / 428.26 s | Elapsed : 427.00 / 428.00 s

-->

Total memory usage is 217356 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 503 ( 0 filtered)

Number of infos : 0 ( 0 filtered)

SYNTHESIS REPORT OF Transposed FIR Filter

Release 8.2i - xst I.31

Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.

--> Parameter TMPDIR set to ./xst/projnav.tmp

CPU : 0.00 / 0.95 s | Elapsed : 0.00 / 1.00 s

--> Parameter xsthdpdir set to ./xst

CPU : 0.00 / 0.95 s | Elapsed : 0.00 / 1.00 s

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--> Reading design: TOP_MODULE.prj

TABLE OF CONTENTS

1) Synthesis Options Summary

2) HDL Compilation3) Design Hierarchy Analysis

4) HDL Analysis

5) HDL Synthesis

5.1) HDL Synthesis Report

6) Advanced HDL Synthesis

6.1) Advanced HDL Synthesis Report

7) Low Level Synthesis

8) Partition Report

9) Final Report

9.1) Device utilization summary

9.2) TIMING REPORT

======================================================

===================

* Synthesis Options Summary *

======================================================

===================

---- Source ParametersInput File Name : "TOP_MODULE.prj"

Input Format : mixed

Ignore Synthesis Constraint File : NO

---- Target Parameters

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Output File Name : "TOP_MODULE"

Output Format : NGC

Target Device : xc3s50-5-pq208

---- Source OptionsTop Module Name : TOP_MODULE

Automatic FSM Extraction : YES

FSM Encoding Algorithm : Auto

FSM Style : lut

RAM Extraction : Yes

RAM Style : Auto

ROM Extraction : Yes

Mux Style : Auto

Decoder Extraction : YES

Priority Encoder Extraction : YES

Shift Register Extraction : YES

Logical Shifter Extraction : YES

XOR Collapsing : YES

ROM Style : Auto

Mux Extraction : YES

Resource Sharing : YES

Multiplier Style : auto

Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES

Global Maximum Fanout : 500

Add Generic Clock Buffer(BUFG) : 8

Register Duplication : YES

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Slice Packing : YES

Pack IO Registers into IOBs : auto

Equivalent register Removal : YES

---- General OptionsOptimization Goal : Speed

Optimization Effort : 1

Keep Hierarchy : NO

RTL Output : Yes

Global Optimization : AllClockNets

Write Timing Constraints : NO

Hierarchy Separator : /

Bus Delimiter :

Case Specifier : maintain

Slice Utilization Ratio : 100

Slice Utilization Ratio Delta : 5

---- Other Options

lso : TOP_MODULE.lso

Read Cores : YES

cross_clock_analysis : NO

verilog2001 : YES

safe_implementation : No

Optimize Instantiated Primitives : NOuse_clock_enable : Yes

use_sync_set : Yes

use_sync_reset : Yes

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======================================================

===================

=========================================================================

* HDL Compilation *

======================================================

===================

WARNING:HDLParsers:3215 - Unit work/TOP_MODULE is now defined

in a different file: was D:/anupam MAURYA/anu maurya/fir_filter/opti.vhd,

now is D:/anupam MAURYA/anu maurya/fir_filter/mcm_block.vhd

WARNING:HDLParsers:3215 - Unit work/TOP_MODULE/Behavioral is

now defined in a different file: was D:/anupam MAURYA/anu

maurya/fir_filter/opti.vhd, now is D:/anupam MAURYA/anu

maurya/fir_filter/mcm_block.vhd

Compiling vhdl file "D:/anupam MAURYA/anu

maurya/fir_filter/mcm_block.vhd" in Library work.

Architecture behavioral of Entity top_module is up to date.

Architecture behavioral of Entity mcm_block_loop is up to date.

======================================================

===================

* Design Hierarchy Analysis *======================================================

===================


(architecture ) with generics.

m = 15

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(architecture ) with generics.

m = 15

Building hierarchy successfully finished.

======================================================

===================

* HDL Analysis *

======================================================

===================

Design Repository: return true for module

Analyzing generic Entity in library

(Architecture ).

m = 15


Design Repository: return true for module

Analyzing generic Entity in library

(Architecture ).

m = 15


======================================================

===================

* HDL Synthesis *

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======================================================

===================

Performing bidirectional port resolution...

Synthesizing Unit .


maurya/fir_filter/mcm_block.vhd".

Found 16x16-bit multiplier for signal .











Summary:

inferred 11 Multiplier(s).

Unit synthesized.

Synthesizing Unit .


maurya/fir_filter/mcm_block.vhd".



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Found 32-bit adder for signal created at line 81.




Found 32-bit adder for signal created at line 78.Found 32-bit adder for signal created at line 79.


















Found 32-bit register for signal .Found 32-bit register for signal .





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Summary:

inferred 512 D-type flip-flop(s).

inferred 15 Adder/Subtractor(s).

Unit synthesized.

======================================================

===================

HDL Synthesis Report

Macro Statistics

# Multipliers : 11

16x16-bit multiplier : 11

# Adders/Subtractors : 15

32-bit adder : 15

# Registers : 16

32-bit register : 16

======================================================

===================

======================================================

===================* Advanced HDL Synthesis *

======================================================

===================

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Loading device for application Rf_Device from file '3s50.nph' in

environment C:\Xilinx.

======================================================

===================Advanced HDL Synthesis Report

Macro Statistics

# Multipliers : 11

16x16-bit multiplier : 11

# Adders/Subtractors : 15

32-bit adder : 15

# Registers : 512

Flip-Flops : 512

======================================================

===================

======================================================

===================

* Low Level Synthesis *

======================================================

===================

INFO:Xst:2261 - The FF/Latch in Unit isequivalent to the following 15 FFs/Latches, which will be removed :

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WARNING:Xst:1710 - FF/Latch (without init value) has a

constant value of 0 in block .

WARNING:Xst:1710 - FF/Latch (without init value) has a

constant value of 0 in block .

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block

.

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch

(without init value) has a constant value of 0 in block

.



.



.



.



.


(without init value) has a constant value of 0 in block.



.

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.





.



.



.



.



.



.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch


.

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.





.



.



.



.



.





.

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.





.



.



.



.



.





.

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.





.



.



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.



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.

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.





.



.



.

INFO:Xst:2261 - The FF/Latch in Unit is

equivalent to the following FF/Latch, which will be removed :

Optimizing unit ...

Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block TOP_MODULE, actual

ratio is 43.

Final Macro Processing ...

Processing Unit :

Found 2-bit shift register for signal .

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Found 2-bit shift register for signal .Found 2-bit shift register for signal .


Unit processed.

======================================================

===================

Final Register Report

Macro Statistics

# Registers : 429

Flip-Flops : 429

# Shift Registers : 8

2-bit shift register : 8

======================================================

===================

======================================================

===================* Partition Report *

======================================================

===================

Partition Implementation Status

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-------------------------------

Preserved Partitions:

Implemented Partitions:

Partition "/TOP_MODULE":

There was no implementation for this Partition.

-------------------------------

Partition NGC Files

-------------------------------

Partition "/TOP_MODULE":

NGC File: TOP_MODULE.ngc

-------------------------------

======================================================

===================

* Final Report *======================================================

===================

Final Results

RTL Top Level Output File Name : TOP_MODULE.ngr

Top Level Output File Name : TOP_MODULE

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Output Format : NGC


Keep Hierarchy : NO

Design Statistics# IOs : 50

Cell Usage :

# BELS : 1777

# GND : 1

# INV : 1

# LUT1 : 101

# LUT2 : 491

# LUT3 : 12

# MUXCY : 593

# VCC : 1

# XORCY : 577

# FlipFlops/Latches : 437

# FDC : 32

# FDE : 405

# Shift Registers : 8

# SRL16E : 8

# Clock Buffers : 1

# BUFGP : 1# IO Buffers : 49

# IBUF : 17

# OBUF : 32

# MULTs : 4

# MULT18X18 : 4

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======================================================

===================

Device utilization summary:

---------------------------

Selected Device : 3s50pq208-5

Number of Slices: 331 out of 768 43%

Number of Slice Flip Flops: 437 out of 1536 28%

Number of 4 input LUTs: 613 out of 1536 39%

Number used as logic: 605

Number used as Shift registers: 8

Number of IOs: 50

Number of bonded IOBs: 50 out of 124 40%

Number of MULT18X18s: 4 out of 4 100%

Number of GCLKs: 1 out of 8 12%

======================================================

===================

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESISESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO

THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

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Clock Information:

------------------

-----------------------------------+------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+clk | BUFGP | 445 |

-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

----------------------------------------

-----------------------------------+------------------------+-------+

Control Signal | Buffer(FF name) | Load |

-----------------------------------+------------------------+-------+

rst | IBUF | 32 |

-----------------------------------+------------------------+-------+

Timing Summary:

---------------

Speed Grade: -5

Minimum period: 5.018ns (Maximum Frequency: 199.288MHz)

Minimum input arrival time before clock: 11.320ns

Maximum output required time after clock: 6.216ns

Maximum combinational path delay: No path found

Timing Detail:

--------------

All values displayed in nanoseconds (ns)

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======================================================

===================

Timing constraint: Default period analysis for Clock 'clk'

Clock period: 5.018ns (frequency: 199.288MHz)



Source: ADD4_31 (FF)

Destination: ADD5_0 (FF)

Source Clock: clk rising

Destination Clock: clk rising

Data Path: ADD4_31 to ADD5_0

Gate Net


---------------------------------------- ------------

FDE:C->Q 1 0.626 0.851 ADD4_31 (ADD4_31)

LUT2:I1->O 2 0.479 0.000 Madd__add0010_lut (N78)

MUXCY:S->O 1 0.435 0.000 Madd__add0010_cy

(Madd__add0010_cy)

MUXCY:CI->O 1 0.056 0.000 Madd__add0010_cy

(Madd__add0010_cy)


(Madd__add0010_cy)MUXCY:CI->O 1 0.056 0.000 Madd__add0010_cy

(Madd__add0010_cy)


(Madd__add0010_cy)

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(Madd__add0010_cy)


(Madd__add0010_cy)

MUXCY:CI->O 1 0.056 0.000 Madd__add0010_cy(Madd__add0010_cy)


(Madd__add0010_cy)


(Madd__add0010_cy)


(Madd__add0010_cy)


(Madd__add0010_cy)


(Madd__add0010_cy)


(Madd__add0010_cy)


(Madd__add0010_cy)


(Madd__add0010_cy)


(Madd__add0010_cy)MUXCY:CI->O 1 0.056 0.000 Madd__add0010_cy

(Madd__add0010_cy)


(Madd__add0010_cy)

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(Madd__add0010_cy)


(Madd__add0010_cy)



(Madd__add0010_cy)


(Madd__add0010_cy)


(Madd__add0010_cy)


(Madd__add0010_cy)


(Madd__add0010_cy)


(Madd__add0010_cy)


(Madd__add0010_cy)


(Madd__add0010_cy)


(Madd__add0010_cy)XORCY:CI->O 1 0.786 0.000 Madd__add0010_xor

(_add0010)

FDE:D 0.176 ADD5_0

----------------------------------------


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(83.0% logic, 17.0% route)

======================================================

===================

Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'Total number of paths / destination ports: 421789 / 846

-------------------------------------------------------------------------


Source: x (PAD)

Destination: ADD14_0 (FF)

Destination Clock: clk rising

Data Path: x to ADD14_0

Gate Net


---------------------------------------- ------------

IBUF:I->O 32 0.715 1.870 x_13_IBUF (x_13_IBUF)

LUT2:I0->O 1 0.479 0.000

MCM_BLOCK/Mmult_mcm14_Madd_lut

(MCM_BLOCK/Mmult_mcm14_Madd_2)

MUXCY:S->O 1 0.435 0.000

MCM_BLOCK/Mmult_mcm14_Madd_cy

(MCM_BLOCK/Mmult_mcm14_Madd_cy)

MUXCY:CI->O 1 0.056 0.000MCM_BLOCK/Mmult_mcm14_Madd_cy


MUXCY:CI->O 1 0.056 0.000



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MUXCY:CI->O 1 0.056 0.000



MUXCY:CI->O 1 0.056 0.000

MCM_BLOCK/Mmult_mcm14_Madd_cy(MCM_BLOCK/Mmult_mcm14_Madd_cy)

MUXCY:CI->O 1 0.056 0.000



MUXCY:CI->O 1 0.056 0.000



XORCY:CI->O 2 0.786 1.040

MCM_BLOCK/Mmult_mcm14_Madd_xor

(MCM_BLOCK/Mmult_mcm14_Madd_9)

LUT2:I0->O 1 0.479 0.000

MCM_BLOCK/Mmult_mcm14_Madd2_lut (N410)

MUXCY:S->O 1 0.435 0.000

MCM_BLOCK/Mmult_mcm14_Madd2_cy

(MCM_BLOCK/Mmult_mcm14_Madd2_cy)

MUXCY:CI->O 1 0.056 0.000



MUXCY:CI->O 1 0.056 0.000MCM_BLOCK/Mmult_mcm14_Madd2_cy


MUXCY:CI->O 1 0.056 0.000



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MUXCY:CI->O 1 0.056 0.000



MUXCY:CI->O 1 0.056 0.000

MCM_BLOCK/Mmult_mcm14_Madd2_cy(MCM_BLOCK/Mmult_mcm14_Madd2_cy)

MUXCY:CI->O 1 0.056 0.000



MUXCY:CI->O 1 0.056 0.000



MUXCY:CI->O 1 0.056 0.000



MUXCY:CI->O 1 0.056 0.000



XORCY:CI->O 1 0.786 0.976

MCM_BLOCK/Mmult_mcm14_Madd2_xor (mcm14)

LUT2:I0->O 1 0.479 0.000 Madd__add0005_lut (N532)

MUXCY:S->O 1 0.435 0.000 Madd__add0005_cy

(Madd__add0005_cy)



(Madd__add0005_cy)


(Madd__add0005_cy)

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(Madd__add0005_cy)


(Madd__add0005_cy)



(Madd__add0005_cy)


(Madd__add0005_cy)


(Madd__add0005_cy)


(Madd__add0005_cy)


(Madd__add0005_cy)

XORCY:CI->O 1 0.786 0.000 Madd__add0005_xor

(_add0005)

FDE:D 0.176 ADD14_0

----------------------------------------


(65.7% logic, 34.3% route)

=========================================================================

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'


-------------------------------------------------------------------------


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Source: YOUT_0 (FF)

Destination: YOUT (PAD)

Source Clock: clk rising

Data Path: YOUT_0 to YOUTGate Net


---------------------------------------- ------------

FDC:C->Q 1 0.626 0.681 YOUT_0 (YOUT_0)

OBUF:I->O 4.909 YOUT_0_OBUF (YOUT)

----------------------------------------


(89.0% logic, 11.0% route)

======================================================

===================

CPU : 54.53 / 55.66 s | Elapsed : 55.00 / 56.00 s

-->

Total memory usage is 153932 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 54 ( 0 filtered)Number of infos : 2 ( 0 filtered)

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BIBLIOGRAPHY

Following is the list of books from which help has been taken

for the completion of this project.

1 VHDL-PRIMER J.Bhasker

2 MODERN DIGITAL ELECTRONICS R.P.Jain

3 DIGITAL DESIGN MorisMano

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Opti FIR Report

Documents

Transcript of Opti FIR Report