Oops conceps

7/29/2019 Oops conceps

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OOPS Concepts

System Verilog


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qSystemVerilog is a hardware description and Verification language(HDVL)

qSystemVerilog is an extensive set of enhancements to IEEE 1364 Verilog-2001 standards

qIt has features inherited from Verilog HDL,VHDL,C,C++

qAdds extended features to verilog

What is SystemVerilog?


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Verilog Shortcomings

Verilog

Static components

Deals at low lever of abstraction

Scenario Generation

Declaring a transaction

Passing transaction from one component to

another

Ex: USB Frame

Result Checking


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Summary of Verilog Shortcoming

Module can not take care of Complexframe declaration

Being static in nature, difficult to

declared dynamic scenario

Module can not be declared in array

Module can not be passed as argument

Module can not be take care ofencapsulation,inheritance for futurerevisions


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Shortcoming Cont..

BFM does not support module

DPI

FunctionalCoverage Connecting Components

Event scheduling

Polymorphism


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SystemVerilog Features

Literal Values : Logic

Arrays : Dynamic in Nature

Ex: Queue, Assoc. Array, Dynamic Array

Class

Encapsulation, Inheritance, Polymorphism

Random Constraints Inter Process Synchronization


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SystemVerilog Features Contd

Scheduling Scemantics

Clocking Blocks

Program Block Assertions

Interface

Functional Coverage DPI


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Introduction

Objects are the building blocks of OOP

technology

The key fetures to understand OOPs is that

object basically have two aspects

State

Behavior


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OOPS concepts

Class

Object

Properties Method

Inheritance

Encapsulation Polymorphism


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Class

Central point of OOP

Defines the properties and behavior of objects

made of that class

class packet;

bit [31:0] data;

function write_data; endfunctionfunction read_data; endfunction

endclass


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Object

Class is the central point of OOPS

Object is the basic unit of object orientation

with behavior, identity and state

An object is expresed by the variables and

methods of that class

packet p1, p2;

p1 = new();

p2 = new();


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Variables & Methods

Attributes are defined by variables and

behaviors are represented by methods

Methods define the abilities of an object.


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Inheritance

Inheritance is a mechanism of reusing and

extending existing classes without modifying

them. Subclass inherits all members of parents

The objects are distinguished from each other

by some attributes but share some/most ofthe common attributes

Better data analysis

Reduces development time


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Example

Class packet;

data [255:0];

function set_data;

endclass

Class packet_A

extends packet;

function get_data;

endclass

data,set_data are members of class packet

Data, set_data are members of classpacket_A

get_data is the additioonal member that

packet_A has


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Encapsulation

Seprating objects state from its behavior

This helps in hiding an object's data describing

its state from any further modification by

external component In system verilog, we have three types data

hding mechanism

Private members

Protected members

Public members


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Polymorphism

Polymorphism means many shapes

Functions can be implemented with the same

name but behaviour is different and correct

execution takes place at run time


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System Verilog


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Introduction

System verilog is built on top of verilog

Improves the readability, productivity,

reusability of verilog based code

Help to create more concise HW description

Extensive support for directed and constrained

random testbench , coverage driven

verification, assertion based erification


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New constructs

Extensions to data types for betterencapsulation and compactness of code and

for tighter specification

C data types: int, typedef, struct, union, enum

bounded queues, logic (0, 1, X, Z) and bit (0, 1),

tagged unions for safety

Dynamic data types: string, classes, dynamic

queues, dynamic arrays, associative arraysincluding automatic memory management

freeing users from de-allocation issues

dynamic casting and bit-stream casting

Automatic/static variables


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Extended operators for concise

description Wild equality and inequality

built-in methods

operator overloading

streaming operators

byte q[$];

Packet p = new;void(p.randomize()); q = {


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Extended procedural statements

pattern matching on selection statements for

use with tagged unions

enhanced loop statements plus the foreach

statement C like jump statements: return, break, continue

final blocks that executes at the end of

simulation (inverse of initial)

extended event control and sequence events


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Enhanced process control

Extensions to always blocks to include

synthesis consistent simulation semantics

Extensions to forkjoin to model pipelines and

for enhanced process control Fine-grain process control


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Enhanced tasks and functions

C like void functions

pass by reference

default arguments

pass by name

optional arguments

import/export functions for DPI (DirectProgramming Interface)


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Classes: Object-Oriented mechanism that

provides abstraction, encapsulation, and safe

pointer capabilities

Automated testbench support with randomconstraints

Interprocess communication synchronization

semaphores mailboxes

event extensions, event variables, and event

sequencing


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Clarification and extension of the scheduling

semantics

Cycle-Based Functionality: Clocking blocks

and cycle-based attributes that help reducedevelopment, ease maintainability, and

promote reusability:

cycle-based signal drives and samples synchronous samples

race-free program context


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Assertions

Extended hierarchy support

Interfaces to encapsulate communication

Functional coverage


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Scheduling semantics

A time slot is divided into a set of orderedregions:

Preponed - Reactive

Pre-active - Postponed

Active

Inactive

Pre-NBA NBA

Post-NBA

Observed


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The purpose of dividing a time slot into theseordered regions is to provide predictable

interactions between the design and

testbench code. This allows properties and checkers to sample

data when the design under test is in a stable

state


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Data Type


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Integer data type

Shortint : 2-state SystemVerilog data type, 16 bit signed integer

Int : 2-state SystemVerilog data type, 32 bit signed integer

Longint : 2-state SystemVerilog data type, 64 bit signed integer

byte :2-state SystemVerilog data type, 8 bit signed integer or ASCII

character

bit :2-state SystemVerilog data type, user-defined vector size

logic: 4-state SystemVerilog data type, user-defined vector size

reg :4-state Verilog-2001 data type, user-defined vector size integer: 4-state Verilog-2001 data type, 32 bit signed integer

time :4-state Verilog-2001 data type, 64-bit unsigned integer


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Signed and unsigned data types

Bit signed [7:0] si_h;

Bit unsigned [7:0] unsi_h;

Byte by_h;

si_h='hff; unsi_h ='hff ; by_h='hff

(*_h=='hff) all will return TRUE (*_h==-1) unsi_h will return FALSE,rest two will

return TRUE


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Void data type:

Non existant data

Can be assigned as a return type of function

chandle data type

The chandle data type represents storage for

pointers passed using the DPI Direct

Programming Interface The size of this type is platform dependent, but

shall be at least large enough to hold a pointer

on the machine in which the tool is running.

class


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String data type

Variable size

Dynamically allocated array of bytes

Provides special method to work on strings

Len, putc,getc,

Toupper, tolower,compare

atoi(), atohex(), atooct(), atobin()


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Event Data Type

SystemVerilog events provide a handle to

a synchronization object

an event variable can be assigned another

event variable or the special value null

When assigned another event variable, both

event variables refer to the same

synchronization object. When assigned null, the association between

the synchronization object and the event

variable is broken


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event done; // declare a new event called done

event done_too = done; // declare done_too as

alias to done

event empty = null; // event variable with no

synchronization object


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Structures and unions

struct { bit [7:0] opcode; bit [23:0] addr; }IR;

typedef struct {

bit [7:0] opcode;

bit [23:0] addr;

} instruction; // named structure type

instruction IR; // define variable


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Arrays

An array is a collection of variables, all of thesame type, and accessed using the same

name plus one or more indices


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Packed and unpacked arrays

Packed array: represented as continuous setof bits

Unpacked array:may or may not be

represented as coontinuous set of bits Packed array:bit [7:0] c;

Unpacked array: bit c [7:0],bit c [8]


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Multidiomensional array

Reg [7:0][9:0] a [8];

Then a [i] [j] [k]


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Dynamic arays

A dynamic array is one dimension of anunpacked array whose size can be set or

changed at runtime. The space for a dynamic

array doesnt exist until the array is explicitlycreated at runtime.

data_type array_name [];

Functions new(),delete(),,size()

i i


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Associative arrays

Dynamic arrays are useful for dealing withcontiguous collections of variables whose

number changes dynamically. When the size

of the collection is unknown or the dataspace is sparse, an associative array is a

better option.

Associative arrays do not have any storage

allocated until it is used

the index expression is not restricted to integral

expressions, but can be of any type.

*

A i i h d


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Associative array methods

num(),delete(index), exists(string) first(index), last(index),next(index),prev(index)

QUEUE


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QUEUE

int q[$] Queue ie generally first in first out, but there

are methods to insert and delete entries with

index Size(), insert(),delete()

push_back(),push_front()

pop_back(),pop_front()

A i t


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Assignment

Make the asynchronous tb usingQUEUEs,Dynamic Arrays.

CLASS


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CLASS

SystemVerilog introduces an object-orientedclass data abstraction

Classes allow objects to be dynamically

created, deleted, assigned, and accessed viaobject handles

Object handles provide a safe pointer-like

mechanism to the language. Classes offer inheritance and abstract type

modeling

class Packet ;//data or class properties


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bit [3:0] command; bit [40:0] address; bit [4:0]

master_id;

integer time_requested; integer time_issued;

integer status; // initialization

function new(); command = IDLE;

address = 41b0; master_id = 5bx;

endfunction

task clean();

command = 0; address = 0; master_id = 5bx;

endtask

Objects (class instance)


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Objects (class instance)

Packet p; // declare a variable of class Packet p = new; // initialize variable to a new

allocated object of the class Packet

Calling tasks

p.current_status();

Simple Class


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Simple Class

class basicframe;logic [3:0] addr;

logic [7:0] data;

// explicit constructor

function new(input logic [3:0]pa);

addr = pa;

data = $urandom;

endfunction

function void print();

$display("%h %h",addr,data);

endfunction

endclass

class basicframe;logic [3:0] addr;

logic [7:0] data;

// explicit constructor

function new(input logic [3:0]pa);

addr = pa;

data = $urandom;endfunction


$display("%h %h",addr,data);

endfunction

endclass

Class declarationProperties/Methods

Full access to all members

Object variable (handle) defined of aspecific class type

Class instance created with constructorExplicit or implicit method new

basicframe one =

new(.pt(3));

basicframe two;

initial begintwo = new(.pt(address));

one.addr = 4;

one.print(); // 4 75

...

basicframe one =

new(.pt(3));

basicframe two;

initial begintwo = new(.pt(address));

one.addr = 4;

one.print(); // 4 75

...

Inheritance


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Inheritanceclass parent;

logic [3:0] avec;logic abit;

function voidprint();$display("%d %d", avec, abit);

endfunction

endclass

class child extends parent;int avec;byte abyte;

function voidprint();$display("%0d %b %h", avec, abit, abyte);

endfunction

endclass

class parent;

logic [3:0] avec;

logic abit;

function voidprint();$display("%d %d", avec, abit);

endfunction

endclass

class child extends parent;int avec;byte abyte;

function voidprint();$display("%0d %b %h", avec, abit, abyte);

endfunction

endclass

A class declaration can extend an existingclass.Inheritance

Subclass inherits all members of parent.Can over-ride parent's members

Parent members are accessed as if theywere members of the subclass.

child one = new();

initial begin

one.avec = 0;

one.abit = 1'b1;

one.abyte = 8'hff;

one.print(); // 0 1 ff

...

child one = new();

initial begin

one.avec = 0;

one.abit = 1'b1;

one.abyte = 8'hff;

one.print(); // 0 1 ff

...

Inheritance and Constructors


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Inheritance and Constructors

class parent;

logic p1;

function new(input logic a1);p1 = a1;

endfunction

endclass

class child extends parent;logic c1;

function new(input logic a1, a2);super.new(a1);c1 = a2;

endfunction


$display("%b %b", p1, c1);

endfunction

endclass

class parent;

logic p1;

function new(input logic a1);p1 = a1;

endfunction

endclass

class child extends parent;logic c1;

function new(input logic a1, a2);super.new(a1);c1 = a2;

endfunction


$display("%b %b", p1, c1);

endfunction

endclass

Parent constructor is implicitly called as first line of subclassconstructor.

Parent constructor must be explicitlycalled to passarguments.

Must be the first line of subclass constructor

Prefix super allows a subclass to access parent members .

Otherwise hidden by subclass members

child one = new(1'b0, 1'b0);

initial begin

one.b1 = 1'b1;

one.print(); // 1 0...

child one = new(1'b0, 1'b0);

initial begin

one.b1 = 1'b1;

one.print(); // 1 0...

Assignment renaming copying


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Assignment, renaming, copying

Packet p1; p1 = new;

Packet p2; p2 = p1;

P1

P1

P2 P1


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Shallow copy

Packet p1;

Packet p2;

p1 = new;

p2 = new p1;

Deep copy

Packet p1 = new;

Packet p2 = new;

p2.copy(p1);

Overridden members


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class Packet; integer i = 1;

function integer get();

get = i;

endfunction

endclass

class LinkedPacketextends Packet;

integer i = 2;

function integer get(); get = -i;

endfunction

endclass

To call the overridden method via a parent class object (p in theexample), the method needs to be declared

virtual

Virtual Method


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Virtual Method

virtual classBasePacket;

virtual function

integersend(bit[31:0]

data);

endfunction

endclass

class EtherPacketextends

BasePacket;

function integersend(bit[31:0]

data);

// body of the

function

endfunction

endclass


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Virtual class can not be instantiated All the methods of abstract class should be

overriden

Useful subclasses can be derived Virtual methods can be overdriven

Polymophism:Dynamic-


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MethodLookup polymorphism allows the use of a variable in

the superclass to hold subclass objects,

It allows reference the methods of those

subclasses directly from the superclass

variable BasePacket packets[100];

EtherPacket ep = new;// extends BasePacket

TokenPacket tp = new;// extends BasePacket

GPSSPacket gp = new;// extends BasePacket

packets[0] = ep;

packets[1] = tp;


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packets[1].send(); It shall invoke the send method associated with

the TokenPacket class

Interface


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Interface

interface simple_bus; logic req, gnt;

logic [7:0] addr, data;

logic [1:0] mode;

logic start, rdy;

endinterface:simple_bus

modulememMod(simple_b

us a, input bit clk);

logic avail; always @(posedge

clk) a.gnt


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module top; logic clk = 0;

simple_bus sb_intf();

memMod mem

(sb_intf, clk);

cpuMod cpu

(.b(sb_intf),.clk(clk));

endmodule

modulecpuMod(simple_bu

s b, input bit clk);

... endmodule


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interface i2; wire a, b, c, d;

modport master (input a, b, output c, d);

modport slave (output a, b, input c, d);

endinterface

Program Block


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Program Block

The program block serves three basicpurposes:

It provides an entry point to the execution of

testbenches.

It creates a scope that encapsulates program-

wide data.

It provides a syntactic context that specifies

scheduling in the Reactive region.


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module test(...) int shared;

program p1;

...; endprogram

program p2;

...; endprogram endmodule


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A program block can contain one or more initialblocks. It cannot contain always blocks, UDPs,

modules,interfaces, or other programs.

Type and data declarations within the program are

local to the program scope and have static lifetime.

Program variables can only be assigned using

blocking assignments.

Non-program variables can only be assigned usingnonblocking assignments.

References to program variables from outside any

pro-gram block shall be an error.

Eliminating race conditions


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g

Program block helps to avoid DUT/TB raceconditions as they are supposed to execute

in reactive region

Queue


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qData storage array [$]Variable size array with automatic sizing

Searching, sorting and insertion methods

Mailbox


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q Fifo with flow controlpasses data between two processes

put() stimgen calls put() to pass data to bfm

get() bfm calls get() to retrieve data from stimgen

mailbox

stimgen bfm

put() get()

Mailbox


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mailbox mbx;

mbx = new(); // allocate mailbox

mbx.put(data); // Put data object into mailbox

mbx.get(data); // data will be updated with data from FIFO

success = mbx.try_get(ref data); // Non-blocking version

mbx.peek(data); // Look but dont remove

count = mbx.num(); // Number of elements in mailbox

mailbox mbx;

mbx = new(); // allocate mailbox

mbx.put(data); // Put data object into mailbox

mbx.get(data); // data will be updated with data from FIFO

success = mbx.try_get(ref data); // Non-blocking version

mbx.peek(data); // Look but dont remove

count = mbx.num(); // Number of elements in mailbox

Fork/join

k j i


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join

fork

Fork/join

Initial

Begin

Clk =0;

#5

Fork#5 a = 0;

#10 b = 0;

Join

Clk= 1;

end

Clkbecomes 1

at t=15

Fork/join

F k/j i


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Join_any

fork

Fork/join_any

Clkbecomes 1

at t=10

Initial

Begin

Clk =0;

#5

Fork#5 a = 0;

#10 b = 0;

Join_any

Clk= 1;

end

Fork/join

F k/j i


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Join_none

fork

Fork/join_none

Clkbecomes 1

at t=5

Initial

Begin

Clk =0;

#5

Fork#5 a = 0;

#10 b = 0;

Join_none

Clk= 1;

end

Semaphore


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qUsed for SynchronizationVariable number of keys can be put and removed

controlled access to a shared object

think of two people wanting to drive the same car the key is asemaphore

Constraint

qControl randomization


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qControl randomizationValues for random variable can be controlled through constraintexpressions

These are declared within constraint block

Class packet ;rand logic [7:0] src;

rand logic [7:0] dest;

Constraint my_constraints {

src[1:0] == 2b00; // constraint expression // always set src[1:0] to 0

}

endclass:packet

Class packet ;rand logic [7:0] src;

rand logic [7:0] dest;

Constraint my_constraints {

src[1:0] == 2b00; // constraint expression

// always set src[1:0] to 0

}

endclass:packet

Covergroup


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qCaptures results from a randomsimulation

qEncapsulates the coverage

specification

bins

transitions

Covergroup check @(posedge top.valid );

coverpoint global;

coverpoint top.test;

endgroup:check

check chk = new();

Covergroup check @(posedge top.valid );

coverpoint global;

coverpoint top.test;

endgroup:check

check chk = new();

Program Block

q Benefits:


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q Benefits:

Encapsulates the testbench

Separates the testbench from theDUT

Provides an entry point for execution

Creates a scope to encapsulateprogram-wide data

q Functionality:

Can be instantiated in any

hierarchical location

Typically at the top level

Ports can be connected in the same

manner as any other module

Program Block

qTh t tb h ( )


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qThe testbench (program) runs

separately from design (module) Triggered by clock

Samples just before clock edge, drives just after clock

clock

Sampl

e

inputs

Drive

output

s

Design

Testbench

Interface


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qbundling of port signalsprovide an abstract encapsulation of communication betweenblocks

Directional information (modports)

Timing (clocking blocks)

Functionality (routines,assertions)

device1 device2interface

Interface

Interface:An example


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Interface bus_a (input clock);

logic [7:0] address;

logic [31:0] data ;

bit valid ;

bit rd_wr ;

Endinterface: bus_a

Interface bus_a (input clock);

logic [7:0] address;

logic [31:0] data ;

bit valid ;

bit rd_wr ;

Endinterface: bus_a

Interface:An example


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Clocking Block

qC b d l d i id


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qCan be declared inside

interface,module or program

Clocking Block

Module M1(ck, enin, din, enout, dout);

Module M1(ck, enin, din, enout, dout);


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input ck,enin;

input [31:0] din ;

output enout ;

output [31:0] dout ;

clocking sd @(posedge ck);

input #2ns ein,din ;

output #3ns enout, dout;

endclocking:sd

reg [7:0] sab ;

initial begin

sab = sd.din[7:0];

end

endmodule:M1

input ck,enin;

input [31:0] din ;output enout ;

output [31:0] dout ;

clocking sd @(posedge ck);

input #2ns ein,din ;

output #3ns enout, dout;

endclocking:sd

reg [7:0] sab ;initial begin

sab = sd.din[7:0];

end

endmodule:M1

Signals will be sampled 2nsbefore posedge ck

Signals will be driven 3nsafter posedge ck

Modports

qAn interface can have multiple


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qAn interface can have multiple

viewpointsMaster/Slave, Transmitter/Receiver

qThese can be specified usingmodports

Interface bus_b (input clock);

logic [7:0] addr,data;

logic [1:0] mode ;

bit ready ;

modport master (input ready,output addr,data,mode) ;

modport slave (input addr,data,mode,output ready) ;

endinterface: bus_b

Interface bus_b (input clock);

logic [7:0] addr,data;

logic [1:0] mode ;

bit ready ;

modport master (input ready,output addr,data,mode) ;

modport slave (input addr,data,mode,output ready) ;

endinterface: bus_b

All signal names in amodport must bedeclared in the

interface

Conclusion


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q Some of SystemVerilog Testbench constructs were discussed

qBut still a long way to go..


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Thank you

References

Websources:


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1. www.systemverilog.org

2. www.asic-world.com/systemverilog/index.html

3. http://svug.org/

Books :

1. Writing Testbenches using SystemVerilog

- Janick Bergeron

2. Verification Methodology Manual

- Janick Bergeron

3. SystemVerilog For Verification

- Chris Spear

Test Cases


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MEMORY DUT

DRIVER MONITOR

SCOREBOARD

SEQUENCER

ENV

Test Cases

Interface

Test Bench

Assertions

Assignment


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Designing TB using Program Block

Oops conceps

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