On the Relation between SAT and BDDs for Equivalence Checking

On the Relation between SAT and BDDs for Equivalence Checking

On the Relation between SAT and BDDs for Equivalence Checking

Sherief Reda Rolf Drechsler Alex OrailogluSherief Reda Rolf Drechsler Alex OrailogluComputer Science &

Engineering Dept.Computer Science &

Engineering Dept.

University of California, San Diego


Institute of Computer Science University of Bremen

Institute of Computer Science University of Bremen

Computer Science & Engineering Dept.

Computer Science & Engineering Dept.



OutlineOutline

IntroductionBDDsThe Davis-Putnam (DP) ProcedureEquivalence Checking

BDD-DP RelationCharacteristics of CNF Formulas of Logic CircuitsRelation between BDD and the DPDynamic Variable Ordering for the DP Procedure

Experimental Results

Conclusions

Open questions

IntroductionIntroduction

BDDs have been traditionally used in logic synthesis and verification

New Boolean satisfiability (SAT) solvers have shown recent promise as efficient equivalence checkers

It is essential to understand the relation between BDDs and SAT procedures and show how the techniques of one domain can be applied to the other

Binary Decision DiagramsBinary Decision Diagrams

ROBDDs are produced through the repeated application of

Redundant test elimination

Equivalent sub-graph sharing

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The Davis-Putnam ProcedureThe Davis-Putnam Procedure

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assign(sat_formula , literal v)begina1. v = true;a2. simplify ;a3. apply unit clause propagation;a4. if has an empty clause then return false else return true;end

DP(sat_formula )begind1. choose literal v to split on;d2. if v = NULL then return true;d3. if assign(, v) then d4. if DP() then return true;d5. undo v assignment;d6. if assign(, v) then d7. if DP() then return true;d8. return false;end

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= (a + d) (b + d) (a + b + d) (c + z) (d + z) (d + c + z).

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By unit clause propagation

By unit clause propagation

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1 Consistent assignment achieved

The Davis-Putnam ProcedureThe Davis-Putnam Procedure

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= (a + d) (b + d) (a + b + d) (c + z) (d + z) (d + c + z).

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dBy unit clause propagation

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1 By unit clause propagation

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assign(sat_formula , literal v)begina1. v = true;a2. simplify ;a3. apply unit clause propagation;a4. if has an empty clause then return false else return true;end

DP(sat_formula )begind1. choose literal v to split on;d2. if v = NULL then return true;d3. if assign(, v) then d4. if DP() then return true;d5. undo v assignment;d6. if assign(, v) then d7. if DP() then return true;d8. return false;end

Equivalence CheckingEquivalence Checking

Core equivalence checking techniques

Using BDDsBuild the BDD of each circuit under verification and check that the BDDs are isomorphic

Using SATCheck that the stuck-at-0 SAT formula of the miter circuit is unsatisfiable

Circuit I

Circuit II

Miter outputPrimary

Input

Equivalence checking can be viewed as

Equivalence CheckingEquivalence Checking

A search in the decision trees of the two circuits for a path that leads to the terminal 1(0) in one but leads to the 0(1) terminal in the other.

Decision tree of Circuit I

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Decision tree of Circuit II

Minimization of the number of paths to be compared

Minimization of equivalence checking time

Characteristics of CNF Formulas of Logic CircuitsCharacteristics of CNF Formulas of Logic Circuits

It is possible to find a set of variables P() V() such that can be satisfied by only splitting on the variables of P() in the DP procedure.

Let be a CNF formula generated from a logic circuit

Let V() be the set of variables that depends on

P() is the set of primary inputs

Reducing the number of decision variables introduces an overall reduction in the decision tree size


Let S denote the set of primary inputs currently assigned logic values under the assignment As

If As is applied to , the resultant is the logic function fAs

If v P() but v S then v is said to be redundant under As if fAs /v = 0

A CNF formula is satisfied under a truth assignment As of a set S P() if v(P()-S): fAs /v = 0

If the primary output variable is assigned a value under the current assignment then there is no point in further assignments

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= (a + d) (b + d) (a + b + d) (c + z) (d + z) (d + c + z) P() = {a, b, c} = z

If S = {a} and Bs={a 1}

then = (d) (b + d) (c + z) (d + z) (d + c + z)

1 a

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If S = {a} and Bs={a 1}

then = (d) (b + d) (c + z) (d + z) (d + c + z)

1 a

Under Bs fBs/b = 0 b is redundant

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If S = {c} and As={c 0} then z 0 and = (a + d) (b + d) (a + b + d).

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Under As both fAs/a and fAs/b = 0 a & b are redundant

If S = {c} and As={c 0} then z 0 and = (a + d) (b + d) (a + b + d).

0 0c


Observation 1: DP decision space is reduced to be that of the primary inputs

Observation 2: Redundant variables are not considered for decision in the DP procedure

Observation 1 reduces the decision space to be like that of a BDD and observation 2 parallels the removal of redundant test in BDDs.

Given a BDD and a CNF formula for a logic circuit C, then under a variable ordering and a truth assignment A on a certain path of to

the terminal, is satisfiable using the same variable ordering and truth assignment.

Relation between BDD and DP Relation between BDD and DP

The equivalence checking problem between two circuits can be viewed as a search in the decision trees of the two circuits for a path that leads to the terminal 1(0) in one but leads to the 0(1) terminal in the other.

Decision tree of Circuit I

Decision tree of Circuit II

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Relation between BDD and DP Relation between BDD and DP

BDD-DP Theorem For BDD with P paths and a CNF formula for a logic circuit C then if DP variable ordering strategy captures the same ordering for every path of , then DP proves the equivalence of C against an equivalent version in P-1 backtracks.

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Decision space of circuit I Decision space circuit II

9 paths in the BDD implies 8 backtracks in the CNF formula

Dynamic Variable Ordering for the DP ProcedureDynamic Variable Ordering for the DP Procedure

The variable ordering strategy should differ for every path of the decision tree

DP dynamic variable ordering strategy should

No splitting on redundant variables

Minimum number of splittings to reach the terminals

Assign a weight of 1.0 to the primary output

For each circuit level from output to input:

Divide the weight of the unbounded gate output among its inputs

Accumulate the weight of the fan-out branches into the fan-out stem

Return the PI with the largest weight

Var_Choose()


The proposed dynamic variable ordering represent the structural impact of every primary input of the circuit

Assigns a weight of zero to redundant variables

Tries to minimize the number of assignments to the terminals by splitting on the primary input with the largest weight

The weights reflect structural properties of the circuit and should be considered as a heuristic to the optimal case

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For this example, the variable ordering that minimizes the number of BDD nodes (4) also minimizes the number of paths (6)

DP procedure proved the equivalence in an optimal number of 5 backtracks

In this case, the proposed dynamic variable ordering strategy faithfully captured the variable ordering of the minimum size BDD

BDD number of nodes and number of pathsBDD number of nodes and number of paths

Questions that need answering

I. Is there a relation between the number of nodes and the number of paths in a BDD?

II. Does the minimum size BDD have the minimum number of paths?

The first question remains an open problem

After numerous experiments, we concluded that the minimum size BDD does not necessarily have the minimum number of paths

Experimental ResultsExperimental Results

Number of Backtracks Comparison

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0.5

11 4 7 10 13 16 19

Millio

ns

Function

TEGUS

Proposed

Optimal

Average 90% reduction in the backtracks for the 21 functions of the ISCAS’89 benchmark circuits

The optimal is determined by picking the minimal path BDD resulting from sifting

Experimental ResultsExperimental ResultsTime Comparison

0100200300400500600700800

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13

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19

Circuit

Tim

e (

sec)

TEGUS

Proposed

Average 70% time reduction for the hard-SAT functions (13) of the ISCAS’ 89 benchmark circuits

The multiplier c6288 number of paths does not significantly change for different variable orderings

Experiments carried out using a Pentime 233Mhz with 64 MB RAM

ConclusionsConclusions

The relation between the search tree of the DP procedure and the BDD of the corresponding circuit was studied

We established the relation between the number of paths in a BDD and the corresponding number of backtracks in the DP procedure, enabling the calculation of optimal lower bounds

This relation enabled the inclusion of a modified BDD variable ordering heuristic in the splitting choice of the DP procedure

Experimental results confirm the reported relation and demonstrate a dramatic decrease in the number of backtracks and time need to solve equivalence checking

On the Relation between SAT and BDDs for Equivalence Checking

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