NXP P80CL410, P83CL410 Data Sheet · 2004-11-03 · DIP40 DESCRIPTION VSO40 QFP44 P1.0/INT2 1 40...

DATA SHEET

Product specificationSupersedes data of 1995 Jan 20File under Integrated circuits, IC20

1997 Apr 10

INTEGRATED CIRCUITS

P80CL410; P83CL410Low voltage 8-bit microcontrollerswith I2C-bus

1997 Apr 10 2

Philips Semiconductors Product specification

Low voltage 8-bit microcontrollers withI2C-bus

P80CL410; P83CL410

CONTENTS

1 FEATURES

2 GENERAL DESCRIPTION

2.1 ROMless version: P80CL410

3 APPLICATIONS

4 ORDERING INFORMATION

5 BLOCK DIAGRAM

6 FUNCTIONAL DIAGRAM

7 PINNING INFORMATION

7.1 Pinning7.2 Pin description

8 FUNCTIONAL DESCRIPTION OVERVIEW

8.1 General8.2 CPU timing

9 MEMORY ORGANIZATION

9.1 Program Memory9.2 Data Memory9.3 Special Function Registers (SFRs)9.4 Addressing

10 I/O FACILITIES

10.1 Ports10.2 Port options10.3 Port 0 options10.3.1 External memory accesses10.3.2 I/O Accesses10.4 SET/RESET options

11 TIMERS/EVENT COUNTERS

12 REDUCED POWER MODES

12.1 Idle mode12.2 Power-down mode12.3 Wake-up from Power-down mode12.3.1 Wake-up using INT2 to INT912.3.2 Wake-up using RST12.4 Power Control Register (PCON)12.5 Status of external pins

13 I2C-BUS SERIAL I/O

13.1 Serial Control Register (S1CON)13.2 Serial Status Register (S1STA)13.3 Data Shift Register (S1DAT)13.4 Address Register (S1ADR)

14 INTERRUPT SYSTEM

14.1 External interrupts INT2 to INT914.2 Interrupt priority14.3 Interrupt registers14.3.1 Interrupt Enable Register (IEN0)

14.3.2 Interrupt Enable Register (IEN1)14.3.3 Interrupt Priority Register (IP0)14.3.4 Interrupt Priority Register (IP1)14.3.5 Interrupt Polarity Register (IX1)14.3.6 Interrupt Request Flag Register (IRQ1)

15 OSCILLATOR CIRCUITRY

16 RESET

16.1 External reset using the RST pin16.2 Power-on-reset

17 SPECIAL FUNCTION REGISTERSOVERVIEW

18 INSTRUCTION SET

19 LIMITING VALUES

20 DC CHARACTERISTICS

21 AC CHARACTERISTICS

22 P85CL000HFZ ‘PIGGY-BACK’SPECIFICATION

22.1 General description22.2 Feature differences/additional features of

P85CL000HFZ with respect to P83CL41022.3 Common specification/feature differences

between P85CL000HFZ andP83CL410/P80CL51

23 PACKAGE OUTLINES

24 SOLDERING

24.1 Introduction24.2 DIP24.2.1 Soldering by dipping or by wave24.2.2 Repairing soldered joints24.3 QFP24.3.1 Reflow soldering24.3.2 Wave soldering24.3.3 Repairing soldered joints24.4 Reflow soldering24.5 Wave soldering24.6 Repairing soldered joints

25 DEFINITIONS

26 LIFE SUPPORT APPLICATIONS

27 PURCHASE OF PHILIPS I2C COMPONENTS

1997 Apr 10 3



P80CL410; P83CL410

1 FEATURES

· Full static 80C51 Central Processing Unit

· 8-bit CPU, ROM, RAM, I/O in a 40-lead DIP,40-lead VSO or 44-lead QFP package

· 128 bytes on-chip RAM Data Memory

· 4 kbytes on-chip ROM Program Memory for P83CL410

· External memory expandable up to 128 kbytes: RAM upto 64 kbytes and ROM up to 64 kbytes

· Four 8-bit ports; 32 I/O lines

· Two 16-bit Timer/Event counters

· On-chip oscillator suitable for RC, LC, quartz crystal orceramic resonator

· Thirteen source, thirteen vector, nested interruptstructure with two priority levels

· I2C-bus interface for serial transfer on two lines

· Enhanced architecture with:

– non-page oriented instructions

– direct addressing

– four 8-byte RAM register banks

– stack depth limited only by available internal RAM(maximum 128 bytes)

– multiply, divide, subtract and compare instructions

· Reduced power consumption through Power-down andIdle modes

· Wake-up via external interrupts at Port 1

· Frequency range: DC to 12 MHz

· Supply voltage: 1.8 to 6.0 V

· Very low current consumption

· Operating ambient temperature range: - 40 to +85 °C.

2 GENERAL DESCRIPTION

The P80CL410; P83CL410 (hereafter generally referred toas the P8xCL410) is manufactured in an advanced CMOStechnology that allows the device to operate at voltagesdown to 1.8 V and at frequencies down to DC.The P8xCL410 has the same instruction set as the 80C51.

The P8xCL410 features 4 kbyte ROM (83CL410),128 bytes RAM (both ROM and RAM are externallyexpandable to 64 kbytes), four 8-bit ports, two 16-bittimer/counter, an I2C serial interface, a thirteen source twopriority level nested interrupt structure, and on-chiposcillator circuitry suitable for quartz crystal, ceramicresonator, RC, or LC. The device operates over a widerange of supply voltages and has low power consumption.

The 8xCL410 has two reduced power modes that are thesame as those on the standard 80C51.

The special reduced power feature of this device is that itcan be stopped and then restarted. Running from anexternal clock source, the clock can be stopped and aftera period of time restarted. The 8xCL410 will resumeoperation from where it was when the code stopped withno loss of internal state, RAM contents, or SpecialFunction Register contents.If the internal oscillator is used the device cannot bestopped and started, but the Power-down mode can beused to achieve similar power savings, without loss ofon-chip RAM and Special Function Register values.The Power-down mode can be terminated via an interrupt.

This data sheet details the specific properties of theP80CL410; P83CL410. For details of the 80C51 core see“Data Handbook IC20”.

For emulation purposes, the P85CL000 (piggy-backversion) with 256 bytes of RAM is recommended. Detailsare given in Chapter 22.

2.1 ROMless version: P80CL410

The P80CL410 is the ROMless version of the P83CL410.The mask options on the P80CL410 are fixed as follows:

· All ports have option ‘1S’ (standard port, HIGH afterreset), except ports P1.6 and P1.7 which have option‘2S’ (open-drain, HIGH after reset)

· Oscillator option: Oscillator 3

· Power-on-reset option: OFF.

3 APPLICATIONS

The P8xCL410 is an 8-bit general purpose microcontrollerespecially suited for battery-powered applications.The P8xCL410 also functions as an arithmetic processorhaving facilities for both binary and BCD arithmetic plusbit-handling capabilities.

1997 Apr 10 4



P80CL410; P83CL410

4 ORDERING INFORMATION

Note

1. Refer to the Order Entry Form (OEF) for this device for the full type number, including options/program.

5 BLOCK DIAGRAM

TYPE NUMBER(1) PACKAGE

ROMless ROM NAME DESCRIPTION VERSION

P80CL410HFP P83CL410HFP DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1

P80CL410HFT P83CL410HFT VSO40 plastic very small outline package; 40 leads SOT158-1

- P83CL410HFH QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);body 10 ´ 10 ´ 1.75 mm

SOT307-2

Fig.1 Block diagram.

(1) Pins shared with parallel port pins.

PROGRAMMABLE I/O64 kbyte BUS EXPANSION CONTROL

OSCILLATOR AND

TIMING

CPU

internal interrupts

PROGRAM MEMORY

(4K x 8 ROM)

DATA MEMORY

(128 x 8 RAM)

I2C-BUS SERIAL I/O

TWO 16-BIT TIMER/EVENT

COUNTERS

XTAL2 XTAL1

frequency reference

T0 T1

counter (1)

external interrupts (1) control parallel ports, address/data bus

and I/O pins

SDA SCL

MBK018

P80CL410 P83CL410

10 3

(1)

1997 Apr 10 5



P80CL410; P83CL410

6 FUNCTIONAL DIAGRAM

Fig.2 Functional diagram.

handbook, full pagewidth

port 0 address and data bus

address bus

port 1

port 2

VDDVSS RST

XTAL1

XTAL2

ALE

EA

PSEN

port 3T0

T1

INT0

INT1

WR

RD

alternative functions

P80CL410 P83CL410

MBK019

INT2

INT4

INT5

INT6

INT7

INT8/SCL

INT9/SDA

INT3

1997 Apr 10 6



P80CL410; P83CL410

7 PINNING INFORMATION

7.1 Pinning

Fig.3 Pin configuration for DIP40 and VSO40 packages.

handbook, halfpage

MBK017

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

21

22

23

24

25

26

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

P2.7/A15

P2.6/A14

P2.5/A13

EA

PSEN

P1.5/INT7

RST

P1.6/INT8/SCL

P1.7/INT9/SDA

P3.4/T0

P3.5/T1

P3.0

P3.1

P3.2/INT0

P3.3/INT1

ALE

P80CL410 P83CL410

XTAL2

XTAL1

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

V SS

P3.7/RD

P3.6/WR

V DD

P1.4/INT6

P1.3/INT5

P1.2/INT4

P1.1/INT3

P1.0/INT2

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

1997 Apr 10 7



P80CL410; P83CL410

Fig.4 Pin configuration for QFP44 package.


P83CL410HFH

MBK016

1P1.5/INT7

2

3

4

5

6

7

8

9

10

11

33

32

31

30

29

28

27

26

25

24

23

12 13 14 15 16 17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 34

P1.6/INT8/SCL

P1.7/INT9/SDA

RST

P3.0

n.c.

P3.1

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.

6/W

R

P3.

7/R

D

XT

AL2

XT

AL1 n.c.

P2.

0/A

8

P2.

1/A

9

P2.

2/A

10

P2.

3/A

11

P2.

4/A

12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE

EA

n.c.

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.

3/A

D3

P0.

2/A

D2

P0.

1/A

D1

P0.

0/A

D0

VD

D

n.c.

P1.

0/IN

T2

P1.

1/IN

T3

P1.

2/IN

T4

P1.

3/IN

T5

P1.

4/IN

T6

VS

S

1997 Apr 10 8



P80CL410; P83CL410

7.2 Pin description

Table 1 Pin description for DIP40 (SOT190-1), VSO40 (SOT319-2) and QFP44 (SOT307-2) packagesFor more extensive description of the port pins see Chapter 10 “I/O facilities”.

SYMBOL

PIN

DESCRIPTIONDIP40VSO40

QFP44

P1.0/INT2 1 40 · Port 1 : 8-bit bidirectional I/O port (P1.0 to P1.7). Port pins that havelogic 1s written to them are pulled HIGH by internal pull-ups, and in thisstate can be used as inputs. As inputs, Port 1 pins that are externallypulled LOW will source current (IIL, see Chapter 20) due to the internalpull-ups. Port 1 output buffers can sink/source 4 LS TTL loads.

· Alternative functions:

– INT2 to INT9 are external interrupt inputs

– SCL and SDA are the I2C-bus clock and data lines.

P1.1/INT3 2 41

P1.2/INT4 3 42

P1.3/INT5 4 43

P1.4/INT6 5 44

P1.5/INT7 6 1

P1.6/INT8/SCL 7 2

P1.7/INT9/SDA 8 3

RST 9 4 Reset : a HIGH level on this pin for two machine cycles while the oscillatoris running resets the device.

P3.0 10 5 · Port 3: 8-bit bidirectional I/O port (P3.0 to P3.7).Same characteristics as Port 1.

· Alternative functions:

– INT0 and INT1 are external interrupts 0 and 1

– T0 and T1 are external inputs for timers 0 and 1

– WR is the external Data Memory write strobe

– RD is the external Data Memory read strobe.

P3.1 11 7

P3.2/INT0 12 8

P3.3/INT1 13 9

P3.4/T0 14 10

P3.5/T1 15 11

P3.6/WR 16 12

P3.7/RD 17 13

XTAL2 18 14 Crystal oscillator output : output of the inverting amplifier of the oscillator.Left open when external clock is used.

XTAL1 19 15 Crystal oscillator input : input to the inverting amplifier of the oscillator,also the input for an externally generated clock source.

VSS 20 16 Ground: circuit ground potential.

P2.0 to P2.7A8 to A15

21 to 28 18 to 25 · Port 2 : 8-bit bidirectional I/O port (P2.0 to P2.7) with internal pull-ups.Same characteristics as Port 1.

· High-order addressing : Port 2 emits the high-order address byte(A8 to A15) during accesses to external memory that use 16-bitaddresses (MOVX @DPTR). In this application it uses the strong internalpull-ups when emitting logic 1s. During accesses to external memory thatuse 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2Special Function Register.

PSEN 29 26 Program Store Enable . Output read strobe to external Program Memory.When executing code out of external Program Memory, PSEN is activatedtwice each machine cycle. However, during each access to external DataMemory two PSEN activations are skipped.

1997 Apr 10 9



P80CL410; P83CL410

ALE 30 27 Address Latch Enable . Output pulse for latching the low byte of theaddress during access to external memory. ALE is emitted at a constantrate of 1 ¤ 6 ´ fosc, and may be used for external timing or clocking purposes(assuming MOVX instructions are not used).

EA 31 29 External Access . When EA is held HIGH the CPU executes out of internalprogram memory (unless the program counter exceeds 0FFFH). HoldingEA LOW forces the CPU to execute out of external memory regardless ofthe value of the program counter.

P0.0 to P0.7AD0 to AD7

39 to 32 30 to 37 · Port 0 : 8-bit open-drain bidirectional I/O port. As an open-drain outputport it can sink 8 LS TTL loads. Port 0 pins that have logic 1s written tothem float, and in that state will function as high impedance inputs.

· Low-order addressing : Port 0 is also the multiplexed low-order addressand data bus during access to external memory. The strong internalpull-ups are used while emitting logic 1s within the low order address.

VDD 40 38 Power supply.

n.c. - 6, 17, 28and 39

Not connected.

SYMBOL

PIN

DESCRIPTIONDIP40VSO40

QFP44

1997 Apr 10 10



P80CL410; P83CL410

8 FUNCTIONAL DESCRIPTION OVERVIEW

This chapter gives a brief overview of the device.The detailed functional description is in the followingchapters:

Chapter 9 “Memory organization”

Chapter 10 “I/O facilities”

Chapter 11 “Timers/event counters”

Chapter 12 “Reduced power modes”

Chapter 13 “I2C-bus serial I/O”

Chapter 14 “Interrupt system”

Chapter 15 “Oscillator circuitry”

Chapter 16 “Reset”.

8.1 General

The P8xCL410 is a stand-alone high-performance CMOSmicrocontroller designed for use in real-time applicationssuch as instrumentation, industrial control, intelligentcomputer peripherals and consumer products.

The device provides hardware features, architecturalenhancements and new instructions to function as acontroller for applications requiring up to 64 kbytes ofProgram Memory and/or up to 64 kbytes of Data Memory.

The P8xCL410 contains a 4 kbytes Program Memory(ROM; P83CL410); a static 128 bytes Data Memory(RAM); 32 I/O lines; two16-bit timer/event counters;a thirteen-source, two priority-level, nested interruptstructure and on-chip oscillator and timing circuit.An I2C-bus serial interface is also provided.

The device has two software-selectable modes of reducedactivity for power reduction:

· Idle mode ; freezes the CPU while allowing the timers,serial I/O and interrupt system to continue functioning.

· Power-down mode ; saves the RAM contents butfreezes the oscillator causing all other chip functions tobe inoperative.

8.2 CPU timing

A machine cycle consists of a sequence of 6 states. Eachstate lasts for two oscillator periods, thus a machine cycletakes 12 oscillator periods or 1 m s if the oscillatorfrequency (fosc) is 12 MHz.

9 MEMORY ORGANIZATION

The P8xCL410 has 4 kbytes of Program Memory (ROM;P83CL410 only) plus 128 bytes of Data Memory (RAM) onboard. The device has separate address spaces forProgram and Data Memory (see Fig.5). Using Port latchesP0 and P2, the P8xCL410 can address a maximum of64 kbytes of program memory and a maximum of64 kbytes of data memory. The CPU generates. The CPUgenerates both read (RD) and write (WR) signals forexternal Data Memory accesses, and the read strobe(PSEN) for external Program Memory.

9.1 Program Memory

After reset the CPU begins program execution at location0000H. The lower 4 kbytes of Program Memory can beimplemented in the on-chip ROM (P83CL410 only) or inexternal Program Memory.

If the EA pin is tied to VDD, then Program Memory fetchesfrom addresses 0000H to 0FFFH are directed to theinternal ROM. Fetches from addresses 1000H to FFFFHare directed to external ROM. Program Counter valuesgreater than 0FFFH are automatically addressed toexternal memory regardless of the state of the EA pin.

9.2 Data Memory

The P8xCL410 contains128 bytes of internal RAM and 27Special Function Registers (SFR). The memory map(Fig.5) shows the internal Data Memory space divided intothe lower 128, the upper 128, and the SFR space.The lower 128 bytes of the internal RAM are organized asmapped in Fig.6. The lowest 32 bytes are grouped into 4banks of 8 registers. Program instructions refer to theseregisters within a register bank as R0 through R7. Two bitsin the Program Status Word select which register bank isin use. The next 16 bytes above the register banks form ablock of bit-addressable memory space. The 128 bits inthis area can be directly addressed by the single-bitmanipulation instructions. The remaining registers(30H to 7FH) are directly and indirectly byte addressable.

1997 Apr 10 11



P80CL410; P83CL410

Fig.5 Memory map.


MLA559

INTERNAL DATA RAM

255

127

0

EXTERNAL

(EA = 0)

INTERNAL

(EA = 1)

INTERNAL DATA MEMORY EXTERNAL DATA MEMORY

PROGRAM MEMORY

EXTERNAL 64K

64K

4096

4095 OVERLAPPED SPACE

0

4095

SPECIAL FUNCTION

REGISTERS

1997 Apr 10 12



P80CL410; P83CL410

Fig.6 The lower 128 bytes of internal RAM.

handbook, halfpage

MLA560 - 1

R7

R0

07H

0

R7

R0

0FH

08H

R7

R0

17H

10H

R7

R0

1FH

18H

2FH

7FH

20H

30H

bit-addressable space (bit addresses 0 to 7F)

4 banks of 8 registers (R0 to R7)

9.3 Special Function Registers (SFRs)

The upper 128 bytes are the address locations of theSFRs. Figure 7 shows the SFR space. The SFRs includethe port latches, timers, peripheral control, serial I/Oregisters, etc. These registers can only be accessed bydirect addressing. There are 128 directly addressablelocations in the SFR address space (SFRs with addressesdivisible by eight).

9.4 Addressing

The P8xCL410 has five methods for addressing sourceoperands:

· Register

· Direct

· Register-indirect

· Immediate

· Base-register plus index-register-indirect.

The first three methods can be used for addressingdestination operands. Most instructions have a‘destination/source’ field that specifies the data type,addressing methods and operands involved.For operations other than MOVs, the destination operandis also a source operand.

Access to memory addressing is as follows:

· Registers in one of the four register banks throughregister, direct or register-indirect

· Internal RAM (128 bytes) through direct orregister-indirect

· Special Function Registers through direct

· External data memory through register-indirect

· Program Memory look-up tables through base-registerplus index-register-indirect.

1997 Apr 10 13



P80CL410; P83CL410

Fig.7 Special Function Register memory map.

MBK020

FEFF FD FC FB FA F9 F8

F6F7 F5 F4 F3 F2 F1 F0

EEEF ED EC EB EA E9 E8

E6E7 E5 E4 E3 E2 E1 E0

DEDF DD DC DB DA D9 D8

D6D7 D5 D4 D3 D2 D1 D0

C6C7 C5 C4 C3 C2 C1 C0

BIT ADDRESSREGISTER MNEMONIC

FFH

DIRECT BYTE

ADDRESS (HEX)

F8H

F0H

E8H

E0H

DBH

DAH

D9H

D8H

D0H

C0H

SFRs containing directly addressable

bits

IP1

B

IEN1

ACC

S1ADR

S1DAT

S1STA

S1CON

PSW

IRQ1

IX1 E9H

BE BD BC BB BA B9 B8

B6B7 B5 B4 B3 B2 B1 B0

AEAF AD AC AB AA A9 A8

A6A7 A5 A4 A3 A2 A1 A0

9697 95 94 93 92 91 90

8E8F 8D 8C 8B 8A 89 88

8687 85 84 83 82 81 80

B8H

B0H

A8H

A0H

90H

8DH

8CH

8BH

8AH

89H

88H

87H

83H

82H

81H

80H

IP0

P3

P2

P1

TH1

TH0

TL1

TL0

TMOD

PCON

DPH

DPL

SP

P0

IEN0

TCON

1997 Apr 10 14



P80CL410; P83CL410

10 I/O FACILITIES

10.1 Ports

The P8xCL410 has 32 I/O lines treated as 32 individuallyaddressable bits or as four parallel 8-bit addressable ports.Ports 0, 1, 2 and 3 perform the alternative functionsdetailed below. To enable a port pin alternate function, theport bit latch in its SFR must contain a logic 1.

Port 0 Provides the multiplexed low-order address anddata bus for expanding the device with standardmemories and peripherals.

Port 1 Used for the external interrupts INT2 to INT9, andthe I2C-bus interface lines SCL and SDA.

Port 2 Provides the high-order address when expandingthe device with external Program or Data Memory.

Port 3 Pins can be configured individually to provide:

· External interrupt request inputs: INT1 and INT0

· Timer/counter inputs: T1 and T0

· Control signals to read and write to externalmemories: RD and WR.

Each port consists of a latch (SFRs P0 to P3), an outputdriver and input buffer. Ports 1, 2, and 3 have internalpull-ups Figure 8(a) shows that the strong transistor ‘p1’ isturned on for only 2 oscillator periods after a LOW-to-HIGHtransition in the port latch. When on, it turns on ‘p3’ (a weakpull-up) through the inverter. This inverter and ‘p3’ form alatch which holds the logic 1. In Port 0 the pull-up ‘p1’ isonly on when emitting logic 1s for external memoryaccess. Writing a logic 1 to a Port 0 bit latch leaves bothoutput transistors switched off so that the pin can be usedas a high-impedance input.

10.2 Port options

The pins of port 1 (except P1.6 and P1.7; with option 2Sonly), port 2 and port 3 may be individually configured withone of the following options. These options are also shownin Fig.8.

Option 1 Standard Port ; quasi-bidirectional I/O withpull-up. The strong booster pull-up ‘p1’ is turnedon for two oscillator periods after aLOW-to-HIGH transition in the port latch;Fig.8(a).

Option 2 Open-drain ; quasi-bidirectional I/O withn-channel open-drain output. Use as an outputrequires the connection of an external pull-upresistor; see Fig.8(b).

Option 3 Push-pull ; output with drive capability in bothpolarities. Under this option, pins can only beused as outputs; see Fig.8(c).

10.3 Port 0 options

The definition of port options for Port 0 is slightly different.Two cases are considered. First, access to externalmemory (EA = 0 or access above the built-in memoryboundary) and second, I/O accesses.

10.3.1 EXTERNAL MEMORY ACCESSES

Option 1 True logic 0 and logic 1 are written as address tothe external memory (strong pull-up to be used).

Option 2 An external pull-up resistor is required forexternal accesses.

Option 3 Not allowed for external memory accesses asthe port can only be used as output.

10.3.2 I/O ACCESSES

Option 1 When writing a logic 1 to the port latch, thestrong pull-up ‘p1’ will be on for 2 oscillatorperiods. No weak pull-up exists. Without anexternal pull-up, this option can be used as ahigh-impedance input.

Option 2 Open-drain; quasi-directional I/O with n-channelopen-drain output. Use as an output requires theconnection of an external pull-up resistor.See Fig.8(b).

Option 3 Push-Pull; output with drive capability in bothpolarities. Under this option pins can only beused as outputs. See Fig.8(c).

10.4 SET/RESET options

Individual mask selection of the post-reset state isavailable with any of the above pins. The requiredselection is made by appending ‘S’ or ‘R’ to Options 1, 2,or 3 above.

Option R RESET, at reset this pin will be initialized LOW.

Option S SET, at reset this pin will be initialized HIGH.

1997 Apr 10 15



P80CL410; P83CL410

Fig.8 Port configuration options.


MGD677

p1

n

strong pull-up

+5 V

Q from port latch

(c) Push-pull

p1

p2

p3

input data

read port pin

2 oscillator periods

n

strong pull-up

I/O pin

+5 V

Q from port latch

INPUT BUFFER

(a) Standard

I/O pin

n

+5 V

Q from port latch

input data

read port pin

INPUT BUFFER

(b) Open-drain

external pull-up

I/O pin

1997 Apr 10 16



P80CL410; P83CL410

11 TIMERS/EVENT COUNTERS

The P8xCL410 contains two16-bit timer/event counterregisters; Timer 0 and Timer 1, which can perform thefollowing functions:

· Measure time intervals and pulse durations

· Count events

· Generate interrupt requests.

In the ‘Timer’ operating mode the register is incrementedevery machine cycle. Since a machine cycle consists of 12oscillator periods, the count rate is 1 ¤ 12 ´ fosc.

In the ‘Counter’ operating mode, the register isincremented in response to a HIGH-to-LOW transition.Since it takes 2 machine cycles (24 oscillator periods) torecognize a HIGH-to-LOW transition, the maximum countrate is 1 ¤ 24 ´ fosc. To ensure a given level is sampled, itshould be held for at least one complete machine cycle.

Timer 0 and Timer 1 can be programmed independently tooperate in four modes:

Mode 0 8-bit timer or 8-bit counter each with divide-by-32prescaler.

Mode 1 16-bit time-interval or event counter.

Mode 2 8-bit time-interval or event counter with automaticreload upon overflow.

Mode 3 Timer 0 establishes TL0 and TH0 as twoseparate counters.

12 REDUCED POWER MODES

There are two software selectable modes of reducedactivity for further power reduction: Idle and Power-down.

12.1 Idle mode

Idle mode operation permits the external interrupts,I2C-bus, and timer blocks to continue to function while theclock to the CPU is halted.

Idle mode is entered by setting the IDL bit in the PowerControl Register (PCON.0, see Table 3). The instructionthat sets IDL is the last instruction executed in the normaloperating mode before the Idle mode is activated

Once in Idle mode, the CPU status is preserved along withthe Stack Pointer, Program Counter, Program StatusWord and Accumulator. The RAM and all other registersmaintain their data during Idle mode. The status of theexternal pins during Idle mode is shown in Table 4.

The following functions remain active during the Idlemode:

· Timer 0 and Timer 1

· I2C-bus

· External interrupt.

These functions may generate an interrupt or reset; thusending the Idle mode.

There are two ways to terminate the Idle mode:

1. Activation of any enabled interrupt will cause IDL(PCON.0) to be cleared by hardware thus terminatingthe Idle mode. The interrupt is serviced, and followingthe RETI instruction, the next instruction to beexecuted will be the one following the instruction thatput the device in the Idle mode. The flag bits GF0(PCON.2) and GF1 (PCON.3) may be used todetermine whether the interrupt was received duringnormal execution or during the Idle mode.For example, the instruction that writes to PCON.0 canalso set or clear one or both flag bits. When the Idlemode is terminated by an interrupt, the service routinecan examine the status of the flag bits.

2. The second way of terminating the Idle mode is with anexternal hardware reset. Since the oscillator is stillrunning, the hardware reset is required to be active fortwo machine cycles (24 oscillator periods) to completethe reset operation. Reset redefines all SFRs but doesnot affect the on-chip RAM.

12.2 Power-down mode

Operation in Power-down mode freezes the oscillator.The internal connections which link both Idle andPower-down signals to the clock generation circuit areshown in Fig.9.

Power-down mode is entered by setting the PD bit in thePower Control Register (PCON.1, see Table 2).The instruction that sets PD is the last executed prior togoing into the Power-down mode.

Once in the Power-down mode, the oscillator is stopped.The contents of the on-chip RAM and the SFRs arepreserved. The port pins output the value held by theirrespective SFRs. ALE and PSEN are held LOW.

In the Power-down mode, VDD may be reduced tominimize circuit power consumption. The supply voltagemust not be reduced until the Power-down mode isentered, and must be restored before the hardware resetis applied which will free the oscillator. Reset should not bereleased until the oscillator has restarted and stabilized.

1997 Apr 10 17



P80CL410; P83CL410

12.3 Wake-up from Power-down mode

When in Power-down mode the controller can bewoken-up with either the external interrupts INT2 to INT9,or a reset operation. The wake-up operation has two basicapproaches as explained in Section 12.3.1; 12.3.2 andillustrated in Fig.10.

12.3.1 WAKE-UP USING INT2 TO INT9

If any of the interrupts INT2 to INT9 are enabled, thedevice can be woken-up from the Power-down mode withthe external interrupts. To ensure that the oscillator isstable before the controller restarts, the internal clock willremain inactive for 1536 oscillator periods. This iscontrolled by an on-chip delay counter.

12.3.2 WAKE-UP USING RST

To wake-up the P8xCL410, the RST pin must be keptHIGH for a minimum of 24 periods. The on-chip delaycounter is inactive. The user must ensure that the oscillatoris stable before any operation is attempted.

12.4 Power Control Register (PCON)

See Tables 2 and 3. Idle and Power-down modes areactivated by software using this SFR. PCON is notbit-addressable.

12.5 Status of external pins

The status of the external pins during Idle and Power-downmode is shown in Table 3. If the Power-down mode isactivated whilst accessing external Program Memory, theport data that is held in the Special Function Register P2 isrestored to Port 2.

If the data is a logic 1, the port pin is held HIGH during thePower-down mode by the strong pull-up transistor ‘p1’;see Fig.8(a).

Table 2 Power Control Register (address 87H)

Table 3 Description of PCON bits

Table 4 Status of external pins during Idle and Power-down modes

7 6 5 4 3 2 1 0

- - - - GF1 GF0 PD IDL

BIT SYMBOL DESCRIPTION

7, 6, 5, 4 - reserved

3 and 2 GF1 and GF0 General purpose flag bits

1 PD Power-down bit; setting this bit activates the Power-down mode

0 IDL Idle mode bit; setting this bit activates the Idle mode

MODE MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 PORT 4

Idle internal 1 1 port data port data port data port data port data

external 1 1 floating port data address port data port data

Power-down internal 0 0 port data port data port data port data port data

external 0 0 floating port data port data port data port data

1997 Apr 10 18



P80CL410; P83CL410

Fig.9 Internal clock control in Idle and Power-down mode.

dbook, full pagewidth

MLA563

OSCILLATOR

CLOCK GENERATOR

interrupts serial ports timer blocks

CPU

IDLPD

XTAL1XTAL2

Fig.10 Wake-up operation.


MGD679

delay counter 1536 periods

24 periods

power-down

RST pin

external interrupt

oscillator

1997 Apr 10 19



P80CL410; P83CL410

13 I2C-BUS SERIAL I/O

The serial port supports the twin line I2C-bus, whichconsists of a serial data line (SDA) and a serial clock line(SCL). These lines also function as the I/O port lines P1.7and P1.6 respectively.

The system is unique because data transport, clockgeneration, address recognition and bus control arbitrationare all controlled by hardware.

The I2C-bus serial I/O has complete autonomy in bytehandling and operates in 4 modes:

· Master transmitter

· Master receiver

· Slave transmitter

· Slave receiver.

These functions are controlled by the Serial ControlRegister S1CON. S1STA is the Status Register whosecontents may also be used as a vector to various serviceroutines. S1DAT is the Data Shift Register and S1ADR isthe Slave Address Register. Slave address recognition isperformed by on-chip hardware.

Figure 11 is the block diagram of the I2C-bus serial I/O.

Fig.11 Block diagram of I2C-bus serial I/O.

MLB199

SLAVE ADDRESS

S1ADR

GC

SHIFT REGISTER

S1DAT

SDA

ARBITRATION SYNC LOGIC

SCL BUS CLOCK GENERATOR

S1STA

INT

ER

NA

L B

US

7 0

S1CON

7 0

7 0

7 0

CONTROL REGISTER

STATUS REGISTER

1997 Apr 10 20



P80CL410; P83CL410

13.1 Serial Control Register (S1CON)

Table 5 Serial Control Register (SFR address D8H)

Table 6 Description of S1CON bits

7 6 5 4 3 2 1 0

CR2 ENS1 STA STO SI AA CR1 CR0


7 CR2 This bit along with bits CR1 (S1CON.1) and CR0 (S1CON.0) determines the serial clockfrequency when SIO is in the Master mode. See Table 7.

6 ENS1 ENABLE serial I/O . When ENS1 = 0, the serial I/O is disabled. SDA and SCL outputsare in the high impedance state; P1.6 and P1.7 function as open-drain ports. WhenENS1 = 1, the serial I/O is enabled. Output port latches P1.6 and P1.7 must be set tologic 1.

5 STA START flag . When this bit is set in Slave mode, the SIO hardware checks the status ofthe I2C-bus and generates a START condition if the bus is free or after the bus becomesfree. If STA is set while the SIO is in Master mode, SIO will generate a repeated STARTcondition.

4 STO STOP flag . With this bit set while in Master mode a STOP condition is generated. Whena STOP condition is detected on the I2C-bus, the SIO hardware clears the STO flag.STO may also be set in Slave mode in order to recover from an error condition. In thiscase no STOP condition is transmitted to the I2C-bus. However, the SIO hardwarebehaves as if a STOP condition has been received and releases the SDA and SCL.The SIO then switches to the not addressed slave receiver mode. The STOP flag iscleared by the hardware.

3 SI SIO interrupt flag . This flag is set, and an interrupt is generated, after any of thefollowing events occur:

· A START condition is generated in Master mode

· Own slave address has been received during AA = 1

· The general call address has been received while GC (S1ADR.0) = 1 and AA = 1

· A data byte has been received or transmitted in Master mode (even if arbitration is lost)

· A data byte has been received or transmitted as selected slave

· A STOP or START condition is received as selected slave receiver or transmitter.

2 AA Assert Acknowledge . When this bit is set, an acknowledge (low level to SDA) isreturned during the acknowledge clock pulse on the SCL line when:

· Own slave address is received

· General call address is received; GC (S1ADR.0) = 1

· A data byte is received while the device is programmed to be a Master Receiver

· A data byte is received while the device is a selected Slave Receiver.

When this bit is reset, no acknowledge is returned. Consequently, no interrupt isrequested when the own slave address or general call address is received.

1 CR1 These two bits along with the CR2 (S1CON.7) bit determine the serial clock frequencywhen SIO is in the Master mode. See Table 7.0 CR0

1997 Apr 10 21



P80CL410; P83CL410

Table 7 Selection of the serial clock frequency SCL in a Master mode of operation

13.2 Serial Status Register (S1STA)

S1STA is a read-only register. The contents of this register may be used as a vector to a service routine. This optimizesthe response time of the software and consequently that of the I2C-bus. The status codes for all possible modes of theI2C-bus interface are given in Tables 10 to 14.

Table 8 Serial Status Register (address D9H)

Table 9 Description of S1STA bits

Table 10 MST/TRX mode

CR2 CR1 CR0 fosc DIVISORBIT RATE (kHz) at f osc

3.58 MHz 6 MHz 12 MHz

0 0 0 256 14.0 23.4 46.9

0 0 1 224 16.0 26.8 53.6

0 1 0 192 18.6 31.3 62.5

0 1 1 160 22.4 37.5 75.0

1 0 0 960 3.73 6.25 12.5

1 0 1 120 29.8 50.0 100.0

1 1 0 60 59.7 100.0 -1 1 1 not allowed - - -

7 6 5 4 3 2 1 0

SC4 SC3 SC2 SC1 SC0 0 0 0


3 to 7 SC4 to SC0 5-bit status code

0 to 2 - these three bits are always zero

S1STA VALUE DESCRIPTION

08H a START condition has been transmitted

10H a repeated START condition has been transmitted

18H SLA and W have been transmitted, ACK has been received

20H SLA and W have been transmitted, ACK received

28H DATA of S1DAT has been transmitted, ACK received

30H DATA of S1DAT has been transmitted, ACK received

38H arbitration lost in SLA, R/W or DATA

1997 Apr 10 22



P80CL410; P83CL410

Table 11 MST/REC mode

Table 12 SLV/REC mode

Table 13 SLV/TRX mode

Table 14 Miscellaneous


08H a START condition has been transmitted

10H a repeated START condition has been transmitted

38H arbitration lost while returning ACK

40H SLA and R have been transmitted, ACK received

48H SLA and R have been transmitted, ACK received

50H DATA has been received, ACK returned

58H DATA has been received, ACK returned


60H own SLA and W have been received, ACK returned

68H arbitration lost in SLA, R/W as MST. Own SLA and W have been received, ACK returned

70H general CALL has been received, ACK returned

78H arbitration lost in SLA, R/W as MST; general CALL has been received

80H previously addressed with own SLA; DATA byte received, ACK returned

88H previously addressed with own SLA; DATA byte received, ACK returned

90H previously addressed with general CALL; DATA byte has been received, ACK has been returned

98H previously addressed with general CALL; DATA byte has been received, ACK has been returned

A0H a STOP condition or repeated START condition has been received while still addressed as SLV/RECor SLV/TRX


A8H own SLA and R have been received, ACK returned

B0H arbitration lost in SLA, R/W as MST; own SLA and R have been received, ACK returned

B8H DATA byte has been transmitted, ACK received

C0H DATA byte has been transmitted, ACK received

C8H last DATA byte has been transmitted (AA = 0), ACK received


00H bus error during MST mode or selected SLV mode, due to an erroneous START or STOP condition

F8H no relevant state information available, SI = 0

1997 Apr 10 23



P80CL410; P83CL410

Table 15 Symbols used in Tables 10 to 14

13.3 Data Shift Register (S1DAT)

S1DAT contains the serial data to be transmitted or data which has just been received. The MSB (bit 7) is transmitted orreceived first; i.e. data shifted from right to left.

Table 16 Data Shift Register (SFR address DAH)

13.4 Address Register (S1ADR)

This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed asa slave receiver/transmitter.

Table 17 Address Register (SFR address DBH)

Table 18 Description of S1ADR bits

SYMBOL DESCRIPTION

SLA 7-bit slave address

R read bit

W write bit

ACK acknowledgement (acknowledge bit is logic 0)

ACK no acknowledgement (acknowledge bit is logic 1)

DATA 8-bit data byte to or from I2C-bus

MST master

SLV slave

TRX transmitter

REC receiver

7 6 5 4 3 2 1 0

S1DAT.7 S1DAT.6 S1DAT.5 S1DAT.4 S1DAT.3 S1DAT.2 S1DAT.1 S1DAT.0

7 6 5 4 3 2 1 0

SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0 GC


7 to 1 SLA6 to SLA0 own slave address

0 GC this bit is used to determine whether the general call address is recognized; whenGC = 0, the general call address is not recognized; when GC = 1, the general calladdress is recognized

1997 Apr 10 24



P80CL410; P83CL410

14 INTERRUPT SYSTEM

External events and the real-time-driven on-chipperipherals require service by the CPU at unpredictabletimes. To tie the asynchronous activities of these functionsto normal program execution a multiple-source,two-priority-level, nested interrupt system is provided.The system is shown in Fig.12. The P8xCL410acknowledges interrupt requests from thirteen sources asfollows:

· INT0 and INT1

· Timer 0 and Timer 1

· I2C-bus

· INT2 to INT9.

Each interrupt vectors to a separate location in ProgramMemory for its service routine. Each source can beindividually enabled or disabled by corresponding bits inthe Interrupt Enable Registers (IEN0 and IEN1).The priority level is selected via the Interrupt PriorityRegisters (IP0 and IP1). All enabled sources can beglobally disabled or enabled. Figure 12 shows the interruptsystem.

14.1 External interrupts INT2 to INT9

Port 1 lines serve an alternative purpose as eightadditional interrupts INT2 to INT9. When enabled, each ofthese lines may wake-up the device from the Power-downmode. Using the Interrupt Polarity Register (IX1), each pinmay be initialized to be either active HIGH or active LOW.IRQ1 is the Interrupt Request Flag Register. If the interruptis enabled, each flag will be set on an interrupt request butmust be cleared by software, i.e. via the interrupt softwareor when the interrupt is disabled.

Port 1 interrupts are level sensitive. A Port 1 interrupt willbe recognized when a level (HIGH or LOW depending onthe Interrupt Polarity Register) on P1.n is held active for atleast one machine cycle. The interrupt request is notserviced until the next machine cycle. Figure 13 shows theexternal interrupt configuration.

14.2 Interrupt priority

Each interrupt source can be set to either a high priority orto a low priority. If a low priority interrupt is receivedsimultaneously with a high priority interrupt, the highpriority interrupt will be dealt with first.

If interrupts of the same priority are requestedsimultaneously, the processor will branch to the interruptpolled first, according to the sequence shown in Table 19and in Fig.12. The ‘vector address’ is the ROM locationwhere the appropriate interrupt service routine starts.

Table 19 Interrupt vector polling sequence

A low priority interrupt routine can only be interrupted by ahigh priority interrupt. A high priority interrupt routinecannot be interrupted.

SYMBOLVECTOR

ADDRESS (HEX)SOURCE

X0 (first) 0003 External 0

S1 002B I2C port

X5 0053 External 5

T0 000B Timer 0

X6 005B External 6

X1 0013 External 1

X2 003B External 2

X7 0063 External 7

T1 001B Timer 1

X3 0043 External 3

X8 006B External 8

X4 004B External 4

X9 (last) xt0073 External 9

1997 Apr 10 25



P80CL410; P83CL410

Fig.12 Interrupt system.

handbook, full pagewidth INTERRUPT SOURCES REGISTERS

PRIORITY

GLOBAL ENABLE

X0

S1

X5

T0

X6

X1

X2

X7

T1

X3

X8

X4

X9

IEN0/1 IP0/1

HIGH

LOW

INT

ER

RU

PT

PO

LLIN

G S

EQ

UE

NC

E

MBK022

1997 Apr 10 26



P80CL410; P83CL410

14.3 Interrupt registers

The registers used in the interrupt system are listed in Table 20. Tables 21 to 32 describe the contents of these registers.

Table 20 Special Function Registers related to the interrupt system

ADDRESS REGISTER DESCRIPTION

A8H IEN0 Interrupt Enable Register

E8H IEN1 Interrupt Enable Register (INT2 to INT9)

B8H IP0 Interrupt Priority Register

F8H IP1 Interrupt Priority Register (INT2 to INT9)

E9H IX1 Interrupt Polarity Register

C0H IRQ1 Interrupt Request Flag Register

Fig.13 External interrupt configuration.


MLA575

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

X9

X8

X7

X6

X5

X4

X3

X2

IX1 IEN1 IRQ1

WAKE-UP

1997 Apr 10 27



P80CL410; P83CL410

14.3.1 INTERRUPT ENABLE REGISTER (IEN0)

Bit values: 0 = interrupt disabled; 1 = interrupt enabled.

Table 21 Interrupt Enable Register (SFR address A8H)

Table 22 Description of IEN0 bits

14.3.2 INTERRUPT ENABLE REGISTER (IEN1)

Bit values: 0 = interrupt disabled; 1 = interrupt enabled.

Table 23 Interrupt Enable Register (SFR address E8H)

Table 24 Description of IEN1 bits

7 6 5 4 3 2 1 0

EA - ES1 - ET1 EX1 ET0 EX0


7 EA general enable/disable control. If EA = 0, no interrupt is enabled. If EA = 1, anyindividually enabled interrupt will be accepted

6 - reserved

5 ES1 enable I2C-bus SIO interrupt

4 - reserved

3 ET1 enable Timer 1 interrupt (T1)

2 EX1 enable external interrupt 1

1 ET0 enable Timer 0 interrupt (T0)


7 6 5 4 3 2 1 0

EX9 EX8 EX7 EX6 EX5 EX4 EX3 EX2










1997 Apr 10 28



P80CL410; P83CL410

14.3.3 INTERRUPT PRIORITY REGISTER (IP0)

Bit values: 0 = low priority; 1 = high priority.

Table 25 Interrupt Priority Register (SFR address B8H)

Table 26 Description of IP0 bits

14.3.4 INTERRUPT PRIORITY REGISTER (IP1)

Bit values: 0 = low priority; 1 = high priority.

Table 27 Interrupt Priority Register (SFR address F8H)

Table 28 Description of IP1 bits

7 6 5 4 3 2 1 0

- - PS1 - PT1 PX1 PT0 PX0


7 - reserved

6 - reserved

5 PS1 I2C-bus SIO interrupt priority level

4 - reserved

3 PT1 Timer 1 interrupt priority level

2 PX1 external interrupt 1 priority level

1 PT0 Timer 0 interrupt priority level


7 6 5 4 3 2 1 0

PX9 PX8 PX7 PX6 PX5 PX4 PX3 PX2










1997 Apr 10 29



P80CL410; P83CL410

14.3.5 INTERRUPT POLARITY REGISTER (IX1)

Writing either a logic 1 or logic 0 to any Interrupt Polarity Register bit sets the polarity level of the corresponding externalinterrupt to an active HIGH or active LOW respectively.

Table 29 Interrupt Polarity Register (SFR address E9H)

Table 30 Description of IX1 bits

14.3.6 INTERRUPT REQUEST FLAG REGISTER (IRQ1)

Table 31 Interrupt Request Flag Register (SFR address C0H)

Table 32 Description of IRQ1 bits

7 6 5 4 3 2 1 0

IL9 IL8 IL7 IL6 IL5 IL4 IL3 IL2


7 IL9 external interrupt 9 polarity level








7 6 5 4 3 2 1 0

IQ9 IQ8 IQ7 IQ6 IQ5 IQ4 IQ3 IQ2


7 IQ9 external interrupt 9 request flag








1997 Apr 10 30



P80CL410; P83CL410

15 OSCILLATOR CIRCUITRY

The on-chip oscillator circuitry of the P8xCL410 is asingle-stage inverting amplifier biased by an internalfeedback resistor. The oscillator circuit is shown in Fig.15.For operation as a standard quartz oscillator, no externalcomponents are needed, except for the 32 kHz option.When using external capacitors, ceramic resonators, coilsand RC networks to drive the oscillator, five differentconfigurations are supported (see Table 33 and Fig.14).

In the Power-down mode the oscillator is stopped andXTAL1 is pulled HIGH. The oscillator inverter is switchedoff to ensure no current will flow regardless of the voltageat XTAL1, for configurations (a), (b), (c), (d), (e) and (g) ofFig.14.

To drive the device with an external clock source, apply theexternal clock signal to XTAL1, and leave XTAL2 to float,as shown in Fig.14(f). There are no requirements on theduty cycle of the external clock, since the input to theinternal clocking circuitry is buffered by a flip-flop.

Various oscillator options are provided for optimumon-chip oscillator performance; these are specified inTable 33 and shown in Fig.14. The required option shouldbe stated when ordering.

Table 33 Oscillator options

OPTION APPLICATION

Oscillator 1 for 32 kHz clock applications with external trimmer for frequency adjustment; a 4.7 MW bias resistoris needed for use in parallel with the crystal; see Fig.14(c)

Oscillator 2 low-power, low-frequency operations using LC components; see Fig.14(e)

Oscillator 3 medium frequency range applications

Oscillator 4 high frequency range applications

RC oscillator RC oscillator configuration; see Figs 14(g) and 16


MLA577

VDD

XTAL1 XTAL2

(d)

XTAL1 XTAL2

(e)

XTAL1 XTAL2

(f)

XTAL1 XTAL2

(g)

n.c. n.c.

XTAL1 XTAL2

(b)

XTAL1 XTAL2

(c)

XTAL1 XTAL2

(a)

STANDARD QUARTZ

OSCILLATOR

QUARTZ OSCILLATOR WITH EXTERNAL

CAPACITORS32 kHz

OSCILLATOR

CERAMIC RESONATOR LC - OSCILLATOR EXTERNAL CLOCK RC - OSCILLATOR

Fig.14 Oscillator configurations.

1997 Apr 10 31



P80CL410; P83CL410

Fig.15 Standard oscillator.


MBK025

VDD

P80CL410 P83CL410

VDD

RbiasC1i C2i

XTAL1 XTAL2

to internal timing circuits

VDD

PD

Fig.16 RC oscillator frequency as a function of RC.

handbook, halfpage

0

600

400

200

02 4 6

MLA579

RC ( m s)

(kHz)

fosc

RC oscillator frequency is externally adjustable; 100 kHz £ fosc £ 500 kHz.

1997 Apr 10 32



P80CL410; P83CL410

Table 34 Oscillator type selection guide

Note

1. 32 kHz quartz crystals with a series resistance >15 kW will reduce the guaranteed supply voltage range to2.5 to 3.5 V.

RESONATORFREQUENCY

(MHz)OPTION

(see Table 33)

C1 EXT. (pF) C2 EXT. (pF) RESONATOR MAX.SERIES RESISTANCEMIN. MAX. MIN. MAX.

Quartz 0.032 Oscillator 1 0 0 5 15 15 kW (1)

1.0

Oscillator 2

0 30 0 30 600 W3.58 0 15 0 15 100 W4.0 0 20 0 20 75 W6.0 Oscillator 3 0 10 0 10 60 W

10.0

Oscillator 4

0 15 0 15 60 W12.0 0 10 0 10 40W16.0 0 15 0 15 20 W

PXE 0.455

Oscillator 2

40 50 40 50 10 W1.0 15 50 15 50 100 W3.58 0 40 0 40 10 W4.0 0 40 0 40 10 W6.0 0 20 0 20 5 W

10.0 Oscillator 3 0 15 0 15 6 W12.0 Oscillator 4 10 40 10 40 6 W

LC - Oscillator 2 20 90 20 90 10 m H = 1 W

100 m H = 5 W

1 mH = 75 W

1997 Apr 10 33



P80CL410; P83CL410

Table 35 Oscillator equivalent circuit parametersThe equivalent circuit data of the internal oscillator compares with that of matched crystals.

SYMBOL PARAMETER OPTION CONDITION MIN. TYP. MAX. UNIT

gm transconductance Oscillator 1; 32 kHz Tamb = +25 °C;VDD = 4.5 V

- 15 - m S

Oscillator 2 200 600 1000 m S

Oscillator 3 400 1500 4000 m S

Oscillator 4 1000 4000 10000 m S

C1i input capacitance Oscillator 1; 32 kHz - 3.0 - pF

Oscillator 2 - 8.0 - pF



C2i output capacitance Oscillator 1; 32 kHz - 23 - pF




R2 output resistance Oscillator 1; 32 kHz - 3800 - kWOscillator 2 - 65 - kWOscillator 3 - 18 - kWOscillator 4 - 5.0 - kW

Fig.17 Oscillator equivalent circuit diagram.


MLA578

C1 i

R f

V1 gm C2 iR2

XTAL1 XTAL2

1997 Apr 10 34



P80CL410; P83CL410

16 RESET

To initialize the P8xCL410 a reset is performed by either ofthree methods:

· Applying an external signal to the RST pin

· Via Power-on-reset circuitry.

A reset leaves the internal registers as shown inChapter 17. The reset state of the port pins ismask-programmable and can be defined by the user.

16.1 External reset using the RST pin

The reset input for the P8xCL410 is RST. A Schmitt triggeris used at the input for noise rejection. The output of theSchmitt trigger is sampled by the reset circuitry everymachine cycle. A reset is accomplished by holding theRST pin HIGH for at least two machine cycles(24 oscillator periods) while the oscillator is running.The CPU responds by executing an internal reset. Portpins adopt their reset state immediately after the RST goesHIGH. During reset, ALE and PSEN are held HIGH.

The external reset is asynchronous to the internal clock.The RST pin is sampled during state 5, phase 2 of everymachine cycle. After a HIGH is detected at the RST pin, aninternal reset is repeated until RST goes LOW.The internal RAM is not affected by reset. When VDD isturned on, the RAM contents are indeterminate.

16.2 Power-on-reset

The device contains on-chip circuitry which switches theport pins to the customer defined logic level as soon asVDD exceeds 1.3 V; if the mask option ‘ON’ has beenchosen. As soon as the minimum supply voltage isreached, the oscillator will start up. However, to ensurethat the oscillator is stable before the controller starts, theclock signals are gated away from the CPU for a further1536 oscillator periods. During that time the CPU is held ina reset state. A hysteresis of approximately 50 mV at atypical power-on switching level of 1.3 V will ensurecorrect operation (see Fig.20).

The on-chip Power-on-reset circuitry can also be switchedoff via the mask option ‘OFF’. This option reduces thePower-down current to typically 800 nA and can bechosen if external reset circuitry is used. For applicationsnot requiring the internal reset, option ‘OFF’ should bechosen.

An automatic reset can be obtained by connecting the RSTpin to VDD via a 10 m F capacitor. At power-on, the voltageon the RST pin is equal to VDD minus the capacitor voltage,and decreases from VDD as the capacitor charges throughthe internal resistor (RRST) to ground. The larger thecapacitor, the more slowly VRST decreases. VRST mustremain above the lower threshold of the Schmitt triggerlong enough to effect a complete reset. The time requiredis the oscillator start-up time, plus 2 machine cycles.The Power-on-reset circuitry is shown in Fig.19.

Fig.18 Reset configuration.

handbook, halfpage

MLA580

SCHMITT TRIGGER

RESET CIRCUITRYRST

Fig.19 Recommended Power-on-reset circuitry.

handbook, halfpageVDD

VDD

RST

10 µF

R RST

MBK024

P80CL410 P83CL410

1997 Apr 10 35



P80CL410; P83CL410

Fig.20 Power-on-reset switching level.


MLA581

SUPPLY VOLTAGE

POWER-ON-RESET (INTERNAL)

OSCILLATOR

CPU RUNNING

Start-up time

1536 oscillator periods delay

hysteresis

switching level POR

1997 Apr 10 36



P80CL410; P83CL410

17 SPECIAL FUNCTION REGISTERS OVERVIEWThe P8xCL410 has 27 SFRs available to the user.

Notes

1. Bit addressable register.

2. Port reset state determined by the customer.

ADDRESS(HEX)

NAMERESET VALUE

(B)FUNCTION

F8 IP1(1) 00000000 Interrupt Priority Register INT2 to INT9)

F0 B(1) 00000000 B Register

E9 IX1 00000000 Interrupt Polarity Register

E8 IEN1(1) 00000000 Interrupt Enable Register 1

E0 ACC(1) 00000000 Accumulator

DB S1ADR 00000000 I2C-bus Slave Address Register

DA S1DAT 00000000 I2C-bus Data Shift Register

D9 S1STA 11111000 I2C-bus Serial Status Register

D8 S1CON(1) 00000000 I2C-bus Serial Control Register

D0 PSW(1) 00000000 Program Status Word

C0 IRQ1(1) 00000000 Interrupt Request Flag Register

B8 IP0(1) XX000000 Interrupt Priority Register 0

B0 P3(1) XXXXXXXX(2) Digital I/O Port Register 3

A8 IEN0(1) 00000000 Interrupt Enable Register

A0 P2(1) XXXXXXXX(2) Digital I/O Port Register 2

90 P1(1) XXXXXXXX(2) Digital I/O Port Register 1

8D TH1 00000000 Timer 1 High byte

8C TH0 00000000 Timer 0 High byte

8B TL1 00000000 Timer 1 Low byte

8A TL0 00000000 Timer 0 Low byte

89 TMOD 00000000 Timer 0 and 1 Mode Control Register

88 TCON(1) 00000000 Timer 0 and 1 Control/External Interrupt Control Register

87 PCON 0XXX0000 Power Control Register

83 DPH 00000000 Data Pointer High byte

82 DPL 00000000 Data Pointer Low byte

81 SP 00000111 Stack Pointer

80 P0(1) XXXXXXXX(2) Digital I/O Port Register 0

1997 Apr 10 37



P80CL410; P83CL410

18 INSTRUCTION SET

The P8xCL410 uses a powerful instruction set whichpermits the expansion of on-chip CPU peripherals andoptimizes byte efficiency and execution speed. Assignedopcodes add new high-power operation and permit newaddressing modes. The instruction set consists of

49 single-byte, 46 two-byte and 16 three-byte instructions.When using a 12 MHz oscillator, 64 instructions execute in1 m s and 45 instructions execute in 2 m s. Multiply anddivide instructions execute in 4 m s.

For the description of the Data Addressing modes andHexadecimal opcode cross-reference see Table 40.

Table 36 Instruction set description: Arithmetic operations

MNEMONIC DESCRIPTION BYTES CYCLESOPCODE

(HEX)

Arithmetic operations

ADD A,Rr add register to A 1 1 2*

ADD A,direct add direct byte to A 2 1 25

ADD A,@Ri add indirect RAM to A 1 1 26, 27

ADD A,#data add immediate data to A 2 1 24

ADDC A,Rr add register to A with carry flag 1 1 3*

ADDC A,direct add direct byte to A with carry flag 2 1 35

ADDC A,@Ri add indirect RAM to A with carry flag 1 1 36, 37

ADDC A,#data add immediate data to A with carry flag 2 1 34

SUBB A,Rr subtract register from A with borrow 1 1 9*

SUBB A,direct subtract direct byte from A with borrow 2 1 95

SUBB A,@Ri subtract indirect RAM from A with borrow 1 1 96, 97

SUBB A,#data subtract immediate data from A with borrow 2 1 94

INC A increment A 1 1 04

INC Rr increment register 1 1 0*

INC direct increment direct byte 2 1 05

INC @Ri increment indirect RAM 1 1 06, 07

DEC A decrement A 1 1 14

DEC Rr decrement register 1 1 1*

DEC direct decrement direct byte 2 1 15

DEC @Ri decrement indirect RAM 1 1 16, 17

INC DPTR increment data pointer 1 2 A3

MUL AB multiply A and B 1 4 A4

DIV AB divide A by B 1 4 84

DA A decimal adjust A 1 1 D4

1997 Apr 10 38



P80CL410; P83CL410

Table 37 Instruction set description: Logic operations


(HEX)

Logic operations

ANL A,Rr AND register to A 1 1 5*

ANL A,direct AND direct byte to A 2 1 55

ANL A,@Ri AND indirect RAM to A 1 1 56, 57

ANL A,#data AND immediate data to A 2 1 54

ANL direct,A AND A to direct byte 2 1 52

ANL direct,#data AND immediate data to direct byte 3 2 53

ORL A,Rr OR register to A 1 1 4*

ORL A,direct OR direct byte to A 2 1 45

ORL A,@Ri OR indirect RAM to A 1 1 46, 47

ORL A,#data OR immediate data to A 2 1 44

ORL direct,A OR A to direct byte 2 1 42

ORL direct,#data OR immediate data to direct byte 3 2 43

XRL A,Rr exclusive-OR register to A 1 1 6*

XRL A,direct exclusive-OR direct byte to A 2 1 65

XRL A,@Ri exclusive-OR indirect RAM to A 1 1 66, 67

XRL A,#data exclusive-OR immediate data to A 2 1 64

XRL direct,A exclusive-OR A to direct byte 2 1 62

XRL direct,#data exclusive-OR immediate data to direct byte 3 2 63

CLR A clear A 1 1 E4

CPL A complement A 1 1 F4

RL A rotate A left 1 1 23

RLC A rotate A left through the carry flag 1 1 33

RR A rotate A right 1 1 03

RRC A rotate A right through the carry flag 1 1 13

SWAP A swap nibbles within A 1 1 C4

1997 Apr 10 39



P80CL410; P83CL410

Table 38 Instruction set description: Data transfer

Note

1. MOV A,ACC is not permitted.


(HEX)

Data transfer

MOV A,Rr move register to A 1 1 E*

MOV A,direct (note 1) move direct byte to A 2 1 E5

MOV A,@Ri move indirect RAM to A 1 1 E6, E7

MOV A,#data move immediate data to A 2 1 74

MOV Rr,A move A to register 1 1 F*

MOV Rr,direct move direct byte to register 2 2 A*

MOV Rr,#data move immediate data to register 2 1 7*

MOV direct,A move A to direct byte 2 1 F5

MOV direct,Rr move register to direct byte 2 2 8*

MOV direct,direct move direct byte to direct 3 2 85

MOV direct,@Ri move indirect RAM to direct byte 2 2 86, 87

MOV direct,#data move immediate data to direct byte 3 2 75

MOV @Ri,A move A to indirect RAM 1 1 F6, F7

MOV @Ri,direct move direct byte to indirect RAM 2 2 A6, A7

MOV @Ri,#data move immediate data to indirect RAM 2 1 76, 77

MOV DPTR,#data 16 load data pointer with a 16-bit constant 3 2 90

MOVC A,@A+DPTR move code byte relative to DPTR to A 1 2 93

MOVC A,@A+PC move code byte relative to PC to A 1 2 83

MOVX A,@Ri move external RAM (8-bit address) to A 1 2 E2, E3

MOVX A,@DPTR move external RAM (16-bit address) to A 1 2 E0

MOVX @Ri,A move A to external RAM (8-bit address) 1 2 F2, F3

MOVX @DPTR,A move A to external RAM (16-bit address) 1 2 F0

PUSH direct push direct byte onto stack 2 2 C0

POP direct pop direct byte from stack 2 2 D0

XCH A,Rr exchange register with A 1 1 C*

XCH A,direct exchange direct byte with A 2 1 C5

XCH A,@Ri exchange indirect RAM with A 1 1 C6, C7

XCHD A,@Ri exchange LOW-order digit indirect RAM with A 1 1 D6, D7

1997 Apr 10 40



P80CL410; P83CL410

Table 39 Instruction set description: Boolean variable manipulation, Program and machine control


(HEX)

Boolean variable manipulation

CLR C clear carry flag 1 1 C3

CLR bit clear direct bit 2 1 C2

SETB C set carry flag 1 1 D3

SETB bit set direct bit 2 1 D2

CPL C complement carry flag 1 1 B3

CPL bit complement direct bit 2 1 B2

ANL C,bit AND direct bit to carry flag 2 2 82

ANL C,/bit AND complement of direct bit to carry flag 2 2 B0

ORL C,bit OR direct bit to carry flag 2 2 72

ORL C,/bit OR complement of direct bit to carry flag 2 2 A0

MOV C,bit move direct bit to carry flag 2 1 A2

MOV bit,C move carry flag to direct bit 2 2 92

Program and machine control

ACALL addr11 absolute subroutine call 2 2 · 1

LCALL addr16 long subroutine call 3 2 12

RET return from subroutine 1 2 22

RETI return from interrupt 1 2 32

AJMP addr11 absolute jump 2 2 ¨ 1

LJMP addr16 long jump 3 2 02

SJMP rel short jump (relative address) 2 2 80

JMP @A+DPTR jump indirect relative to the DPTR 1 2 73

JZ rel jump if A is zero 2 2 60

JNZ rel jump if A is not zero 2 2 70

JC rel jump if carry flag is set 2 2 40

JNC rel jump if carry flag is not set 2 2 50

JB bit,rel jump if direct bit is set 3 2 20

JNB bit,rel jump if direct bit is not set 3 2 30

JBC bit,rel jump if direct bit is set and clear bit 3 2 10

CJNE A,direct,rel compare direct to A and jump if not equal 3 2 B5

CJNE A,#data,rel compare immediate to A and jump if not equal 3 2 B4

CJNE Rr,#data,rel compare immediate to register and jump if notequal

3 2 B*

CJNE @Ri,#data,rel compare immediate to indirect and jump if notequal

3 2 B6, B7

DJNZ Rr,rel decrement register and jump if not zero 2 2 D*

DJNZ direct,rel decrement direct and jump if not zero 3 2 D5

NOP no operation 1 1 00

1997 Apr 10 41



P80CL410; P83CL410

Table 40 Description of the mnemonics in the Instruction set

MNEMONIC DESCRIPTION

Data addressing modes

Rr working register R0-R7

direct 128 internal RAM locations and any special function register (SFR)

@Ri indirect internal RAM location addressed by register R0 or R1 of the actual register bank

#data 8-bit constant included in instruction

#data 16 16-bit constant included as bytes 2 and 3 of instruction

bit direct addressed bit in internal RAM or SFR

addr16 16-bit destination address. Used by LCALL and LJMP;the branch will be anywhere within the 64 kbytes Program Memory address space

addr11 111-bit destination address. Used by ACALL and AJMP; the branch will be within thesame 2 kbytes page of Program Memory as the first byte of the following instruction

rel signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps;range is - 128 to +127 bytes relative to first byte of the following instruction

Hexadecimal opcode cross-reference

* 8, 9, A, B, C, D, E, F

· 1, 3, 5, 7, 9, B, D, F

¨ 0, 2, 4, 6, 8, A, C, E

1997 Apr 10 42



P80CL410; P83CL410

Tabl

e 41

Inst

ruct

ion

map

Not

e

1.M

OV

A, A

CC

is n

ot a

val

id in

stru

ctio

n.

Firs

t hex

adec

imal

cha

ract

er o

f opc

ode

¬ S

econ

d he

xade

cim

al c

hara

cter

of o

pcod

e ®

¯0

12

34

56

78

9A

BC

DE

F

0N

OP

AJM

Pad

dr11

LJM

Pad

dr16

RR A

INC A

INC

dire

ctIN

C @

Ri

INC

Rr

01

01

23

45

67

1JB

Cbi

t,rel

AC

ALL

addr

11LC

ALL

addr

16R

RC

AD

EC

AD

EC

dire

ctD

EC

@R

iD

EC

Rr

01

01

23

45

67

2JB

bit,r

elA

JMP

addr

11R

ET

RL A

AD

DA

,#da

taA

DD

A,d

irect

AD

D A

,@R

iA

DD

A,R

r0

10

12

34

56

7

3JN

Bbi

t,rel

AC

ALL

addr

11R

ET

IR

LC AA

DD

CA

,#da

taA

DD

CA

,dire

ctA

DD

C A

,@R

iA

DD

C A

,Rr

01

01

23

45

67

4JC re

lA

JMP

addr

11O

RL

dire

ct,A

OR

Ldi

rect

,#da

taO

RL

A,#

data

OR

LA

,dire

ctO

RL

A,@

Ri

OR

L A

,Rr

01

01

23

45

67

5JN

Cre

lA

CA

LLad

dr11

AN

Ldi

rect

,AA

NL

dire

ct,#

data

AN

LA

,#da

taA

NL

A,d

irect

AN

L A

,@R

iA

NL

A,R

r0

10

12

34

56

7

6JZ re

lA

JMP

addr

11X

RL

dire

ct,A

XR

Ldi

rect

,#da

taX

RL

A,#

data

XR

LA

,dire

ctX

RL

A,@

Ri

XR

L A

,Rr

01

01

23

45

67

7JN

Zre

lA

CA

LLad

dr11

OR

LC

,bit

JMP

@A

+D

PT

RM

OV

A,#

data

MO

Vdi

rect

,#da

taM

OV

@R

i,#da

taM

OV

Rr,#

data

01

01

23

45

67

8S

JMP

rel

AJM

Pad

dr11

AN

LC

,bit

MO

VC

A,@

A+

PC

DIV AB

MO

Vdi

rect

,dire

ctM

OV

dire

ct,@

Ri

MO

V d

irect

,Rr

01

01

23

45

67

9M

OV

DT

PR

,#da

ta16

AC

ALL

addr

11M

OV

bit,C

MO

VC

A,@

A+

DP

TR

SU

BB

A,#

data

SU

BB

A,d

irect

SU

BB

A,@

Ri

SU

B A

,Rr

01

01

23

45

67

AO

RL

C,/b

itA

JMP

addr

11M

OV

bit,C

INC

DP

TR

MU

LA

BM

OV

@R

i,dire

ctM

OV

Rr,d

irect

01

01

23

45

67

BA

NL

C,/b

itA

CA

LLad

dr11

CP

Lbi

tC

PL

CC

JNE

A,#

data

,rel

CJN

EA

,dire

ct,r

elC

JNE

@R

i,#da

ta,r

elC

JNE

Rr,#

data

,rel

01

01

23

45

67

CP

US

Hdi

rect

AJM

Pad

dr11

CLR bit

CLR C

SW

AP

AX

CH

A,d

irect

XC

H A

,@R

iX

CH

A,R

r0

10

12

34

56

7

DP

OP

dire

ctA

CA

LLad

dr11

SE

TB

bit

SE

TB

CD

A AD

JNZ

dire

ct,r

elX

CH

D A

,@R

iD

JNZ

Rr,r

el0

10

12

34

56

7

EM

OV

XA

,@D

TP

RA

JMP

addr

11M

OV

X A

,@R

iC

LR AM

OV

A,d

irect

(1)

MO

V A

,@R

iM

OV

A,R

r0

10

10

12

34

56

7

FM

OV

X@

DT

PR

,AA

CA

LLad

dr11

MO

VX

@R

i,AC

PL

AM

OV

dire

ct,A

MO

V @

Ri,A

MO

V R

r,A0

10

10

12

34

56

7

1997 Apr 10 43



P80CL410; P83CL410

19 LIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 134).

20 DC CHARACTERISTICSVSS = 0 V; Tamb = - 40 to +85 °C; all voltages with respect to VSS unless otherwise specified.

SYMBOL PARAMETER MIN. MAX. UNIT

VDD supply voltage - 0.5 +6.5 V

VI input voltage on any pin with respect to ground (VSS) - 0.5 VDD + 0.5 V

II DC current on any input - 5.0 +5.0 mA

IO DC current on any output - 5.0 +5.0 mA

Ptot total power dissipation - 300 mW

Tstg storage temperature - 65 +150 °CTamb operating ambient temperature - 40 +85 °CTj operating junction temperature - +125 °C

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDD supply voltage

operating VSS = 0 V 1.8 6.0 V

RAM retention in Power-down mode 1.0 - V

Operating supply current (note 1, note 2)

IDD operating supply current Oscillator 1; fclk = 32 kHz;VDD = 1.8 V; Tamb = 25 °C

- 50 m A

Oscillator 2; fclk = 3.58 MHz;VDD = 3 V

- 2.5 mA

Oscillator 2; fclk = 10 MHz;VDD = 5 V

- 14 mA


- 16 mA


- 20 mA

Supply current (Idle mode) (note 2, note 3)

IDD(idle) supply current (Idle mode) Oscillator 1; fclk = 32 kHz;VDD = 1.8 V; Tamb = 25 °C

- 25 m A

Oscillator 2; fclk = 3.58 MHz;VDD = 3 V

- 1.0 mA


- 5.0 mA


- 7.0 mA


- 8.5 mA

1997 Apr 10 44



P80CL410; P83CL410

Notes

1. The operating supply current is measured with all output pins disconnected; XTAL 1 driven with tr = tf = 10 ns;VIL = VSS; VIH = VDD; XTAL 2 not connected; EA = RST = Port 0 = VDD; all open drain outputs connected to VSS.

2. Circuits with Power-on-reset option ‘OFF’ are tested at VDD(min) = 1.8 V; within option ‘ON’ (typically 1.3 V) they aretested at VDD(min) = 2.3 V. Please note, option ‘ON’ is only available on P83CL410.

3. The Idle mode supply current is measured with all output pins disconnected; XTAL 1 driven with tr = tf = 10 ns;VIL = VSS. XTAL 2 not connected; EA = Port 0 = VDD; RST = VSS; all open drain outputs connected to VSS.

4. The Power-down current is measured with all output pins disconnected; XTAL 1 not connected; EA = Port 0 = VDD;RST = VSS; all open drain outputs connected to VSS.

Supply current (Power-down mode) (note 2, note 4)

IDD(pd) supply current (Power-down mode) VDD = 1.8 V; Tamb = 25 °C - 10 m A

Inputs

VIL LOW level input voltage VSS 0.3VDD V

VIH HIGH level input voltage 0.7VDD VDD V

IIL input current logic 0 (port 1,2,3) VDD = 5 V; VI = 0.4 V - - 100 m A

VDD = 2.5 V; VI = 0.4 V - - 50 m A

IITL input current logic 0, HIGH- to-LOWtransition (port 1,2,3)

VDD = 5 V; VI = 0.5VDD - - 1.0 mA

VDD = 2.5 V; VI = 0.5VDD - - 500 m A

ILI input leakage current (port 0, EA) VSS < VI < VDD - 10 m A

Port outputs

IOL LOW level output current (except SDA;SCL)

VDD = 5 V; VOL = 0.4 V 1.6 - mA

VDD = 2.5 V; VOL = 0.4 V 0.7 - mA

IOL LOW level output current (SDA; SCL) VDD = 5 V; VOL = 0.4 V 3.0 - mA

IOH HIGH level output current (push-pulloptions)

VDD = 5 V; VOH = VDD - 0.4 V - 1.6 - mA

VDD = 2.5 V; VOH = VDD - 0.4 V - 0.7 - mA

RRST RST pull-down resistor 10 200 kW

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

1997 Apr 10 45



P80CL410; P83CL410

Fig.21 Frequency operating range.

handbook, halfpage

842

fXTAL (MHz)

0 6VDD (V)

102

10

1

10 - 2

10 - 1

MBK026handbook, halfpage

2.0

0 2 6VDD (V)VDD MIN = 1.8 V

04

IDD (mA)

0.4

0.8

1.2

1.6

MBK047

1.2 MHz

32 kHz

Fig.22 Typical operating current as a function offrequency and VDD (32 kHz and 1.2 MHz).

Tamb = 25 °C.

Fig.23 Typical operating current as a function offrequency and VDD (3.58, 8 and 12 MHz).

Tamb = 25 °C.

handbook, halfpage

0 2 4 6

16

12

4

0

8

MBK027

VDD (V)

IDD (mA)

12 MHz

8 MHz

3.58 MHz

Fig.24 Typical Idle current as a function offrequency and VDD.

Tamb = 25 °C.

handbook, halfpage

0 2 4 6

4

5

3

1

0

2

MBK028

VDD (V)

IDD(idle) (mA)

12 MHz

8 MHz

3.58 MHz

1997 Apr 10 46



P80CL410; P83CL410

Fig.25 Typical Power-down current as a function ofVDD.

Tamb = 25 °C.

handbook, halfpage

0 2 4 6

8

6

2

0

4

MBK029

VDD (V)

IDD(pd) (m A)

1997 Apr 10 47



P80CL410; P83CL410

21 AC CHARACTERISTICSVDD = 5 V; VSS = 0 V; Tamb = - 40 to +85 °C; CL = 50 pF for Port 0, ALE and PSEN; CL = 40 pF for all other outputsunless specified; tCLK = 1/ fCLK.

SYMBOL PARAMETERfosc = 12 MHz fosc = VARIABLE

UNITMIN. MAX. MIN. MAX.

Program Memory (Fig.26)

tLHLL ALE pulse width 127 - 2tCLK - 40 - ns

tAVLL address valid to ALE LOW 43 - tCLK - 40 - ns

tLLAX address hold after ALE LOW 48 - tCLK - 35 - ns

tLLIV ALE LOW to valid instruction in - 233 - 4tCLK - 100 ns

tLLPL ALE LOW to PSEN LOW 58 - tCLK - 25 - ns

tPLPH PSEN pulse width 215 - 3tCLK - 35 - ns

tPLIV PSEN LOW to valid instruction in - 125 - 3tCLK - 125 ns

tPXIX input instruction hold after PSEN 0 - 0 - ns

tPXIZ input instruction float after PSEN - 63 - tCLK - 20 ns

tPXAV PSEN to address valid 75 - tCLK - 8 - ns

tAVIV address to valid instruction in - 302 - 5tCLK - 115 ns

tPLAZ PSEN LOW to address float 12 - 0 - ns

External Data Memory (Figs 27 and 28)

tRLRH RD pulse width 400 - 6tCLK - 100 - ns

tWLWH WR pulse width 400 - 6tCLK - 100 - ns

tLLAX address hold after ALE LOW 48 - tCLK - 35 - ns

tRLDV RD LOW to valid data in - 150 - 5tCLK - 165 ns

tRHDZ data float after RD - 97 - 2tCLK - 70 ns

tLLDV ALE LOW to valid data in - 517 8tCLK - 150 ns

tAVDV address to valid data in - 585 - 9tCLK - 165 ns

tLLWL ALE LOW to RD or WR LOW 200 300 3tCLK - 50 3tCLK + 50 ns

tAVWL address valid to RD or WR LOW 203 - 4 - ns

tWHLH RD or WR HIGH to ALE HIGH 43 123 tCLK - 40 tCLK + 40 ns

tQVWX data valid to WR transition 23 - tCLK - 60 - ns

tQVWH data valid time WR HIGH 433 - 7tCLK - 150 - ns

tWHQX data hold after WR 33 - tCLK - 50 - ns

tRLAZ RD LOW to address float - 12 - 12 ns

1997 Apr 10 48



P80CL410; P83CL410

Fig.26 Read from Program Memory.

andbook, full pagewidth

MGD680

t LHLL

ALE

PORT 0

PORT 2

t CY

LLIVt

t LLPL

t PLPH

t LLAX

tAVLL

AVIVt

PLAZt

PLIVt

t PXIX

t PXIZ

t PXAV

address A8 to A15 address A8 to A15

inst. inputinst. input A0 to A7A0 to A7

PSEN


MGA177

t LHLL

ALE

PORT 0

PORT 2

t CY

t LLDV

t LLAXt AVLL

AVDVt

RLAZt

address A8 to A15 (DPH) or Port 2

data inputA0 to A7

PSEN

tWHLH

AVWLt

t LLWL t RLRH

t RHDX

t RHDZ

t RLDV

RD

Fig.27 Read from Data Memory.

1997 Apr 10 49



P80CL410; P83CL410

Fig.28 Write to Data Memory.


MGA178

t LHLL

ALE

PORT 0

PORT 2

t CY

t LLAXtAVLL

address A8 to A15 (DPH) or Port 2

data outputA0 to A7

PSEN

tWHLH

AVWLt

t LLWL t WLWH

t WHQXt QVWH

t QVWX

WR

1997 Apr 10 50



P80CL410; P83CL410

Fig.29 Instruction cycle timing.


MGD681

P1 P2S1

P1 P2S2

P1 P2S3

P1 P2S4

P1 P2S5

P1 P2S6

P1 P2S1

P1 P2S2

P1 P2S3

P1 P2S4

P1 P2S5

P1 P2S6

one machine cycle one machine cycle

XTAL1 INPUT

address A0 - A7

inst. in

address A0 - A7

inst. in

address A0 - A7

inst. in

address A0 - A7

inst. in

address A8 - A15address A8 - A15address A8 - A15address A8 - A15

address A0 - A7

inst. in

address A0 - A7

inst. in

address A0 - A7

data output or data input

address A8 - A15address A8 - A15 or Port 2 outputaddress A8 - A15

old data new data

sampling time of I/O port pins during input

SERIAL PORT SHIFT CLOCK (MODE 0)

PORT 0, 2, 3 INPUT

PORT 0, 2, 3 OUTPUT

PORT 2

BUS (PORT 0)read or

write of external data

memory

PORT 2

BUS (PORT 0)

external program memory

fetch

WR

RD

only active during a write

to external data memory

only active during a read from external data memory

PSEN

ALE

dotted lines are valid when RD or WR are

active

old data new dataPORT 1 OUTPUT

1997 Apr 10 51



P80CL410; P83CL410

Fig.30 AC testing input waveform.

handbook, halfpage

MLA586

0.9 V

0.4 V

0.7 V

0.3 V

0.7 V

0.3 V

test points

DD

DD

DD

DD DD

DD

MBK023

0.5 VDD VDD0

100 m A

IIL(T)

I IL

II

500 m A

Fig.31 Input current.

1997 Apr 10 52



P80CL410; P83CL410

22 P85CL000HFZ ‘PIGGY-BACK’ SPECIFICATION

The differences between the masked version and thepiggy-back are described below.

22.1 General description

The P85CL000HFZ is a piggy-back version with 256 bytesof RAM used for emulation of the P83CL410 and theP80CL51 microcontrollers. The P85CL000HFZ ismanufactured in an advanced CMOS technology.The instruction set of the P85CL000HFZ is based on thatof the 8051. The device has low power consumption and awide supply voltage range. The P85CL000HFZ has twosoftware selectable modes of reduced activity for furtherpower reduction: Idle and Power-down. For timing andAC/DC characteristics, please refer to the P83CL410specifications.

22.2 Feature differences/additional features ofP85CL000HFZ with respect to P83CL410

· No internal ROM

· 8-bit CPU, RAM, I/O in a single 40-lead package withDIP pin-out

· Socket for up to 16 kbytes external EPROM

· 256 bytes RAM, expandable externally to 64 kbytes

· UART interface

· On-chip oscillator: Oscillator 4 option only.

22.3 Common specification/feature differences between P85CL000HFZ and P83CL410/P80CL51

PARAMETER P83CL410/P80CL51 P85CL000HFZ ‘PIGGY-BACK’

RAM size 128 256

ROM size 4K EPROM size dependent (max. 16K)

Port options 1, 2, 3 1

Oscillator options Oscillator 1, 2, 3, 4, RC Oscillator 4

Mechanical dimensions standard dual in-line, small outline same pin-out as SOT129-1, but largerpackage size

Current consumption IDD IDD (Oscillator 4) + IEPROM

Voltage range full full, limited by EPROM

ESD specification not tested (different package)

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P80CL410; P83CL410

23 PACKAGE OUTLINES

UNIT Amax.

1 2 b1 c D E e MHL

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT129-192-11-1795-01-14

A min.

A max. b Z

max.wMEe1

1.701.14

0.530.38

0.360.23

52.5051.50

14.113.7

3.603.05 0.2542.54 15.24

15.8015.24

17.4215.90 2.254.7 0.51 4.0

0.0670.045

0.0210.015

0.0140.009

2.0672.028

0.560.54

0.140.12 0.010.10 0.60

0.620.60

0.690.63 0.089 0.19 0.020 0.16

051G08 MO-015AJ

MH

c

(e )1

ME

A

L

seat

ing

plan

e

A1

w Mb1

e

D

A2

Z

40

1

21

20

b

E

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

(1)(1)(1)

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

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P80CL410; P83CL410

UNIT A1 A2 A3 bp c D(1) E(2) Z(1)e HE L Lp Q ywv q

REFERENCESOUTLINE VERSION

EUROPEAN PROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm

inches

0.3 0.1

2.45 2.25 0.25

0.42 0.30

0.22 0.14

15.6 15.2

7.6 7.5 0.762 2.25

12.3 11.8

1.15 1.05

0.6 0.3 7

0

o

o

0.1 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes


2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

1.7 1.5

SOT158-192-11-17 95-01-24

X

w M

q

AA1

A2

bp

D

HE

Lp

Q

detail X

E

Z

e

c

L

v M A

(A )3

A

y

40

20

21

1

pin 1 index

0.012 0.004

0.096 0.089

0.017 0.012

0.0087 0.0055

0.61 0.60

0.30 0.29 0.03 0.089

0.48 0.46

0.045 0.041

0.024 0.0120.004

0.2

0.008 0.0040.067 0.0590.010

0 5 10 mm

scale

VSO40: plastic very small outline package; 40 leads SOT158-1

A max.

2.70

0.11

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P80CL410; P83CL410

UNIT A1 A2 A3 bp c E(1) e HE L Lp Q Zywv q

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm 0.250.05

1.851.65 0.25

0.400.20

0.250.14

10.19.9 0.8 1.3

12.912.3

0.850.75

1.20.8

100

o

o0.15 0.10.15

DIMENSIONS (mm are the original dimensions)

Note


0.950.55

SOT307-292-11-1795-02-04

D(1) (1)(1)

10.19.9

HD

12.912.3

EZ

1.20.8

D

e

E

B

11

c

EH

D

ZD

A

ZE

e

v M A

X

1

44

34

33 23

22

12

y

q

A1A

Lp

Q

detail X

L

(A )3A2

pin 1 index

DH v M B

bp

bp

w M

w M

0 2.5 5 mm

scale

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

Amax.

2.10

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P80CL410; P83CL410

24 SOLDERING

24.1 Introduction

There is no soldering method that is ideal for all ICpackages. Wave soldering is often preferred whenthrough-hole and surface mounted components are mixedon one printed-circuit board. However, wave soldering isnot always suitable for surface mounted ICs, or forprinted-circuits with high population densities. In thesesituations reflow soldering is often used.

This text gives a very brief insight to a complex technology.A more in-depth account of soldering ICs can be found inour “IC Package Databook” (order code 9398 652 90011).

24.2 DIP

24.2.1 SOLDERING BY DIPPING OR BY WAVE

The maximum permissible temperature of the solder is260 °C; solder at this temperature must not be in contactwith the joint for more than 5 seconds. The total contacttime of successive solder waves must not exceed5 seconds.

The device may be mounted up to the seating plane, butthe temperature of the plastic body must not exceed thespecified maximum storage temperature (Tstg max). If theprinted-circuit board has been pre-heated, forced coolingmay be necessary immediately after soldering to keep thetemperature within the permissible limit.

24.2.2 REPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to thelead(s) of the package, below the seating plane or notmore than 2 mm above it. If the temperature of thesoldering iron bit is less than 300 °C it may remain incontact for up to 10 seconds. If the bit temperature isbetween 300 and 400 °C, contact may be up to 5 seconds.

24.3 QFP

24.3.1 REFLOW SOLDERING

Reflow soldering techniques are suitable for all QFPpackages.

The choice of heating method may be influenced by largerplastic QFP packages (44 leads, or more). If infrared orvapour phase heating is used and the large packages arenot absolutely dry (less than 0.1% moisture content byweight), vaporization of the small amount of moisture inthem can cause cracking of the plastic body. For moreinformation, refer to the Drypack chapter in our “QualityReference Handbook” (order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension offine solder particles, flux and binding agent) to be appliedto the printed-circuit board by screen printing, stencilling orpressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,thermal conduction by heated belt. Dwell times vary from50 to 300 seconds depending on heating method. Typicalreflow temperatures range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporatethe binding agent. Preheat for 45 minutes at 45 °C.

24.3.2 WAVE SOLDERING

Wave soldering is not recommended for QFP packages.This is because of the likelihood of solder bridging due toclosely-spaced leads and the possibility of incompletesolder penetration in multi-lead devices.

If wave soldering cannot be avoided, the followingconditions must be observed:

· A double-wave (a turbulent wave with high upwardpressure followed by a smooth laminar wave)soldering technique should be used.

· The footprint must be at an angle of 45 ° to the boarddirection and must incorporate solder thievesdownstream and at the side corners.

Even with these conditions, do not consider wavesoldering the following packages: QFP52 (SOT379-1),QFP100 (SOT317-1), QFP100 (SOT317-2),QFP100 (SOT382-1) or QFP160 (SOT322-1).

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P80CL410; P83CL410

During placement and before soldering, the package mustbe fixed with a droplet of adhesive. The adhesive can beapplied by screen printing, pin transfer or syringedispensing. The package can be soldered after theadhesive is cured. Maximum permissible soldertemperature is 260 °C, and maximum duration of packageimmersion in solder is 10 seconds, if cooled to less than150 °C within 6 seconds. Typical dwell time is 4 secondsat 250 °C.

A mildly-activated flux will eliminate the need for removalof corrosive residues in most applications.

24.3.3 REPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally-opposite end leads. Use only a low voltage soldering iron(less than 24 V) applied to the flat part of the lead. Contacttime must be limited to 10 seconds at up to 300 °C. Whenusing a dedicated tool, all other leads can be soldered inone operation within 2 to 5 seconds between270 and 320 °C.

24.4 Reflow soldering

Reflow soldering techniques are suitable for all VSOpackages.

Reflow soldering requires solder paste (a suspension offine solder particles, flux and binding agent) to be appliedto the printed-circuit board by screen printing, stencilling orpressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,thermal conduction by heated belt. Dwell times varybetween 50 and 300 seconds depending on heatingmethod. Typical reflow temperatures range from215 to 250 °C.

Preheating is necessary to dry the paste and evaporatethe binding agent. Preheating duration: 45 minutes at45 °C.

24.5 Wave soldering

Wave soldering techniques can be used for all VSOpackages if the following conditions are observed:

· A double-wave (a turbulent wave with high upwardpressure followed by a smooth laminar wave) solderingtechnique should be used.

· The longitudinal axis of the package footprint must beparallel to the solder flow.

· The package footprint must incorporate solder thieves atthe downstream end.

During placement and before soldering, the package mustbe fixed with a droplet of adhesive. The adhesive can beapplied by screen printing, pin transfer or syringedispensing. The package can be soldered after theadhesive is cured.

Maximum permissible solder temperature is 260 °C, andmaximum duration of package immersion in solder is10 seconds, if cooled to less than 150 °C within6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removalof corrosive residues in most applications.

24.6 Repairing soldered joints

Fix the component by first soldering two diagonally-opposite end leads. Use only a low voltage soldering iron(less than 24 V) applied to the flat part of the lead. Contacttime must be limited to 10 seconds at up to 300 °C. Whenusing a dedicated tool, all other leads can be soldered inone operation within 2 to 5 seconds between270 and 320 °C.

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P80CL410; P83CL410

25 DEFINITIONS

26 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of theseproducts can reasonably be expected to result in personal injury. Philips customers using or selling these products foruse in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from suchimproper use or sale.

27 PURCHASE OF PHILIPS I2C COMPONENTS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one ormore of the limiting values may cause permanent damage to the device. These are stress ratings only and operationof the device at these or at any other conditions above those given in the Characteristics sections of the specificationis not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use thecomponents in the I2C system provided the system conforms to the I2C specification defined byPhilips. This specification can be ordered using the code 9398 393 40011.

1997 Apr 10 59



P80CL410; P83CL410

NOTES

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1997 SCA54

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changedwithout notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any licenseunder patent- or other industrial or intellectual property rights.

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,Tel. +47 22 74 8000, Fax. +47 22 74 8341

Philippines: Philips Semiconductors Philippines Inc.,106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,Tel. +381 11 625 344, Fax.+381 11 635 777

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,Tel. +43 1 60 101, Fax. +43 1 60 101 1210

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Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,51 James Bourchier Blvd., 1407 SOFIA,Tel. +359 2 689 211, Fax. +359 2 689 102

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Colombia: see South America

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Hungary: see Austria

India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722

Indonesia: see Singapore

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Middle East: see Italy

Printed in The Netherlands 457047/1200/02/pp60 Date of release: 1997 Apr 10 Document order number: 9397 750 01518

NXP P80CL410, P83CL410 Data Sheet · 2004-11-03 · DIP40 DESCRIPTION VSO40 QFP44 P1.0/INT2 1 40...

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Transcript of NXP P80CL410, P83CL410 Data Sheet · 2004-11-03 · DIP40 DESCRIPTION VSO40 QFP44 P1.0/INT2 1 40...