PROGRAMMABLE LOGIC DEVICES

By: T V S Ram Email address: tvsramisro@gmail.com

The programmable logic devices have traveled a large distance from their birth and grown to various forms from PROMS (Programmable read only memories), PLA’s (programmable logic arrays), PALs (Programmable array logic), PLD’s (programmable logic devices) and FPGA (Field Programmable Gate Array). The programmable logic devices are replacing discrete logic components which simplifies in design, development, and implementation. The function provided by each of the 7400 series parts is limited and fixed and it cannot be tailored to suit a particular design situation. This fact, coupled with the limitation that each chip have only a few number of logic gates, makes these chips inefficient for building large logic circuits. It is possible to manufacture chips that contain relatively large amounts of logic circuitry with a structure that is not fixed. Such chips were first introduced in the 1970 and are called programmable logic devices (PLDs). These devices enable the design engineer to program the logic elements to meet the specific design applications. The flexibility in the design, availability of tools for simulation and re-programmability enabled the designer to go for efficient design and development process. The architecture of these chips vary from device to device and also between manufacturers. Devices are available whose architectures are application oriented. Programming equipments and supporting tools for design, simulation and verification are coming up with more and more features and with more standard logic elements or functions in the part library. These are all available either from the manufactures themselves or from third party vendors. PC based software tools are also available to allow schematic, state machine entry, waveform entry, Boolean equations, truth table entries and through hardware description language (HDL). In the performance arena the programmable logic chips are no inferior to their discrete counter parts. As it consumes many discrete chips to one single chip their reliability goes very high ,power consumption drastically decreases. In short a programmable logic device is a general purpose chip for implementing logic circuitry. It contains a collection of logic circuit elements that can be tailored or customized in different ways. A PLD can be viewed as a “ Black Box” that contains logic gates and programmable switches, as shown in fig1.

LOGIC GATESAND

PROGRAMMABLESWITCHES

INPUTS(LOGIC VARIABLES)

OUTPUTS(LOGIC FUNCTIONS)

Fig 1. PROGRAMMABLE LOGIC DEVICE AS A BLOCK BOX

The programmable switches allow the logic gates inside the PLD to be connected together to implement whatever logic circuit is needed. This makes the real estate on the printed circuit board required is very small. Therefore the problems associated with longer signal tracks ground returns are eliminated. The following are the other advantages of the programmable logic chips.

Full benefits of full custom Short time to market. Lots of design cores are available in the market in HDL. No NRE (Non recurrence expenditure) No test issues No ASIC re-spin risk. Easy ,Faster and flexible design development and verification process Saves overall valuable board space. Re-programmability and configurability and up-gradability of the design

makes them versatile. Existence of PC based supporting tools for design, development and

simulation. Availability of application oriented devices architectures. Availability of programming equipments for design implementation and

verification. Very cost effective High reliability and lower power consumption Reduces inventory associated with large number of discrete Ics Security of the design.

Though the logic chips boast of their merits they are not without their limitations. Since various manufactures provide devices which are architecturally different, the designer must understand and choose the device whose architecture would suit their individual application and enable himself implementation of optimal design and efficient usage of resources. Not many universal programming equipments are available, which forces the user to either to restrict one type of device or invest in procuring various programming equipments. Unfortunately there is no standardization in the methods of defining specifications. However, of-late manufactures started using PREP as their bench mark. The following are the dis-advantages of the programmable logics.

No standardization in the specifications. Delays vary depending on the signal path and frequency of operation. Poor thermal characterization in nonmilitary devices of course with the

development of new technology and thereby new devices, this problem was taken care.

Programmable memories. In general programmable memories are classified into mask programmable ROM which is simply called as ROM, one time programmable ROM (PROM), UV

erasable and electrically erasable and electrically programmable ROM (EPROM) and electrically erasable programmable ROM (EEPROM). The basic programmable memory consists of an address decoder and a data matrix with ‘n’ address lines ROM includes 2n word lines, Address information received at the address decoder is used to select any one of 2n lines. The selected word line is driven to logic ‘1’ while the other lines remain at logic ‘0’. For each word line there exists ‘m’ programmable cross points corresponding to the ‘m’ bits of the word. The cross points are programmed by the inclusion or exclusion of a MOS transistor at the cross point. For the cross points without the transistor, the bit line will remain at logic ‘1’, causing the output line for that bit to be 0 due to inverter at the output. But, where a transistor connects the selected word line to a bit line, the transistor will be tuned “ON” and the bit line will be pulled to a zero state. The corresponding output line will go to logic ‘1’ state. The address decoder of ROM is exhaustive i.e., all possible addresses are decoded, with a word line provided for each address. Other ROM organization include selecting many words for a single word line. A multiplexor on the bit line then select the single word desired. This approach reduces the size of the decoder and squares up the data matrix but adds up a multiplexor. However the net result is a ROM which is easier to implement. Even through the organization is different, the general concept is same, regid, exhaustive, non-programmable data addressing with programming data. Mask –programmed Rom: In this type of Mask Programmed Rom the information is permanently stored by masks during fabrication by the manufacturers and once set it cannot be altered. A Mask programmed Rom is implemented in bipolar type with diodes/transistors (TTL or ECL) and in MOS type MOSFET. In bipolar type, data are stored by connecting diodes between word lines and bit lines. Then only those bit lines that are connected to the word lines via diodes / MOSFET s have high voltages. The connection of gates of MOSFETs are realized by varying the width of the silicon dioxide insulation layer underneath the metal gates. If a portion of the layer is thin MOSFET Is formed. If a portion of the layer is thick, a horizontal metal connection cannot function as a MOSFET gate, and a MOSFET is not formed. The ROM is much easier to manufacture because of its simpler storage mechanism. Programming or masking requires custom preparation of only one connection or gate mask leaving the other masks intact. This makes ROMs very economical among all memories. Although mask programmable ROM s available in the market may not necessarily be the fastest, the technology allows them to be manufactured with higher speed (20 – 50ns). The packing density is also very high. In one approach, three different sizes of MOSFET s by sense amplifiers, each memory cell can store two bits instead of one bit, but at the sacrifice of yield in chip fabrication. Another approach is the use of two layers of lines conduction path between the two layers. Here the chip area is roughly halved.

When micro programs are completely debugged and need not be rewritten during computation and if to be packed in small space as calculators, ROMs can be used efficiently. Another advantage of using ROM for software stored (often called firmware) can simply be inserted into a calculator or computer, with metal pins and without any mechanically moving equipment. Whereas if software is to be stored in a RAM, it must be loaded using a mechanically moving equipment such as a paper or magnetic tape reader, which are unreliable and expensive requiring maintenance. When electronic circuits for ROM decoders, sense amplifiers and other circuits are dynamic, these ROMs are called dynamic ROM and have the advantage of low standby power consumption. Otherwise ROMs are called static ROM. PROM: For small quantity production of ROM, custom preparation of even a single connection mask may be expensive or delivery time from a semiconductor manufacture may be too long./ Hence field programmable ROMs (EPROMs) are available, where users can set informations by themselves, but only once. In the commonly used structers of ROM, a diode / transistor and fuse are connected in series at every cross point of word and bit lines.

Fig: 2 : Prom Address Decoder.

DECODER

A1

A2

A3

A4

An

INPU

TS

W1

W2

W3

W4

W 2n-1

W2n

2n

WORSLINES

D1 D2 D3 DM

Va a

M OUTPUTS

Fig2: shows how the address decoder functions in the case of proms. To store information, users blow the fuses at a desired intersections by feeding in heavy currents. On a chip, special electronic circuits are provided to supply these heavy currents, adding 40- 50 % area on the chip. Programmable logic array (PLA): PLA is a special type of ROM. In ROM addressing is fixed and only the data is programmable. Conversely, in PLAs addressing itself is programmable overcoming the rigidity of ROM. Several types of PLD s are commercially available. The first developed was the programmable logic array (PLA). The general structure of a PLA is depicted in Fig 3 Based on the idea that logic functions can be realized in sum-of-products form, a PLA comprises a collection of AND gates that feeds a set of OR gates. As shown in the figure, the PLA’s inputs x1,…..xn pass through a set of buffers ( which provide both the true value and compliment of each input) into a circuit block called an AND plane, or AND array. The AND plane produces a set of product terms P1,…. PK. Each of these terms can be configured to implement any AND function of x1,…. Xn. The product terms serve as the inputs to an OR plane, which produces the outputs f1…. fm. Each output can be configured to realize any sum of P1,…. PK and hence any sum of products function of the PLA inputs..

Fig:3: General Structure of PLA

INPUT BUFFERSAND

INVERTERS

AND PLANE OR PLANE

X1 X2 Xn

X1 X1 Xn Xn

P1

P2

f1 fm

. In the figure 4 the AND gate that produces P1 is shown connected to the inputs x1 and x2. Hence P1= x1x2. Similarly P2 = x1 (!x3), p3 = (!x1)(!x2)x3, and P4 = x1 x3. Programmable connection also exist for the OR plane. Output f1 is connected to product terms P1, P2, P3. It therefore realizes the function f1 = x1x2+ x1 (!x3), + (!x1)(!x2)x3. Similarly, output f2 = x1x2+(!x1)(!x2)x3+ x1x3. Although fig.4 depicts the PLA programmed to implement the function described above, by programming the AND and OR planes differently, each of the outputs f1 and f2 could implement various functions of x1, x2, x3The only constraint on the functions that can be implemented is the size of the AND plane because it produces only four product terms. Commercially available PLA’s come in larger sizes that we have shown here. Typical parameters are 16 inputs, 32 products terms, and eight outputs.

X1 X2 X3

AND Plane

P1

P2

P3

P4

f1 f2

PROGRAMMABLECONNECTION

Fig 4: GATE-LEVEL DIAGRAM OF A PLA

Although figure 4 illustrates clearly the functional structure of a PLA , this style of drawing is awkward for larger chips. Instead it has become customary in technical literature to use the style shown in fig 5:. Each AND gate is depicted as a single horizontal line attached to an AND-gate symbol. The possible inputs to the AND gate are drawn as vertical lines that cross the horizontal line. At any crossing of a vertical and horizontal line, a programmable connection, indicated by an X, can be made. Fig:5, show the programmable connections needed to

X1 X2 X3

AND Plane

P1

P2

P3

P4

f1 f2

Fig 5:CUSTOMARY SCHEMATIC FOR THE PLA IN fig 4.

X X

XX

XXX

XX

X X

X

X X

X

OR Plane

implement the product terms in fig 4:. Each OR fate is drawn in a similar manner, with a vertical line attached to an OR –gate symbol. The AND gate outputs cross these lines, and corresponding programmable connections can be

formed. The figure illustrates the programmable connections that produce the functions f1 and f2 from fig:4. The PLA is efficient in terms of the area needed for its implementation on an integrated circuit chip. For this reason, PLA are often included as part of larger chips, such as microprocessors. In this case a PLA is created so that the connections to the AND and OR gates are fixed, rather than programmable. PROGRAMMABLE ARRAY LOGIC (PAL). PAL is an PLA where the OR array is not programmable. The concept of this family of devices is that there are innumerable combination of logic, but, some are always seem to be required. By taking the flexibility of single level programmable gate arrays and combining it with additional logic elements, the functional complexity of two level PLAs can be reached while being simpler to understand and use efficiently. The advantage of PAL is the elimination of fuses in the OR array and associated electronics to blow them. So, a large area is save in a PAL. When MSI, LSI and VLSI off – the -shelf packages for standard network and microprocessors and their peripheral network are assembled and PC boards, many non – standard network are usually required for interfacing other key network or for minor modifications , and they require many SSI packages, and discrete component, occupying significant share of the areas on PC boards. PAL packages can replace them, reducing the area to one fourth or less, though the number of gates per FPAL is limited to a few hundred due to the large area occupied by the fuse blowing circuits and fuses. Also, when logic design is not finalized and needs to be changed often, these PAL packages can reduce expenses and time for repeatedly designing and remaining PC boards. PALs are generally used in minicomputers. In a PLA both AND and OR planes are programmable. Historically, the programmable switches presented two difficulties for manufactures of these device: they were hard to fabricate correctly, and they reduced the speed performance of circuits implemented In the PLAs. These drawbacks led to the development of a similar device in which the AND plane is programmable, but the OR plane is fixed. Such a chip is known as a programmable array logic (PAL) device. Because they are simpler to manufacture, and thus less expensive than PLA s, and offer better performance. PAL s have offer better performance, PALs have become popular in practical applications. An example of a PAL with three inputs, four product terms, and two outputs is given in Fig 6. The product terms P1 AND P2 are hardwired to one OR gate, and P3 and P4 are hardwired to the other OR gate. The PAL is shown programmed to realize the two logic functions f1 = x1 x2 (!x3) + (!x1)x2x3 and f2 = (!x1)(!x2) + x1 x2 x3. In comparison to the PLA of Fig 4 and 6., the Pal offer less flexibility; the PLA allows up to four product terms per OR gate, where as the OR gates in the PAL have only two inputs. To compensate for the reduced flexibility. PAL’s are manufactured in a range of sizes, with various numbers of inputs and outputs, and different numbers of inputs to the OR gates..

So far we have assumed that the OR gates in a PAL, as in a PLA, connect directly to the output pins of the chip. In many PALs extra circuitry is added at the output of each OR gate to provide additional flexibility. It is customary to use the term macro-cell to refer to the OR gate combined with the extra circuitry. An example of the flexibility that may be provided in a macro cell is given in Fig 7. The flip flop is controlled by the signal called clock. When clock makes a transition from logic value 0 to 1, the flip flop stores the value at its D input at that time and this value appears at the flop flop’s Q output. Flip-Flops are used for implementing many types of logic circuits.

X1 X2 X3

AND Plane

P1

P2

P3

P4

FIG 6: AN EXAMPLE OF A PAL

X X

XX

XX

XX

f1

X

X

X

TO AND PLANE

f2

Let us discuss a 2 to 1 multiplexer circuit. It has two data inputs, a select input, and one output. The select input is used to choose one of the data inputs as the multiplexer’s output. In fig 7. the 2 to 1 multiplexer selects as an output. From the PAL either the OR gate output or the flip flop output. The multiplexer’s select lines can be programmed to be either 0 or 1. Fig 7 shows another logic gate, called a tri-state buffer, connected between the multiplexer and the PAL out. Finally the multiplexer’s output is “fed back” to the AND plane in the PAL. This

feedback connection allows the logic function produced by the multiplexer to be used internally in the PAL, which allows the implementation of circuits that have multiple stages or levels, of logic gates. A number of companies manufacture PLAs or PALs, or other, similar types of simple PLDs (SPLDs).

D

Q

QCLK

FLIP-FLOP

SELECT ENABLE

f1

Fig: 7 Extra Circuitry added to ortGATE outputs to fig 6.

PLDs: PLDs also, like other programmable devices, is an array of basic logic elements interconnected by fusible links,. Or programmable EPROM type cells. These devices combine the logistical advantages of standard, fixed integrated chips with the architectural flexibility of custom devices. These devices allow users to electrically program standard off – the –shelf logic elements to meet the specific needs of their applications. Proprietary logic functions can be designed and fabricated in house eliminating the long engineering lead times,. High tooling costs, complex procurement logistics and dedicated inventory problems associated with the custom ASIC devices. EPLDs can be used to integrate complete PCB of TTL, PAL etc., devices into a single package. Although the device architecture of PLDs vary from device to device and between manufactures they mainly consist of a combinational logic array, sequential logic elements and I/O elements where all of them are programmable. The combinational logic array and the sequential logic elements constitute a macro cell. The logic array is nothing but a PAL structure with programmable AND array feeding product terms into fixed OR array. The output of OR array can be inverted to reduce the number of product terms required to implement a function by applying the De morgan’s theroum. These are fed to programmable registers that provide D, T, JK st OPTIONS. The registers can also be bypassed. These fip-flops can be clocked from dedicated global clock or clock from any I/O pins or any logic function. The I/O blocks contain a tri-state buffer controlled by a macro-cell product term and drives the I/O pins. The I/O pins can be configured as dedicated inputs or outputs or as bi-directional outputs. Most EPLDs have “dual feed back” whereby the macro-cell feedback is decoupled from I/O feedback. This makes it possible \to implement a buried function in the macro-cell while the I/O pin is used simultaneously as dedicated input. All macro-cell functions are globally routed. In higher density EPLDs called complex EPLDs a special type of interconnect routing is done between groups of macros. This enhances the operational speed . Direct routing between macros and I/O blocks also enables the delay predictable. It also imposes minimal demand on the automatic layout tools and therefore successful routing is achieved by modest tools in only a short

time. Though PLDs are simple to use, cheap and fast their main drawback is density and utilization. Both attributed to the single AND / OR array architecture, which limits the number of product terms per macro. Also, there is little or no evidence of sharing of product terms between the macros, However some EPLD s also have expander product terms (expanders) which are unallocated inverted product terms that can be used and shared by all macros to create combinational and registered logics. Although this approach offers increased functionally form the macro-cell, it increases the routing delays. Also, considerable silicon area is required to provide the logic expansion and it also leads to increased inefficiency of resource utilization. EPLDs are based on EPROM technology. Consequently, the configuration date are non volatile and erasable, electrically or using UV rays. Other technologies include SRAM based embedded registered and one time programmable antifuse technologies. Advantages of EPLDs:

Simplified design process. Mostly standard architecture and easy to use. Low cost design and development tools Deterministic, uniform delays and predictable timing.

Disadvantages and limitations of EPLD;

Low to moderate density. Low utilization of internal resources. Inflexible architecture.

Complex programmable logic devices (CPLDs) PLAs and PALs are useful for implementing a wide variety of small digital circuits. Each device can be used to implement circuits that do not require more than the number of inputs, product terms, and outputs that are provided in the particular chip. These chips are limited to fairly modest sizes, typically supporting a combined number of inputs plus outputs of not more than 32. For implementation of circuits that require more inputs and outputs, either multiple PLAs or PALs can be employed or else a more sophisticated type of chip, called a complex programmable logic device (CPLD)s, can be used/ A CPLD comprises multiple circuit blocks on a single chip, with internal wiring resources to connect the circuit blocks. Each circuit block is similar to a PLA or a PAL; we will refer to the circuit blocks as PAL –like blocks. An example of a CPLD is given in fig 8. It include four PAL –like blocks that are connected to a set of interconnection wires. Each PAL – like block is also connected to a sub circuit labeled I / O block, which is attached to a number of the chip’s input and output pins.

Fig 9 shows an example of the wiring of the wiring structure and the connections to a PAL like block in a CPLD. The PAL –like block includes 3 macrocells ( real CPLDs typically have about 16 macrocells in a PAL –like block), each consisting of a four-input OR gate ( real CPLDs usually provide between 5 and 20 inputs to each OR gate). The OR gate output is connected to another type of logic gate that we have not yet introduced. It is called an exclusive –OR (XOR) gate. The behavior of an XOR gate is the same as for an OR gate except that if both of the inputs are 1, the XOR gate produces a 0. One input to the XOR gate in fig 9 can be programmable connected to 1 or 0; if 1, then the XOR GATE complements the OR gate output, and if 0 then the XOR gate has no effect. The macro cell also includes a flip-flop a multiplexer, and a tri-state buffer. AS we mentioned in the discussion for fig 9, the flip-flop is used to store the output value produced by the OR gate. Each tri-sate buffer acts as a switch that allows each pin to be used either as an output from the CPLD or as an input. To use a pin as an output, the corresponding tri-state buffer is enabled, acting as a switch that is turned on. If the pin is to be used as an input, then the tri state buffer is disabled, acting as a switch that s turned off. In this case an external source can drive a signal onto the pin, which can be connected to other macro cells using the interconnection wiring. The interconnection wiring contains programmable switches that are used to connect the PAL like blocks. Each of the horizontal wires can be connected to some of the vertical wires that it crosses, but not to all of them. Extensive research has been done to decide how many switches should be provided for connections between the wires. The number of switches is chosen to provide sufficient flexibility for typical circuits without wasting many switches in practice. One detail to note is that when a pin is used as an input, the macrocell associated with that pin cannot be used and is therefore wasted. Some CPLD include additional connection between the macro-cells and the interconnection wiring that avoids wasting macro-cells in such situations. Commercial CPLDs range in size from only 2 PAL like blocks to more than 100 PAL like blocks. They are available in a variety of packages, including the PLCC packages. They are also available the other packages such as QUAD FLAT PACK (QFP). Like a PLCC package, the QFP package has pins on all four sides, but where as the PLCC’s pins wrap around the edges of the package, the QFP’s pins extend outward from the package, with a downward –curving shape. The QFP’s pins are much thinner than those on a PLCC, which means that the package can support a larger number of pins; QFPs are available with more than 200 pins, whereas PLCCs are limited to fewer than 100 pins.

PAL-LIKEBLOCK

PAL-LIKEBLOCK

I/O B

LOC

K

I/O B

LOC

K

PAL-LIKEBLOCK

PAL-LIKEBLOCK

I/O B

LOC

K

I/O B

LOC

K

INTERCONNECTION WIRES

Fig 9.STRUCTURE OF A COMPLEX PROGRAMMABLE LOGIC DEVICE(CPLD)

Most CPLD s contain the programmable switches. Programming of the switches may be accomplished using special purpose programming unit. However, this programming method is rather inconvenient for large CPLDs for two reasons, First, large CPLDs may have more than 200 pins on the chip package, and these p[ins are often fragile and easily bent. Second, to be programmed in programming unit, a socket is required to hold the chip. Sockets for large QFP packages are very expensive; They sometimes cost more than the CPLD device itself. For these reasons, CPLD devices usually support the ISP technique. A small connected is include d on the PCB that houses the CPLD, and a cable is connected between that connector and a computer system. The CPLD is programmed by transferring the programming information generated by a CAD system through the cable, form the computer into the CPLD. The circuitry on the CPLD a that allows this type of programming has been standardized by the IEEE and is usually called a JTAG port. It uses four ries to transfer information between the computer and the device being programmed. The term JTAG stands for JOINT TEST ACTION GROUP . once a CPLD is programmed , it retains the programmed state permanently, even when the power supply for the chip is turned off. This property is called nonvolatile programming.

Fig: 10: A section of the CPLD for the fig 9. CPLDs are used for the implementation of many types of digital circuits. In industrial designs that employ some type of PLD device, CPLDs are used in about half the cases. A number of companies offer competing CPLDs. Field Programmable Gate arrays. The types of chips described in 7400, series, and CPLDs, are useful for implementation of a wide range of logic circuits. Except for CPLDs, these devices are rather small and are suitable only for relatively simple applications. Even for CPLDs, only moderately large circuits can be accommodated in a single

D Q

D Q

D Q

PAL- LINK BLOCK ( DETAILS NOT SHOWN )

PAL- LINK BLOCK

chip. For cost and performance reasons, it is prudent to implement a desired logic circuit using as few chips as possible, so the amount of circuitry on a given chip and its functional capability are important. One way to quantify a circuit's size is assume that the circuit is to be built using only simple logic gates and then estimate how many of these gates are needed. A common used measure is the total number of two-input NAND gates that would be needed to build the circuit; this measure is often called the number of equivalent gates. Using the equivalent gates metric, the size of a 7400 series chip is simple to measure because each chip contains only simple gates. For CPLDs the typical measure used is that each macro-cell represents about 20 equivalent gates. Thus a typical PAL that has eight; macro-cells can be accommodate a circuit that need up to about 160 gates, and a large CPLD that has 1000 macro-cells can implement circuits of up to about 20,000 equivalent gates. By modern standards, a logic circuit with 20,000 gates is quite small. To implement larger circuits, it is convenient to use a different type of chip that has a larger logic capacity. A FIELD PROGRAMMABLE GATE ARRAY (FPGA) is a programmable logic device that supports implementation of relatively large circuits. FPGAs are quite different from CPLDs and EPLDs because FPGA do not contain AND and OR planes. Instead, FPGAs provide logic blocks for implementation of the required functions. The general structure of an FPGA is illustrated in Fig 10. It contains three main types of resources: logic blocks, I/O blocks for connecting to the pins of the package, and interconnection wires and

I/O BLOCK

I/O BLOCK

I/O B

LOC

KI/O

BLO

CK

LOGIC BLOCK INTERCONNECTION SWITCHES

Fig: 11 General structure of an FPGA. switches. The logic blocks are arranged in a two-dimentional array, and the inter connection wires are organized as horizontal and vertical routing channels between rows and columns of logic blocks. The routing channels contain wires and programmable switches that allow the logic blocks to be interconnected in many ways. Fig 10 shows two locations for programmable switches, the boxes adjacent to logic blocks hold switches that connect the logic blocks input and output terminals to the interconnection wires, and the blue boxes that are diagonally between logic blocks to connect one interconnection wire to another ( such as vertical wire to a horizontal wire). Programmable connections also exist between the I/O blocks and the interconnection wires. The actual number of programmable switches and wires in an FPGA varies in commercially available chips. FPGA can be used to implement logic circuits of more than a few hundred thousand equivalent gates in size. Two examples of FPGAs, called XILINX

XC4000, VERTEX –series. SAPTRON and ALTERA FLEX 10 K series. FPGA s are available in a variety of packages including PLCC , QFP and PGA packages. A PGA package may have up to few hundred pins in total, which extend straight outward from the bottom of the package, in a grid pattern. Yet another packaging technology that has emerged is known as the ball grid array (BGA) . The BGA is similar to the PGA except that the pins are small round balls, instead of posts. The advantage of BGA package is that the pins are very small; hence more pins can be accommodated on the package. Each block in an FPGA typically has a small number of inputs and one output. A number of FPGA products are on the market, featuring different types of logic blocks. The most commonly used logic block is a look table (LUT), which contains storage cells that are used to implement a small logic function. Each cell is capable of holding a single logic value, either 0 or 1. The stored value is produced as the output of the storage cell. LUTs of various sizes may be created, where the size is defined by the number of inputs. Fig 3.36 shows the structure of a small LUT. It has two inputs x1 and x2, and one output f. It is capable of implementing any logic function of two variables. Because a two - variable truth table has four row, this LUT has four storage cells. One cells corresponds to the output value in each row of the truth table. The input variables x1 and x2 are used as the select inputs of three multiplexers, which, depending on the valuation of x1 and x2, select the content of one of the four storage cells as the output of the LUT. To see how a logic function can be realized in the two 0 input LUT, consider the truth table in FIG 12b. The function f1 from this table can be stored in the LUT as illustrated in fig.12c. the arrangement of multiplexers in the LUT correctly realizes the function f1. When x1 = x2 = 0, the output of the LUT is driven by the top storage cell, which represents the entry in the truth table for x1x2 = 00. Simillarly for all valuations of x1 and x2, the logic value stored in the storage cell corresponding to the entry in the truth table chosen by the particular valuation appears on the LUT output. Providing access to the contents of storage cells is only one way in which multiplexers can be used to implement logic functions. Fig 13 shows a three-input LUT. It has eight storage cells because a three- variable truth table has eight rows. In commercial FPGA chips , LUTs usually have either four or five inputs, which require 16 and 32 storage cells, respectively. In fig 7 we showed that PALs usually have extra circuitry included with their AND-OR gates. The same is true for FPGAs, which usual have extra circuitry, besides a LUT, in each logic block. Fig 3.38 shows how a flip flop may be included in an FPGA LOGIC block. As mentioned for fig 3.29 the flip flop is used to store the value of its D input under control of its clock input. For logic circuit to be realized in an FPGA, each logic function in the circuit must be small enough to fit within a single logic blocks.

O/I

O/I

O/I

O/I

x1

x2

f

x1 x1 f0 0 10 1 01 0 0

1 1 1

fig: 12(b) f1 = (!x1)(!x2) + x1x2

fig: 12(a) circuit for a two-inputLUT

1

0

0

1

x1

x2

f1

fig: 12(c) Storage cell in theLUT

O/I

O/I

O/I

O/I

O/I

O/I

O/I

O/I

X1X2

X3

f

Fig13: A three Input LUT.

LUT D Q

CLK

IN1

IN2

IN3

SELECT

OUT

FLIP-FLOP

Fig: 14. Inclusion of a Flip – flop in an FPGA logic Block

0001

0100

0111

X3 f

X1

X2

f2

f

f1

X1

X2

X2

X3

f1

f2

Fig: 15: A section of a programmed FPGA.

In practice, a user's circuit is automatically in to the required from by using CAD tools When a circuit is implemented in an FPGA, the logic blocks are programmed to realize the necessary functions and the routing channels, are programmed to make the required interconnections between logic blocks. FPGA S are configured by using the ISP method. The storage cells in the LUTs in an FPGA are volatile, which means that they lose their stored contents whenever the power supply for the chip is turned off.. Hence the FPGA has to be programmed every time power is applied. which means the bit map file(data) ( the output file from the CAD TOOL ) will be placed in the serial prom (SPROM) or in parallel prom which is included on the circuit board that houses the FPGA will down load the bit map file to the FPGA after power on reset and also one can down load the same using JTAG cable. What every may be the method the storage cells in the FPGA are loaded automatically form the above said devices

when power is applied to the chips. A small FPGA that has been programmed to implement a circuit is depicted in fig 3.39. The FPGA has two -input LUTS and there are four wires in each routing channel. The figure shows the programmed states of both the logic blocks and wiring switches in a section of the FPGA, programmable wiring switches are indicated by an X. each switch shown in blue is turned on and makes a connection between a horizontal and vertical wire. The switches shown in black are turned off, these switches are designed using the transistors which witch on for contact and off con non contact. The truth tables programmed in to the logic blocks in the top row of the FPGA correspond to the functions f1 = x1x2 and f2 = (!x1) x3. The logic block in the bottom right of the figure is programmed to produce f = f1 + f2 = x1x2 + (!x2) x3.

CUSTOM CHIPS, STANDARD CELLS, AND GATE ARRAYS. The key factor that limits the size of a circuit that can be accommodated in a PLD is the existence of programmable switches. Although these switches provide the benefit of user programmability, they consume a significant amount of space on the chip. They also result in a reduction in the speed of operation of circuits. In this section we will introduce some integrated circuit technologies that do not contain programmable switches. Chips that provide the largest number of logic gates and the highest speed are called custom-chips. Whereas a PLD is prefabricated, containing logic gates and programmable switches that are programmed to realize a user's circuit, a custom chip is created from scratch. The designer of a custom chip has complete flexibility to decide the size of the chip, the number of transistors the chip contains, the placement of each transistor on the chip, and the way the transistors are connected together. The process of defining exactly where on the chi each transistor and wire is situated is called chip layout. For a custom chip the designer may create any layout that is desired. Because it may contain more than a million transistors, a custom chip requires a large amount of design effort and therefore is expensive. Consequently, custom chips are used only when a very large number of transistors is needed and high-speed performance is important. Also, m the product being designed must be expected to sell in sufficient quantities to recoup the expense. Two examples of products that are usually realized with custom chips are microprocessors and memory chips. Some of the design effort incurred for a custom chip can be avoided by using a technology known as standard cells. Chips made using this technology are often called applications specific integrated circuits (ASICs). This technology is shown in fig 3.40 which depicts a small portion of a chip., The rows of logic gates may be connected by wires that are created in the routing channels between the rows of gates. In general, many types of logic gates may be used in such a chip. the available gates are pre built and are stored in a library that can be accessed by the designer. In fig 3.40 the wires are drawn in tow colors. This scheme is used because metal wires can be created on integrated circuits in multiple layers, which makes it possible for two wires to cross one another without creating different layer. Each light colour wires represent a hard wired connection (Called via) between a wire on one layer and a wire on the other layer. In current

technology it is possible to have eight or more layers of metal wiring. Some of the metal layers can be placed on top of the transistors in the logic gates, resulting in a more efficient chip layout. Like a custom chip, a standard cell chip us created from scratch according to a user's specifications. The circuitry shown in fig 3.40 implements the two logic functions that we realized in a PLA in fig 3.26, namely f1 = x1x2+x1(!x3)+(!x1)(!x2) x3 and f2 = x1x2 + (!x1)(!x2)x3 + x1x3. Because of the expense involved a standard cell chip would never be created for a small circuit such as this one, and thus the figure shows only a portion of a much larger chip. The layout of individual gates (standard cells) is pre designed and fixed. The chip layout can be created automatically by CAD tools because of the regular arrangement of the logic gates (cells) in rows. A typical chip has many long rows of logic gates with a large number of wires between each pair of rows. The I/O blocks around the periphery connect to the pins of the chip package, which is usually a QFP, PGA, or BGA package.

X1

X2

X3

f1

f2

Fig: 16 A section of two rows in a standard cell chip. Another technology, similar to standard cells, is the gate-array technology, Ina gate array parts of the chip are prefabricated, and other parts are custom fabricated for a particular user's circuit. This concept exploits the fact the integrated circuits are fabricated in a sequence of steps, some steps to create transistors and other steps to crate wires to connect the transistors together. In gate-array technology, the manufacturer performs most of the fabrication steps, typically those involved in the creation of the transistors, without considering the requirements of a user's circuit. This process results in a silicon wafer of partially finished chips, called the gate array template. Later the template is modified, usually by fabricating wires that connect the transistors together, to crate a user's circuit in each finished chip. The gate-array approach provides cost savings in comparison to the custom-chip approach provides cost savings in a comparison to the custom-chip approach because the gate-array manufacturer can amortize the cost of the chip fabrication over a large number of template wafers, all of which are identical. Many variants of gate-array technology exist. Some have relatively large cells which others are configurable at the level of a single transistor. An example of a gate-array template is given in fig 3.41. The gate array contain a two-dimentional array of logic cells. The chip's general structure is similar to a standard cell chip except that in the gate array all logic cells are identical. Although the types of logic cells used in gate arrays vary, one common example is a two or three input NAND gates. In some gate arrays empty spaces exist

between the rows of logic cells to accommodate the wires that will be added later to connect the logic cells together.

Fig 17 : A sea – of – gates gate array. However, most gate arrays do not have spaces between rows of logic cells, and the interconnection wires are fabricated on top of the logic cells. This design is possible because, as discussed for fig 3.40 metal wires can be created on a chip in multiple layers. This technology is known as the sea-of -gates. Fig 3.42 depicts a small section of a gate array that has been customized to implement the logic function f = x2(!x3) + x1 x3. It is easy to verify that this circuit with only NAND gates is equivalent to the AND-OR form of the circuit.

f1

X 1

X 2

X 3

Fig 18 : The logic function f1 = x2(!x3) + x1 x3 in the gate array of

STANDARD CELLAREA 1

2

4

3

5

FIXEDBLOCKS

STANDARD CELL BASED ASIC

CHANNELED GATE ARRAY

BASE CELL

fig: 19 standard cell based ASIC and CHANNELED GATE ARRAY.

ARCHITECTURES: Configuration of FPLD s is achieved by either EPROM technology,. antifuse or embedded register. EPROM and embedded register are erasable, while the antifuse approach is one time programmable. Iot is assumed that readers are familiar with the EPROM based approach from consideration of simple PLDS, Three series of devices, namely actel ACT, crosspoint solutions cp20k AND QUICKLOGIC pasic, USE PROPRIETARY ANTIFUSE TECHNOLOGU. A SCHEMATIC CROSs-section through such an antifuse is shown fig. Basically a

voltage sensitive material is sandwiched between two conductors. In the case of actel the antifuse, called a plice, comprises a dielectric sandwiched between n+

diffusion and polysilicon. quicklogic place programmable silicon in the vias between metal layers of an otherwise standard COMS process. In both column approach. As a measure of the complexity of the approach, the largest ACTEL DEVICE contains about 750000 anti-fuses. The embedded register configuration technique is common referred to as embedded RAM. This description is avoided in the present surveys as, currently, there are no commercial devices available that offer random access to the configuring bits. All of the devices that are based on an embedded register introduce the configuration data using shift registers, which, by its nature is a serial process. There are three common architecatural styles and these are referred to here as

INTER

CONNECT

LOGICBLOCK

LOGICBLOCK

LOGICBLOCK

LOGICBLOCK

LOGICBLOCK

LOGICBLOCK

LOGICBLOCK

LOGICBLOCK

LOGICBLOCK

LOGICBLOCK

LOGICBLOCK

LOGICBLOCK

I/O PADS

Fig20: Red square architecrture

Fig 21: Manhattern architectures

I/O PADS

Fig 22 Terraaced architecrture

I/O PADS

RED SQUARE, TERRACED and MANHATTEN, as shown in fig:20,21 and 22. All of the complex PLD s emplloy RED SQUARE architectures. These are charactrised byu a small number of large logic blocks surrounding an expanse of fast, direct interconnect. In contrast, all of thee FPGAs based on embedded registers employ a Manhatten architecture. Terraced architecture are employed in one-shot FPTA (OTP) devices from Actel and Crosspoint. FPGA devices conventionally employ small cells that are connected by sophisticatd, and often fragmented, routing rources. Granularity is an issue that attracts considerable debate. Manufactures of complex PLDs , having relatively course ( big) blocks, argue that the simple and direct routing that is possible between a relatively small number of large logic blocks is fast and predictable. It also imposes minimal demands on automatic layout tools and therefore successful routing is achieved by modest tools in only a short time. This is in contrast to the situation that is encountered for the complex and fragmented interconnection resourses that are necessary for fine-grained architectures. Also, the high functionality of large blocks ensures that most functions can be realized in two levels of logic,. And this provides a performance advantage. In addition the large blocks can have direct access to I/O resouress. Alternatively, the vendors of FPGAs, characterized by many fine-grained blocks, argue that they offer higher logic densities and better utilization of the avoidable resources. In addition, small blocks are preferable for implementing register intensive designs and therefore offer improved flexibility. Some of the more recent FPGA architectures, notably ALTERA FLEX AND AT&T Orca, address these conflicting requirements by providing hybrid logic blocks having a mixed medium/course grained nature. Clearly there is no consensus of opinion and one technology will not be the most appropriate for all applications. Figure 5 depicts part of a Manhatten architecture with programmable connections between intersection tracks. In commercial devices, programming of such a device may be achieved using ant-fuse or embedded register devices. The origin of the fragmentation that is claimed to be typical of such an approach can be appreciated by consideration of the example track between logic blocks (shown in bold) . This track has to traverse a umber of intersections and change direction six times. Clearly, for complex designs this presents a considerable challenge compared to the more straightforward connections encountered in complex PLDs. For devices based on embedded registers the switching is achieved using MOSFETS, as shown in the inset, and considerable delays can result if several switches are included in one path. The ‘m’ represents a bit, stored in the embedded register, that is used to turn the MOSFET ‘on’ or ‘off’. It is worth nothing that, while terraced architectures are preeminent in mast programmable gate arrays, the Manhattan architecture provides more routing channels at the expense of logic blocks and this assists automated layout. Considering the similar constrains it is somewhat surprising that FPGAs have not inherited the strong preference for Terraced architectures that is evident for MPGAs.

EVALUATION: In attempting to identify, firstly, the suitability of FPLDs, for a given application and, secondly the most appropriate technology, the reader may find it worthwhile to consider the following criteria: Cost of involvement. In particular how much are the supporting CAD tools and programming hardware likely to cost? Cost of devices. There is little point, in a survey such as this, in suggesting prices for specific components. The nature of the industry dictates that prices are extremely dynamic and may alter by significant amounts, especially during the early stages of availability. Clearly, in order to compete a device that offers certain logic equivalence must be comparable in price to its competitors if it is to survive. A rough guide to present prices suggest that 1000 equivalent gates cost from £5 to £20 and £5000 from £50 to £150, for mature products. New products are usually relatively expensive. Logic complexcity. How many ‘equivalent gates’ are included on a chip? What exactly is and equivalent gate? What proportion of these can realistically be utilized in a design? Speed: Vendors often quote toggle rates, but how does this compare to likely system speeds? The technologies based on embedded registers should be carefully scrutinized. As configured interconnect paths may include several active switches, each with a considerable associated delay, the overall system speed may be significantly less that the quoted toggle rate.

References: A Survey of FPGA architectures of programmable logic devices" By: Trevor A york. Published inMicro processors and Micro computers vol17 no 7 September 1993 . Fundamentals of DIGITAL LOGIC with VHDL DESIGN By Stephen Brown and Zvonko Vranesic Mc Graw Hill Publications. Xilinx Data Book 2000. Data Book of Altera Data Book of ACTEL.