NoiseInDeepSubU Shepard

8/11/2019 NoiseInDeepSubU Shepard

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Noise in Deep Submicron Digital Design

Kenneth L. Shepard and Vinod NarayananIBM T. J. Watson Research Center

Yorktown Heights, NY 10598

AbstractA s t e chno logy sca l e s i n to t he deep submic ron reg ime ,n o i s e i m m u n i t y i s b e c o m i n g a m e t r i c o f c o m p a r a b l ei m p o r t a n c e t o a r e a , timing, a n d p o w e r f o r t h e a n a ly -s i s a n d d e s i g n o f VLSI s y s t e m s . T h i s p a p e r d e f i n esn o i s e a s it p e r t a i n s t o d i g i t a l s y s t e m s a n d a d d r e s s e st h e t e c h n o l o g y t r e n d s w h i c h a r e b r i n g i n g n o i s e i s s u e st o t h e f o r e f r o n t . T h e n o i se s o u r c e s w h i c h a re p la g u -ing dig i t a l sys t em s a re ezp l a ined . A m e t r i c r ef e rr e d t oa s no i se s t ab i l i t y i s de fined , and a s t a t i c no i se ana ly -s i s m e t h o d o l o g y b as ed o n t h i s m e t r i c i s i n t roduced t odem ons t ra t e ho w no i se can be ana lyzed sys t ema t i ca l l y .A n a l y s i s i s s u e s a s s oc i at e d w i t h o n - c h i p i n t e r c o n n e c ta re a l so cons ide red . Th i s pape r conc ludes with a dis-c u s s i o n of t he dev ice , c i r cu i t , l ayou t , and logi c de s igni ssu es a ssoc i a ted w i th no i se .

1 IntroductionNoise immuni ty has always been a metric of interest inanalog circuit design where the noise sources of princi-pal concern are those associated with physical effects

shot noise, thermal noise, flicker noise, and burstnoise[l]. In contrast, the pervasiveness of digital sys-tems is in great part due to their inherent noise im-munity. Digital circuits use a range of analog voltagesto define a logic 1 and logic O where degradation ofthese voltages due to noise would cause them to fallou t of the valid ranges. High-gain logic gates, the bestexamples being CMOS inverters, restore these logicvalues by means of nonlinear voltage transfer charac-teristics which significantly reduce noise near the highan d low voltage rails[2]. These gates are usually re-ferred to as restor ing logic ga tes.

The high gain of digital circuits, however, resultsin new man-made noise sources, which can be sev-eral orders of magnitude greater t han t hose associatedwith th e physical silicon devices. Thi s first became aproblem in the context of mixed digital-analog ICsin which the noisy digital circuits could strongly in-fluence th e noise-sensitive anal og ones[3]. Wi th thecontinued scaling of CMOS technology and with per-formance requirements which are driving designs inthe direction of more noise-sensitive dynamic circuits,man-made noise sources are becoming an issue evenin purely digital designs. In modern CMOS processes,more levels of interconnect > 6 levels) are beingpacked closer together (minimum spacing < 0.3 p m ) ,increasing the amount of capacitive coupling betweennets. To maintain drive strength in th e face of scaled-down power supply voltages, threshold voltages are

1063-6757/96 5.00 0 1996 IEEE

also scaled lower. Lower threshold voltages result inlower noise margins an d increased leakage noise. Noisein deep submicron digital circuits must now be ana-lyzed and designed as a metric of comparable impor-tance to area, timing, and power.

2 Noise in deep submicron digital de-signs

2.1 What is noise?We begin this discussion with a few useful definitions.An e v a l u a t i o n n o d e is a circuit node that forms theconnection between channel connected components inthe design. Pass transistors are one exception to t hisrule, in that it is useful to treat both the source anddrain as evaluation nodes. S t a t i c e v a l u a t i o n n o d e sare evaluation nodes which always have a conductingpath to power or ground. S t a t i c c i r c u i t s are circuitsin which all evaluation nodes are static. Th e imped-ance which holds an evaluation node high or low is re-ferred to as the n o d e i m p e d a n ce . D y n a m i c e v a l u a t i o nn o d e s are evaluation nodes that during some part ofnormal system operation are disconnected from powerand ground; that is, they have an infinite node imped-ance and a logic value determined by a charge storedon a capacitor. D y n a m i c c i r c u i t s are circuits which

contain dynamic evaluation nodes.N o i s e can be defined as anything that causes thevoltage of an evaluation node t o deviate from t he nom-inal supply or ground rails when it should otherwisehave a stable high or low value (i.e., the node is notswitching) as determined by the logic and delay of t hecircuit.

Noise can be characterized by its peak magnituderelative to the nominal supply and ground rails andits behavior in the time-domain. Noise sources th atreduce an evaluation node voltage below the supplylevel (VDD) are denoted V H , while noise sources thatincrease an evaluation node voltage above the groundlevel (GND) are denoted VL. Noise may also be boot-strapping if it increases node voltage above the supply level V**) or below the ground level VL.). Forthe purposes of determining how circuits respond tonoise, one can abstract time-domain response i nto oneof two categories D C noise and pulse noise as shownin Figure 1. These two noise behaviors are discussedin detail in the context of noise sources in Section 2.2.Pulse noise on an otherwise high logic level is, for ex-ample, denoted as V F l s e while DC noise on an other-wise high logic level is denoted as Vgc.

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DD .................................. _____c ..............................................................a) 1 f v u

................. _____.............- Pul= vVDD t HFigure 1: Tim e domain abstractions for noise: (a) DCnoise and (b) pulse noise

2.2 Noise sources in digital systems

The noise sciurces most relevant to digital designare leakage nIDise, power supply noise, charge-sharingnoise, and crosstalk noise.

2.2.1 Leakage noise

Leakage noise is generally applied to the context ofdynamic nodes and comes from two sources. There isleakage noise due to the off current of FETs, whichallows charge. to drain from or accumulate on thedynamic node. This is largely due to subthresholdcurrent and is directly determined by the thresholdvoltage an d the temperature, Another leakage noisesource is mi nority carrier back-injection i nto the sub-strate due to bootstrapping. This is sometimes re-ferred to as substrate noise in the context of mixedanalog-digital. ICs[4]. One solution for substrate noiseis to introduce guard bands, n-type diffusions tiedto the supply voltage to collect the minority carrierelectrons[3, 51. Substrate noise becomes less of a prob-lem at scaled power supply voltages because of theneed to bootstrap more than - 0.6V and, therefore,is not considered in t he st ati c noise analysis methodol-ogy discussed in Section 3. Leakage noise can also beused in reference to static evaluation nodes, in whichthe "leakage" is ratioed against a static path holdingthe node in th e opposite direction. Leakage noise isa DC noise source because it changes the steady-statelogic high or low voltage value on a time scale whichis slowly varying wi th respect the th e system clock, atime scale which we refer to a s the phase time.

2.2.2 Charge-sharing noise and crosstalk

Charge-sharing noise is produced by charge redistrib-ution between a dynamic evaluation node and inter-nal nodes of the circuit. Figure 2(a) shows a circuitin which charge sharing noise is graphed under four

noise

conditions in Figure 2(b) .l In z), the charge shar-ing noise is calculated in the absence of a half-latchPFET device for All A2, A3, and A4 simultaneouslyswitching from low to high, while B1, B2, B3, and B4are low. ii) shows the same situation in the pres-ence of a half-latch. In iii), Al , A2, A3, and A4are assumed to be logically orthogonal (i. e., at mostone of these signals may be 1 at the same time), aBoolean satisfiability constraint that can be verifiedthrough binary-decision diagram techniques[7, 81, butno half-latch is used. In iv), logical orthogonality anda half-latch are assumed.

(bl

Figure 2: Charge sharing noise: (a) circuit and (b)dynamic node voltage

Crosstalk noise is the voltage induced on a node dueto capacitive coupling to a switching node of anothernet. Figure 3 shows the noise coupling onto three dif-ferent types of evaluation nodes from a single noisesource switching with a fall time of loops with simplecapacitive coupling.

2 4 cy

111 0 0.5 10 3 211

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Figure 3: Coupling noise calculated for three circuittopologies (a) Pass transistor (b) Two inverters (c)Dynamic node of domino stage

Both crosstalk and charge-sharing noise are pulsenoise sources, in which the leading edge is determinedby a switching signal on the chip and t he t railing edgeis determined by the node impedance charging or dis-charing the capacitance of the evaluation node. Thetime constant of this response is referred to as therestoring time constant, since it is the time it takesthe node to be restored t o its static value. For dy-namic nodes, as in cases iii) and i) of Figure 2, this

The simulations shown in this paper are performed in a0 . 5 ~ ~ 7 1M OS process described in detail elsewhere [SI.

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ti me const ant is infinite (i.e., t he node never recovers).For static paths that drive through pass gates, as inFigure 3(a), this time constant can be very long.

2.2.3 Power supply noise

Power supply noise explicitly refers to noise appearingon the supply and ground nets of the chip and cou-pled ont o evaluation nodes through a FE T conductionpath. Figure 4 shows the actual supply variation asmeasured on a fourth-level metal sense point near theon-chip cache of a CMOS microprocessor running ata clock period of 7 nsec. Power supply noise contains

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both a DC and sinusoidal content. Th e DC compo-nent of power supply noise is produced by the IR dropthrough the power and ground nets due to the aver-age current d emands over the chip. The DC compo-nent of power supply noise can be reduced through adenser or wider interconnect structure for the poweran d ground network. Th e sinusoidal component ofpower supply noise comes from the RLC response ofthe chip and package to current demands that peakat th e beginning of the clock cycle. In addition to si-nusoidal variation, a sharply peaked current demandmay also produce higher frequency components, whichcan be largely suppressed by the use or placement ofon-chip decoupling capacitors[9]. In Figure 4 here issome higher frequency content around 1 GHz. Sincepower supply variations vary slowly relative to circuitfrequency response, they are generally treated as DCfor analysis purposes.

2.3 How do we know when the system willfunction?

The fundamental goal of a conservative noise analysismethodology is to guarantee that on every evaluationnode n the circuit, the correct 1 or 0 value is definedby voltages that fall within one of two valid ranges forall times that a stable high or low logic value shouldbe present as determined by the logic and delay ofth e circuit. For dynamic evaluation nodes, this goal isessential since no static path exists to restore the cor-rect logic st at e in the case of noise. I t is also essentialfor many bistable circuits. One example of this wouldbe VL* oupling noise feeding the pass gate of a latchin which the gate of the pass gate is 0 and the latch

stores a 1. If TIL* exceeds the threshold voltage of th eNFET of the pass gate, the latch can be drained andflipped to a 0 without a chance for recovery. Sta-tic evaluation nodes in the absence of feedback will,in general, recover from pulse noise if one waits for arestoring time constant to elapse; however, the stabil-ity of logic signals due to noise is not something thatis practical to manage in predicting performance and

cycle time.One way to ensure functionality for static CMOSlogic gates is to define DC noise margins, N M L andN M H such that the bistable circuits shown in Figure5 do not switch and NMH + N M L is maximum[lO].This corresponds to biasing each gate at the unitygain point in its DC voltage transfer characteristic.For noise V < NM H and VL < N M L , gates will al-ways be biased into regions of their voltage transfercharacteristics in which noise is attenuated.

Figure 5: Latch circuits which define DC noise mar-gins for CMOS NOR, NAND, and NOT gates.

DC noise margins are much too conservative to ap-ply against the magnitude of pulse noise sources, be-cause they fail to consider the fact that logic gatesact as low-pass filters. N o i s e t o l e r a n c e is a general-ized view of noise margi ns applied to triangul ar pulsednoise sources, in which different noise margins are cal-culated for different pulse amplitudes and widths[l l].

In order to handle nonrestoring logic gates, such aspass transistors, and provide more precision in han-dling pulse noise and bootstrap noise sources, one canfurther generalize the idea of noise tolerance, whichapplies to an individual logic gate, to the concept ofnoise s tabi l i ty which applies to the entire digital cir-cuit. Consider th e case in which noise is present o nevery evaluation node juxtapo sed in ti me in the worstallowable way. T he worst possible magni tude at whichnoise can exist in the circuit defines a bias point. Atthis bias point, t he circuit is defined to be noise stableif for any one noise source, a small change in its am -plitude of c ~ Kesults in a noise amplitude change on

any evaluate node of 6 6 such that 16vj/SK < 1 withi, E { L ,H , L * ,H * } .2 .4 Noise and delayAs an aside, capacitive coupling and power supplyvariations can also have a direct effect on delay thatmust also be considered independent of this noiseanalysis. Leakage noise and power supply noise re-sult in lower or higher supply levels, which reduce

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or enhance the current drive of a circuit and conse-quently increase or decrease the delay. Coupling noisecan cause the effective line capacitance to increase ordecrease in the presence of simultaneously switchingnoisy lines, increasing or decreasing the delay.

3 Static noise analysisIn this section, we briefly introduce a static noiseanalysis methodology, called H a r m o n y, which en-forces circuit stability. Details will be presentedelsewhere[l2]. Dynamic simulation is not feasible forchecking noise on designs with tens of millions of tran-sistors. Instead , as with timing, stat ic analysis tech-niques which couple simulations on small numbers oftransistors (basically individual gates) with a pathtrace are used. Worst-case preconditioning assump-tions and (in most cases) worst-case temporal rela-tionships drive the simulations. At the same time,global interconnect is handled with more sophistica-tion than local circuit interconnect in determiningthe magn itude of coupling noise. Analysis is based onconstructing a noise graph abstraction, which followsvery closely 1,he timing graphs used in s tatic timinganalysis[l3]. As in the case of stati c timing analysisin which waveforms are abstracted as saturate ramps,the actual dynamic waveforms ar e simplified to pulseor DC waveshapes. In the case of precharged logic,only noise against the reset state is considered sincethis is th e transition th at contains the logical informa-tion of the ciIcuit. Power supply noise is also assumedto be characterized by a DC value.

3.1 Constructing a noise graphThe steps t o constructing a noise graph from a circuitare outlined below.

3.1.1 Evaluation node identification and di-rection setting

The evaluation nodes in the circuit are identified. Ba-sic topologies; are recognized - restoring logic stages,domino logic stages, simple inverter feedbacks, weakpullups, and pass transistor stages. Evaluation nodeswhich are precharged in dynamic logic stages are iden-tified as precharge evaluat ion nodes . These nodes po-tentially require charge-sharing noise calculation asdiscussed in Section 3.1.3. Transistor directions are setusing the simple rules-based approach of Jouppi[ 141.This is of principal concern for pass gates. Feedbacksare recognized so that they can be independently pre-conditioned. Floating capacitors are broken and tiedto ground w:hen connected to any nodes other thanevaluation nodes (i.e., coupling is only considered toevaluation nodes). This is not a significant source oferror since evaluation nodes will be the only nodeswith significant interconnection length. Nodes whichfeed NFET pass transistors are identified as bootstrap-d o w n e v a l u a t i o n n o d e s ,since they will be sensitive toV p while nodes which feed PFET pass transistors areidentified as boo ts t rap -up e va lua t ion n odes since theywill be sensitive to V .

3.1.2 Calculate the coupling noise and restor-ing time constants for each evaluationnode in the circuit

For wire lengths less than lmm, we ignore resis-tance. In addition, all signals coupled to the givenevaluation node are assumed to switch simultaneouslyat a minimum slew time (t;:,). In Section 4, weshow how these assumptions are relaxed in the caseof long interconnect. Sta tic pat hs ar e preconditionedto keep the evaluation nodes quiet against the noisesource, including feedback paths. All pass transistorsare configured off except that configuration which pro-duces the highest stat ic resistance to supply or groundto produce worst-case coupling noise on the node inquestion. VH and Vh due to coupling are calculatedat each evaluation node, except precharge evaluationnodes, for which only VH or VL s calculated, depend-ing on whether the node is precharge high or low. Forbootstrap-down evaluation nodes, VL s also calcu-lated while for bootstrap-up evalaution nodes, VH-is calculated. Each coupling noise waveshape is ab-stracted as a pulse waveform with a leading edge deter-mined by a maximum slew time (t;::) and a trailingedge determined by a restoring time constant. Figure3 shows the typical results of such a simulation.

3.1.3 Charge sharing noise is calculated on allprecharge evaluation nodes

Charge-sharing noise is calculated for all prechargeevaluate nodes identified topologically. In every stackconnected to the precharge evaluate node, the t op de-vice and bottom device are configured off. All otherdevices in the leg of the NFET s tack are on. Thetop devices are then switched simultaneously for par-allel stacks. In the presence of an evaluate NFE T footdevice in the domino NFET stack, the foot device isconsidered on. Logic constra ints can be used t o reduce

pessimism as shown in Figure 2. Th e charge sharingand coupling noise are summed t o determine the totalpulse noise on the evaluation node.

3.1.4 Draw the directed segmen ts connec tingevalution nodes in th e noise graph

Now that the evaluation nodes and pulse noise sourceson each of these nodes is defined, the next step is toconnect the nodes by directed segments according tothe circuit structure to define the noise graph.

There are two basic types of segments in a noisegraph a res to r ing segment and a propaga te segment.A res to r ing segment connects evaluation nodes in thecase that the DC transfer characteristic shows gain.Restoring segments are identified by dashed lines andconnect inputs and ou tpu ts of restoring logic gates. Apropagate segment is one which propagates noise fromone evaluation node to another without gain. Chan-nel conduction in a pass gate, for example, is repre-sented by a propagate segment. Propagate segmentsare denoted by solid lines. Both types of segments arelabelled by noise type. A power-supply noise segmentis a special propagate segment in which the source

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node is ground or supply. Th e power supply noise ispropagated as VL from ground and VH from supply.For bootstrap-up nodes, V* is also propagated fromsupply and V p from ground. Figure 6 shows an ex-ample of a noise graph, in th is case for a lat ch drivinga domino gate.

-

Figure 6: (a) Circuit and (b) noise graph for a latchdriving a domino stage

3.2 Propagat ing noise through a graph

Once the noise graph is constructed, it is searchedin a breadth-first fashion to propagate noise throughthe network and, in the case of restoring segments, toperform the sensitivity tests required to ensure noisestability.

search

3.2.1 Propagate segments

On each propagate segment , the peak output voltagewaveform is calculated for the DC noise and pulsenoise appearing on the inpu t. This peak voltage ispropagated as DC noise onto the output evaluationnode; therefore, the DC noise appearing on the in-put is that propagated from previous stages as well astha t introduced as power supply noise. This assump-tion introduces pessimism into the analysis but elim-inates the need to propagate time-domain responsewhile taking into account the low-pass filter charac-teristics of logic gates.

3.2.2 Restoring segm ents

For restoring logic, there will, in general, be multipleinputs entering t he same stage. A set of inputs form anoise equivalence class when the worst-case responseat the out put is produced when those i nput s are simul-taneously excited by noise. This allows us t o perform aworst-case analysis for noise without knowledge of therelative timing of noise events. Two distinct types ofsimulations are performed for restoring logic segments.

The first is a simulation to check stabili ty and the sec-ond, performed conditionally based on the results ofthe first, propagates noise to t he output . In both sim-ulations, for a given input and given noise type, VH orV other conduction paths in parallel with the one inquestion are preconditioned on except for the tr an-sistor closest to th e evaluate node, which will be noiseequivalent to the inp ut under test. Feedback pat hs

are also preconditioned to hold t he node at the staticlevel during both simulations.The first simulation checks the condition of noise

stability, which must be done for restoring logic stagessince they have gain. Let i denote different inputs ofa noise equivalence class. Let V,); denote the DCvoltage on input i, let Vr l s e ) i enote the pulse volt-age appearing on input i, and let V, be the outputvoltage, then for all equivalence classes, for all i in anequivalence class,

where p , v E { L ,H , . This is a sufficient con-conditions localizes the global stability definition ofSection 2.3 to a n effective stability analysis on a singlestage by requiring subunity sensitivity in magnitudeagainst all the noise propagated from previous stages.The derivatives are evaluated at the bias point de-termined by the noise appearing on the inputs of theequivalence class. These sensitivities can be readilycalculated in certain timing simulators in the time-domain by the direct or adjoint methods[l5, 161. Inthe event of a violation, the noise and noise sensitivi-ties for all the inputs in the equivalence class contain-ing the violation are reported. The noise source (i nputand DC/pulse) of th e highest sensitivity is th e mostlikely candidate for repair.

For those equivalence classes which do have stabil-ity violations, a second simulat ion is performed similarto that performed for propagate segments in which theactual DC and pulse noise is simultaneo usly applied toeach input in the class to determine the out put noise.For those equivalence classes which are in violation,a recovery mechanism exists to provide a worst-casevoltage to propagate forward in the pat h search. Inthis simulation the same pulse is applied to each in-put in an equivalence class in the absense of a DCbias to determine th e outp ut voltage at the unity gainpoint. Thi s generally represents the most pessimisticoutput noise. Figure 7 hows the pulse transfer char-acteristic that would be calculated as part of thissimulation for an and-or-invert gate for one particularnoise equivalence class with a restoring time constantof Ins. The inset shows th e configuration used in eachcase. These look similar in their hysteretic behaviorto the AC transfer characteristics of Ref. 17.

dition to ensure circuit sta ility. The first of the two

3.2.3

A DC noise value and a pulse noise value are storedon each evaluation node during pat h traversal. When

Implied rules of the path trace

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static timing analysis.

P

Figure 7: Pulse transfer characteristic and-or-invertstatic CMOS gate for (a){Al, Bl} VL VH equiv-alence class and (b) {Al, A2} V -+ VL equivalenceclass

multiple restoring segments converge on a node, thepropagated noise is the worst of the converged seg-

ments. When multiple propagat e segments convergeon a node, t he noise sources are summed. When prop-agate and restoring segments converge on an evalua-tion node, the worst of the propagated output noisesfrom the restoring segments is added to t he sum of th epropagate segment noises.

4 Long interconnect analysisIn calculating coupling as in Section 3.1.2, we madetwo significant simplifying assumptions regarding in-terconnect tha t we could ignore resistance and th atwe could assume that all of the coupling sources weresimultaneously switching. In calculating the couplingnoise in long interconnect, resistance must be consid-ered. In additi on, coupling noise calculation on longinterconnect :s ne place where th e addition of timi nginformation to break temporal correlation can have abig effect on reducing pessimism in the analysis.

We define the primary net as the net on which wewish to calculate the noise at each receiver. The sec-ondary nets are those nets coupled to the primarynet. The re itre two possible network simplificationsthat can be used in long interconnect analysis, bothshown in Figure 8. Driver outputs are modeled asresistances and receiver inputs are modeled as ca-pacitances. These linear networks are easily ana-lyzed by moment-matching techniques such as AWEor PVL[18, l )]. Four poles are usually more th an ade-quat e to determine the response. In Figure 8(a onlythe resistance of the primary net is considered. &he re-sistances on the secondary nets are ignored. In Figure

8(b), the resistances on both primary and secondarynets is considered, which is more accurate since it con-siders RC delays in the secondary net. The couplingcapacitance between the secondary nets and other netsis assumed tc, be grounded.

In both cases, two types of analysis are possible -o n e that assumes worst c s e temporal correlation ofnoise sources and one that attempts to break tempo-ral correlation with the addition of information from

T

T-

i

Figure 8: Long interconnect analysis for (a) resis-tances only on th e pri mary net and ( b) for resistanceson both the primary and secondary nets

4.1 Worst-case temporal correlation of

In this case, each noise source is a voltage waveformwith a slew time t:::. The sources are applied oneat a time while the other sources are grounded andthe peak magnitudes are added at th e receiver. Thi sis equivalent to assuming that the noise voltage ar-rives at each coupling capacitor at the time requiredto produce the worst coupling at the quiet receiver.

4.2 Using static t iming analysis to breaktemporal correlation

In thi s case, we consider t he following addit ional in-formation from stat ic timi ng analysis early an d latemode arrival times and best case slews t : f w ) at eachSecondary net driver. Let the driver of secondary neti begin rising at time t ; . The problem is then to find

the times t , that fall within the valid early and latemode arrival time windows for each secondary net dri-ver that produce the highest peak coupling noise onthe given receiver. One can do this by calculating theresponse for each driver individually and determiningthe peak position at the quiet receiver. The peak po-

time t , skews. The worst-case combination tha t satis-fies the timi ng orthogonality constraints is selected.

noise sources

sition skews immediately translate back to the arrival

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4.3 InductanceWith the increasing use of wide, thick wires and thepotential introduction of copper interconnect, induc-tance is becoming a concern[20]. There are two condi-tions which must be met for inductance to be signifi-cant:

R < w C where R is the resistance per unitlength, C is the inductance per unit length, andw is the characteristic frequency, roughly deter-mined by the typical slew times (t,) by w = 27r/t,.

t, < 2t f, where tf is the time-of-flight given bytf = l i? where C is the capacitance per unitlength and 1 is the length of the line[21].

Even if these two conditions are satisfied, the farend response will behave like a distributed RC lineif RI > 2Z0, where 2 s the characteristic impedanceof the line, given by 2 = m . he complexity incalculating inductance is determining the current re-tu rn p ath . Roughly speaking, the current will return

through the path of minimumR

+ w C . For lowU

the return path will be the path of minimum resis-tance. In t he case of solder-ball flip-chip packaging inwhich supply and ground are introduced throughoutthe chip, this will be a return path through the packagefor most long interconnect runs, a path of very highinductance. As w increases, the current return willseek a lower inductance (and higher resistance) returnon chip. In most cases, it will find a return on a poweror ground bus but in the absence of adequate poweror ground distribution, current m ay return through asignal line.

Inductance in the global interconnect has two ef-fects on noise. At th e receivers of switching nets,inductive ringing may be a concern. For quiet netswithin actively switching environments, inductive cou-pling tends to worsen noise at the near end while re-ducing noise at the far end.

To ill ustr ate these points, five parallel lines on 2pmthick copper interconnect are analyzed as shown inFigure 9(a) . The lines are 3.6pm spaced 1.8pm apart.Line A is grounded and the current return path as-s u m e d for inductance calculations. Line E is activelyswitched while the other lines are held quiet by ac-tive drivers. Figure 9(b) shows the response a t thenear and far end of line E in the case of RC and RLCmodelling. There is ringing a t t he far end when induc-tan ce is considered. Figure 9(c) shows th e response atthe near and far end of line D. Including inductancein the analysis reduces the noise at the far end whileincreasing the noise at the n e r end.

5There are many design techniques that can be used toredu ce noise. Many of these techniques are enforced asrules early in the design process, while others must bemor e carefully traded off. Cer tai n circuit topologiescan be restricted because of their noise sensitivity. Inmany cases, NFET-only pass gates are disallowed be-cause of their sensitivity t o power supply noise. Pass

Design issues in reducing noise

Figure 9: (a) Example long interconnect structure,(b) response on the driver line, and c ) response onthe quiet line. Near end is dashed and far end is solid.

gates at the ends of long wires are almost always for-bidden because of their sensitivity to bootstrappingcoupling noise. In general, buffers and inverters canbe introduced to clean up noise at the receivers ofnoisy lines at the expense of additional delay. Charge-sharing noise can be controlled to a considerable ex-tent through the careful use of logic constraints as dis-cussed in Section 3.1.3 and demonstrated in Figure 2or through the addition of babysit devices to stat-ically hold internal nodes high or low as the cost ofadditional power.

Many device sizing techniques can be used to im-prove noise margins, almost always at the expense ofadditio nal delay. Half-latches can b e added or sizedup for dynamic nodes. Device lengths can be tun edup to increase thresholds and reduce leakage. Betaratios can be adjusted t o improve one noise mar gin atthe expense of the other.

To reduce coupling noise, th e spacing between wirescan be increased or signals can be alternately routedwith power or ground. These techniques have beenapplied to constraint-driven routing, primarily in thecontext of analog or mixed-signal ICs[22]. Sometimesit is sufficient to increase the driver strength to helphold the quiet line quiet, but this is less effective inlong wires because of resistive shielding. In some caseswhen coupling noise is accentuated by simultaneouslyswitching noise sources, buffers or inverters can beadded onto noisy nets as delay elements t o offset th eirswitching times. In other cases, coupling noise can bereduced by decreasing overall wire length by insert-ing a repeater. In extreme cases, differential buses orDCVS logic can be used.

6 ConclusionsIn this paper, we have defined noise and discussed

the noise sources relevant t o digita l systems. We havealso defined a metric, noise stability, for determin-ing design goodness and described a static analysis

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methodology for verifying a design against this metric.Special modeling issues associated with long intercon-nect were dixussed . Several future issues were notedin the course of the discussion.

7 AcknowledgementsThe authors gratefully acknowledge H. Smith and

D. Becker for helpful discussions about power supplynoise and for providing the da ta in Figure 4. The au-thors also acknowledge C. Visweswariah for a carefulreading of the paper.

ReferencesP. R. Gray and It G. Meyer, Analysis and De-sign of Analog Integrated Circuits, John Wiley andSons, 1984, Chapter 11.

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