NJIT ECE271 Dr. Serhiy LevkovChap 4-1 Topic 4 Field-Effect Transistors ECE 271 Electronic Circuits...

NJIT ECE271 Dr. Serhiy Levkov Chap 4-1

Topic 4Field-Effect Transistors

ECE 271

Electronic Circuits I


Chapter Goals

• Describe structure and operation of MOSFETs.• Define FET characteristics in operation regions of cutoff, triode and

saturation.• Develop mathematical models for i-v characteristics of MOSFETs.• Introduce graphical representations for output and transfer

characteristic descriptions of electron devices.• Define and contrast characteristics of enhancement-mode and

depletion-mode FETs.• Define symbols to represent FETs in circuit schematics.• Investigate circuits that bias transistors into different operating

regions.• Explore FET modeling in SPICE.


Intro (1)

• Solid state transistor is the main building block of microelectronics. • It performs two major functions used in electronic devices:


Intro (1)


- amplifications (in analog)


Intro (1)


- amplifications (in analog) - switching (in digital)


Intro (1)



• There are two basic types of solid state transistors: BJT (bipolar junction transistor) and FET (field effect transistor).


Intro (1)



• There are two basic types of solid state transistors: BJT (bipolar junction transistor) and FET (field effect transistor).

• FET: electric field is used to control the shape and the conductivity of the channel of one type charge carrier (p or n) in semiconductor device.

• They are also called unipolar to contrast their single-carrier-type operation with the dual-carrier-type operation of bipolar (junction) transistors (BJT).


Intro (1)



• There are two basic types of solid state transistors BJT (bipolar junction transistor) and FET (field effect transistor).

• FET: electric filed is used to control the shape and hence the conductivity of the channel of one type charge carrier (p or n) in semiconductor device.

• They are also called unipolar to contrast their single-carrier-type operation with the dual-carrier-type operation of bipolar (junction) transistors (BJT).

• FET can be of two major types MOSFET (metal oxide semiconductor field effect transistor (mostly used)), and JFET (junction field effect transistor).


Intro (2)

• Metal Oxide Semiconductor Field Effect device was first solid state device conceived (Lilienfield, 1928), however it took very long to develop a successful commercial application of such devices. The first successful device was fabricated in 1950, however the reliable commercial fabrication did not start until decade later.

• Today, the CMOS technology based on MOSFET is the dominant technology in electronics.


Intro (2)

• Metal Oxide Semiconductor Field Effect device was first solid state device conceived (Lilienfield, 1928), however it took very long to develop a successful commercial application of such devices. The first successful device was fabricated in 1950, however the reliable commercial fabrication did not start until decade later.

• Today, the CMOS technology based on MOSFET is the dominant technology in electronics.

• BJT devices were first introduced in 1948 and quickly became commercially available. The first IC with logic gates and operational amplifiers that appeared in early 1960s, were based on BJT technology. They are still widely used, particularly in applications requiring high speed and high precision.

• BJT device is based on pn-junction structure, while MOSFET is utilizing the MOS capacitor structure.

NJIT ECE271 Dr. Serhiy Levkov

Metal Oxide Semiconductor Field-Effect Transistors

(MOSFET)

Chap 4-11


MOS Capacitor Structure

• Metal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor.




• Consists of two electrodes and insulator in between.





• First electrode (Gate): low-resistivity material such as metal or polycrystalline silicon.






• Dielectric - Silicon dioxide: stable high-quality electrical insulator between gate and substrate.







• Second electrode (Substrate, Body): n- or p-type semiconductor.








• The semiconductor body has limited supply of holes and electrons, and substantial resistivity.








• The semiconductor body has limited supply of holes and electrons, and substantial resistivity.

The concentration of carriers being dependant on voltage, the capacitance of this structure therefore is a nonlinear function of voltage applied.


Substrate Conditions for Different Biases

• Accumulation : VG<<VTN

The majority carriers (holes) accumulate in a very thin layer below the negative gate (like in capacitor)

We consider the conditions of the semiconductor region (p-type) below the gate electrode under three different voltage bias: accumulation, depletion, inversion.

Those conditions are determined by VTN (0.5 - 2.0 V) the threshold voltage, at which the electron inversion layer is just starting to form.



• Accumulation : VG<<VTN , VG<0The majority carriers (holes) accumulate in a very thin layer below the negative gate (like in capacitor)

• Depletion: 0<VG<VTN The small positive charge of the gate wipe out the holes from the layer below (depletes free carriers) creative a negative charge of ionized atoms





• Accumulation : VG<<VTN

The majority carriers (holes) accumulate in a very thin layer below the negative gate (like in capacitor)

• Depletion: 0<VG<VTN The small positive charge of the gate wipe out the holes from the layer below (depletes free carriers) creative a negative charge of ionized atoms

• Inversion: VG>VTN The larger positive charge of the gate attracts electrons whose concentration in the very thin layer exceeds that of holes – inversion of p-type into n-type.




Low-frequency C-V Characteristics for MOS Capacitor on P-type Substrate

• MOS capacitance is non-linear function of voltage.

• Total capacitance in any region is dictated by the separation between capacitor plates.

• Total capacitance can be modeled as series combination of fixed oxide capacitance and voltage-dependent depletion layer capacitance.


NMOS Transistor: StructureA N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region.


NMOS Transistor: Structure

• 4 device terminals:

Gate(G)

A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region.




Gate(G)

Drain(D)





Gate(G)

Drain(D),

Source(S)





Gate(G)

Drain(D),

Source(S)

Body(B)





Gate(G)

Drain(D),

Source(S)

Body(B).• Source and drain regions form

pn junctions with substrate.





Gate(G)

Drain(D),

Source(S)


pn junctions with substrate.• vSB,= vS – vB , vDS = vD - vS and vGS

= vG - vS are typically nonnegative during normal operation.





Gate(G)

Drain(D),

Source(S)


pn junctions with substrate.• vSB,= vS – vB , vDS = vD - vS and vGS

= vG - vS are always positive during normal operation.

• vB <= vD and vB <= vS , to keep pn junctions reverse biased.



NMOS Transistor and Variable Resistor

• A transistor is a three (or four) terminal device, in which one terminal controls the voltage or current between other two terminals

• In certain way it is similar to a variable resistor, in which the movement of the middle terminal controls the voltage.

+

-

+

-


NMOS Transistor: Qualitative Behavior @ vDS =0

• VGS<<VTN (VGS <0): Two back to back reverse biased pn junctions btw S and D. Only small leakage current flows.




• VGS<VTN (VGS >0): Depletion region formed under gate merges with source and drain depletion regions. No current flows between source and drain.




• VGS<VTN (VGS >0): Depletion region formed under gate merges with source and drain depletion regions. No current flows between source and drain.

• VGS>VTN: Channel is formed between source and drain by electrons in inversion layer. If VDS>0, finite iD flows from drain to source.

• iB=0 and iG=0.


Since the induced inversion layer is formed by electrons, it’s called N-channel MOSFET.



NMOS Transistor: Triode Region

vDSi K v V vnD TNGS DS2

where

Kn= Kn’W/L – the gain factor

Kn’=mnCox’’ (A/V2)

Cox’’=ox/Tox

ox= oxide permittivity (F/cm)

Tox = oxide thickness (cm)

for 0 v v VTNDS GS

Applying a small vDS creates a flow of electrons in the induced inversion layer between source and drain - current iD (iD = iS , since iB=0 and iG=0).

This is the triode region (linear region, ohmic mode). MOSFET operates like a resistor, controlled by the gate voltage relative to both the source and drain voltages.

smallvDS


N-MOS Transistor: Triode Region(derivation of the source-drain current)

' ''( ) / cm for ,

where '' / oxide capacitance per area, oxide permittivity(F/cm), oxide thickness (cm)ox ox TN ox TN

ox ox ox ox ox

Q W C v V C v V

C T T

Since currents iB and iG both are zero, and there is no path for drain current to escape: iS = iD.

To find it, we consider the transport of the charge. The linear density of the electron charge at any point in the channel is:

dx

xdvEx

)(

dx

xdvVxvvWCxi TNGSoxn

)()('')(

22" DS

TNGSnDSDS

TNGSoxnD

vVvKv

vVv

L

WCi

The voltage vox is the function of position x in the channel: . For inversion layer to exist, should be vox > VTN , so Q’ = 0 until vox > VTN . At the source, vox = vGS and it decrease to vox = vGS - vDS at the drain.

The electron drift current is : , where

Combining everything: and integrating:

, we get

)(xvvv GSox

)()(''')( xnTNoxoxx EVvCWvQxi

)()(")(0 0

xdvVxvvWCdxxi TNGS

L v

oxn

DS

'''' and,where oxnnnn CKL

WKK


Triode (a bit of history)

A triode is an electronic amplification device having three active electrodes. most commonly it’s a vacuum tube with three elements: the filament (cathode), the grid (controlling element), and the plate or anode. The triode vacuum tube was the first electronic amplification device. It’s iv-characteristics was quite linear.


N-MOSFET: Triode Region Characteristics• The expression for iD is quadratic in vDS

vDSi K v VnD TNGS 2

vDS



with max reached at vDS = vGS - vTN = vOV


vDS



with max reached at vDS = vGS - vTN = vOV

• For small vDS << vGS - vTN , the characteristics iD vs. vDS appear to be linear (triode region, linear)

vDS



N-MOSFET: Triode Region CharacteristicsUnder this condition, MOSFET behaves like a gate-source voltage-controlled resistor between source and drain,

1

onRi K v V v vnD TNGS DS DS

• The expression for iD is quadratic in vDS with max reached at vDS = vGS - vTN = vOV



N-MOSFET: Triode Region Characteristics

( )

1

'0

1'

on

DS

R

Ron WK V V Vn GS TN DSL v

VGSWK V Vn TNGSL

Under this condition, MOSFET behaves like a gate-source voltage-controlled resistor between source and drain,

where on-resistance:

1

onRi K v V v vnD TNGS DS DS

• The expression for iD is quadratic in vDS with max reached at vDS = vGS - vTN = vOV



MOSFET as Voltage-Controlled ResistorExample: Voltage-Controlled Attenuator



) , ) 1( (1

o GS s GSv v

v Ro onG V G V v R Rs K R V Von n TNGS

If Kn=500 A/V2, VTN=1V, R=2k and VGS = 1, 1.5, 2 V:



) , ) 1( (1

o GS s GSv v



( 1) 1 1

A1 500 2000 1 1 V

2V

GSG V



) , ) 1( (1

o GS s GSv v



( 1) 1 1

A1 500 2000 1 1 V

2V

GSG V

( 2) 1 0.5

A1 500 2000 2 1 V

2V

GSG V



) , ) 1( (1

o GS s GSv v


( 1.5) 1 0.667

A1 500 2000 1.5 1 V

2V

GSG V

To maintain triode region operation,v V Vo GS TN

or

vDSvGS VTN


( 1) 1 1

A1 500 2000 1 1 V

2V

GSG V

( 2) 1 0.5

A1 500 2000 2 1 V

2V

GSG V


NMOS Transistor: inversion layer change

VOV - overdrive voltage

If we increase vDS , and it’s no more vDS << VGS - VTN = VOV (triode region limit), it starts influencing the depth of induced inversion layer, for which we need VGS > VTN.


NMOS Transistor: inversion layer change If we increase vDS , and it’s no more vDS << VGS - VTN = VOV (triode region limit), it starts influencing the depth of induced inversion layer, for which we need VGS > VTN.

vDS = VOV - pinch-off voltage, saturation region begins

VOV - overdrive voltage


NMOS Transistor: Saturation Region

is also called saturation or pinch-off voltage.

v v VTNDSAT GS

What is the current in saturation region?

• When vDS increases above triode region limit, channel region akmost disappears, MOSFET also said to be pinched-off.

• Current saturates at (almost) constant value, independent of vDS.


NMOS Transistor: Saturation Region

' 2

2

K Wni v VD TNGSL

for DS GS TN

v v V

Substituting vDS = vGS - VTN into previous equation for drain current, we get

Example here

• Saturation region operation mostly used for analog amplification.

is also called saturation or pinch-off voltage.

v v VTNDSAT GS

• When vDS increases above triode region limit, channel region akmost disappears, MOSFET also said to be pinched-off.

• Current saturates at (almost) constant value, independent of vDS.


NMOS Transistor: iv-characteristic

( )GS po TN

v x Vv


NMOS Transistor: Region Summary• If vDS << VGS - VTN MOSFET is in linear

portion of the triode region

Triode



portion of the triode region • If vDS < VGS - VTN MOSFET is in quadratic

portion of the triode region



portion of the triode region • If vDS < VGS - VTN MOSFET is in

quadratic portion of the triode region • If vDS < VGS - VTN MOSFET is in saturation

region and current saturates at (almost) constant value, independent of vDS.

Discuss how to build the iv graph


Transconductance of a MOS Device

• Transconductance is the important characteristics that relates the change in drain current to a change in gate-source voltage

gmdiD

dvGS Q pt




• Taking the derivative of the expression for the drain current in saturation region,

gmdiD

dvGS Q pt

gmKn'WL

(VGS VTN)2I

DV

GS V

TN




• Taking the derivative of the expression for the drain current in saturation region,

• The larger the device transconductance, the more gain we can expect from the amplifier that uses the transistor.

• Transconductance is inverse to the Ron defined earlier and slightly differently.

gmdiD

dvGS Q pt

gmKn'WL

(VGS VTN)2I

DV

GS V

TN


Channel-Length Modulation• On the previous iv-characteristics, the

saturation part was horizontal (the current was constant, as vDS increases). However, it’s not exactly so.




• As vDS increases above vDSAT , length of depleted channel beyond pinch-off point, DL, increases and actual L decreases.





• Since L is in denominator of the current expression, it compensate slightly the general increase of resistivity, which normally makes the curve flat.

' 2

2

K Wni v VD TNGSL






• As a result, iD increases slightly with vDS

instead of being constant and we can rewrite equation in the form:

' 2

2

K Wni v VD TNGSL

' 2

12

K Wni v V vDSD TNGSL

• On the previous iv-characteristics, the saturation part was horizontal (the current was constant, as vDS increases). However, it’s not exactly so.



• As a result, iD increases slightly with vDS

instead of being constant and we can rewrite equation in the form:


Channel-Length Modulation

where lis the channel length modulation parameter, depends on manufacturing and L.

Va – Early voltage.

' 21

2

K Wni v V vDSD TNGSL


Enhancement and Depletion Mode MOSFETS• The MOSFETS transistors can be of two types:

enhancement mode when VTN > 0



enhancement mode when VTN > 0 depletion mode when VTN < 0

(the NMOS transistors considered so far were of enhancement type.)




(the NMOS transistors considered so far were of enhancement type.) • The depletion mode devices are fabricated by ion implantation process

used to form a built-in n-type channel in device to connect source and drain by a resistive channel.






• In such case, a non-zero drain current exists for vGS=0, and a negative vGS required to turn device off.






• In such case, a non-zero drain current exists for vGS=0, and a negative vGS required to turn device off.

Depletion mode – because negative voltage has to be applied to the gate to deplete the n-type channel and eliminate the current path between the source and the drain.


Output and Transfer Characteristics of MOSFETS• A MOSFET has one output variable – the drain-source current , that

depends on two input variables – drain-source voltage and gate-source voltage (VGS is usually is a control variable).


Output and Transfer Characteristics of MOSFETS• A MOSFET has one output variable – the drain-source current , that depends

on two input variables – drain-source voltage and gate-source voltage (VGS is usually is a control variable).

• Two types of iv-curves are used to describe a MOSFET device fully:

output (drain) curve (DS current vs. DS voltage for a fixed GS voltage)(the earlier considered characteristics were drain curves)


Output and Transfer Characteristics of MOSFETS• A MOSFET has one output variable – the drain-source current , that depends

on two input variables – drain-source voltage and gate-source voltage (VGS is usually is a control variable).

• Two types of iv-curves are used to describe a MOSFET device fully:

output (drain) curve (DS current vs. DS voltage for a fixed GS voltage)(the earlier considered characteristics were drain curves)

transfer curve (DS current vs. GS voltage for a fixed DS voltage, f.i. sat.)

Curves show that the enhancement mode device turns on at VGS = 2, while the depletion mode device turns on at VGS = -2.

Example here


Body Effect or Substrate Sensitivity

• Non-zero vSB changes threshold voltage.

• This is called substrate sensitivity and is modeled by

where

VTO - zero substrate bias for VTN (V)

gbody-effect parameter ,determines the intensity of the body effect

2FF - surface potential parameter (V), typically 0.6V.

VTNVTO

g vSB2F 2F

V

So far it was assumed that the source-bulk voltage vSB , is zero, which means that a MOSFET is a three terminal device. Quite often vSB , especially in ICs is not zero..


NMOS Summary (output characteristics)


PMOS Transistors Structure (Enhancement-Mode)

• p-type source and drain regions in n-type substrate.

00

DI

• n-type source and drain regions in p-type substrate.

NMOSPMOS



• P-type source and drain regions in n-type substrate.

• vGS < 0 required to create p-type inversion layer in channel region

00

DI

• N-type source and drain regions in p-type substrate.

• vGS > 0 required to create n-type inversion layer in channel region

NMOSPMOS





• For current flow, vGS<vTP

00

DI



• For current flow, vGS > vTN

NMOSPMOS





• For current flow, vGS<vTP

• To maintain reverse bias on diodes of source-substrate and drain-substrate junctions: vSB < 0 and vDB < 0

00

DI



• For current flow, vGS > vTN

• To maintain reverse bias on the diodes of source-substrate and drain-substrate junctions: vSB >0 and vDB >0

NMOSPMOS


Enhancement-Mode PMOS Transistors: Output Characteristics

• For the PMOS transistor, all parameters and behavior are inverse of NMOS transistor.




• Thus the output characteristics of PMOS are the complete inverse of those of NMOS





• Often, they are shown in the inverted scale and then they look very similar to the characteristics of NMOS



• For , transistor is off (note that on the diagram it’s vSG = - vGS).

VGSVTP







• For more negative vGS, drain current increases in magnitude.

VGSVTP







• For more negative vGS, drain current increases in magnitude.

• PMOS is in triode region for small (absolute) values of VDS and in saturation for larger values (note that on the diagram it’s more negative to the right).

VGSVTP





NMOS Summary (model)

For the enhancement-mode NMOS transistor, VTN > 0. For the depletion-mode NMOS, VTN < 0.


PMOS Summary (model)

For the enhancement-mode PMOS transistor, VTP < 0. For the depletion-mode PMOS, VTP > 0.


NMOS and PMOS Summary (regions of operation)


NMOS and PMOS Summary (terminal voltages)


Short Summary of MOSFET (1)• A MOSFET is a 3 terminal (Gate, Source, Drain) or 4 terminal (Gate, Source, Drain,

Body) electronic device -- it has input (usually vGS) and output (usually iD).

• The basic function of all transistors - an input voltage is used to provide the change in the output current (or voltage): – the change in output can be much bigger then the change in the input - amplifier– the change in output can be to turn it on or off – digital gate

• There are two types of MOSFET : PMOS and NMOS

• Both types exist in two modes: Enhancement and Depletion.• NMOS enhancement mode: the output current (the inversion channel) may exist only

when input (vGS ) is positive (>0).

• NMOS depletion mode: the output current (the inversion channel) may exist when input (vGS ) is zero, requires to apply vGS <0 to shut the current).

• PMOS is pretty much the complete inverse of NMOS.


Short Summary of MOSFET (2)

NMOSBody: p-substrateSource, Drain: n+

Inversion (conduction) layer: n

E-NMOSChannel

(drain current exists

when vGS > 0)

VTN > 0

D-NMOSChannel


when vGS = 0)

VTN <= 0

PMOSBody: n-substrateSource, Drain: p+

Inversion (conduction) layer: p

E-PMOSChannel


when vGS < 0)

VTP < 0

D-PMOSChannel


when vGS = 0)

VTP >= 0


Short Summary of MOSFET (3)• MOSFET is a symmetrical device – D and S are interchangeable.• MOSFET is fully described by two characteristics:

- input-output or transfer characteristic: (iD - vGS or vDS - vGS )

- output characteristic: (iD – vDS )

• All four types of MOSFET may operate in three regions:

- cutoff : output current is 0

- triode: output current almost linearly depends on output voltage vDS (like in resistor)

- saturation: output current almost does not depend on DS voltage vDS (like in diode)

Transfer characteristics Output characteristics


MOSFET Circuit Symbols

• (g) and (i) are the most commonly used symbols in VLSI logic design.

• MOS devices are symmetric.• In NMOS, n+ region at higher

voltage is the drain.• In PMOS p+ region at lower

voltage is the drain


MOSFET Analysis• Depending on the type of application, a MOSFET may be put into one of three

regions of operation by setting its operating Q-point .



regions of operation by setting its operating Q-point.• For binary logic application the transistor acts like an “on-off” switch and the

Q-point is set in ether cut-off region (“off”) or in the triode region (“on”) for the output characteristic or at the ends of transfer characteristic.



regions of operation by setting its operating Q-point.• For binary logic application the transistor acts like an “on-off” switch and the

Q-point is set in ether cut-off region (“off”) or in the triode region (“on”) for the output characteristic or at the ends of transfer characteristic.

• For amplifier application, the Q-point is set in the saturation region for the output characteristic or in the middle (high) point of the transfer characteristic


MOSFET Analysis: logic inverter example

• For the low values of input vGS (binary 0) the MOSFET is off, iD =0 and vDS = vout = 5V binary 1.

=low

= 0

= 5

• For vGS =5V (binary 1) the MOSFET is on, iD is high, and the output voltage vDS = vout = 0.65V binary 0.



= 5

=high

=0.6



• For the low values of input vGS (binary 0) the MOSFET is off, iD =0 and vDS = vout = 5V binary 1.

• For vGS =5V (binary 1) the MOSFET is on, iD is high, and the output voltage vDS = vout = 0.65V binary 0.

= 5

=high

=0.6

=low

= 0

= 5


MOSFET Analysis: amplifier example• For the amplifier, the Q-point created by

vGS = 2.5V is located at the high slope region of transfer characteristic and at the saturation region of the 2.5V curve.

=2. 5


MOSFET Analysis: amplifier example• For the amplifier, the Q-point created by

vGS = 2.5V is located at the high slope region of transfer characteristic and at the saturation region of the 2.5V curve.

• A small AC signal is added to vary the gate voltage about vGS = 2.5V, which causes the drain current to change significantly and amplified replica of the input appears at the drain.

=2. 5


MOSFET Analysis: load line example• From KVL for the right loop:

vDD - vDS - iD RD = 0 iD = (vDD - vDS )/RD

• Setting two different values for vDS (5V and 3V for example) two points can be obtained and the load line drawn.

Nonlinearelement

Thevenin equivalent


MOSFET Analysis: load line example• From KVL for the right loop:

vDD - vDS - iD RD = 0 iD = (vDD - vDS )/RD

• Setting two different values for vDS (5V and 3V for example) two points can be obtained and the load line drawn.

• Intersection with the transistor iv-curve gives the Q-point, which, of course, depends on the input vGS.

Conclusion• The same device in the similar circuits may

behave differently depending on the ‘biasing‘ – DC voltages applied to different terminals of MOSFET. The ‘signal’ then, is actually comprised of relatively small changes in the DC current and/or voltage bias.

Nonlinearelement

Thevenin equivalent


Bias Analysis Approach• The previous examples shows the importance of biasing for the desired

operation of MOSFET.• Because of nonlinearity of characteristics and substantial difference in

operation region equations (different equations used), iterative approach is used:





• Assume an operation region (generally the saturation region)





• Assume an operation region (generally the saturation region)• Use circuit analysis to find VGS (left, input loop)






• Use VGS to calculate ID, and ID to find VDS (right, output loop)






• Use VGS to calculate ID, and ID to find VDS (right, output loop)

• Check validity of operation region assumptions• Change assumptions and analyze again if required.

NOTE : An enhancement-mode device with VDS = VGS is always in saturation.Why? For pinch off: VDS >= VGS - VTN . If VDS = VGS , then VDS >= VDS - VTN , or VTN >= 0, which is

always true for E-MOS device.


Problem: Find Q-pt (ID, VDS , VGS) without and with the channel-length modulation ( and ).

Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region.

0 102.0 V

Bias Analysis 1- Constant GS Voltage Biasing (1)

Do this example on the board




Assumption: 1. Transistor is saturated. 2. IG=IB=0.

0 102.0 V



Analysis:

Simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage.

Bias Analysis: Ex.1- Constant GS Voltage Biasing (1)

0 102.0 V





Analysis:


Find VGS from the input loop, and then use this to find ID.

0 102.0 V






Analysis:


Find VGS from the input loop, and then use this to find ID.

With ID, we can then calculate VDS using the output loop

0 102.0 V






0 3V I R V V V VEQ GS GS EQG EQ

The left (input) loop. Since IG=0:

A

TNV

GSVnK

DI

502V2132V

A

2

61025

2

2

Then, from the transistor equation:



0 3V I R V V V VEQ GS GS EQG EQ


A

TNV

GSVnK

DI

502V2132V

A

2

61025

2

2

0V I R VDD D D DS

Check:VDS>VGS-VTN. Hence saturation region assumption is correct.

Q-pt: (50.0 mA, 5.0 V) with VGS= 3.0V

Discussion.

The obtained result is proportional to K and to the square of VTN , thus Q-pt. is quite sensitive to the parameter fluctuation of the device, so this circuit is not very used.

VKuAVDS

V 00.5 )100)(50(10

The right (output) loop:

Then, from the transistor equation:




Q-pt: (54.5 mA, 4.55 V) with VGS= 3.00 V

IDKn2

VGS

VTN

2

1VDS

VDSVDD IDRD

VDS10V (100K)(2510 6)2

3 1 2 10.02 VDS

4.55 V

ID(2510 6)2

3 1 2 10.02 (4.55) 54.5 A

Now let’s repeat the same problem taking into account channel length modulation.




Q-pt: (54.5 mA, 4.55 V) with VGS= 3.00 V

IDKn2

VGS

VTN

2

1VDS

VDSVDD IDRD

VDS10V (100K)(2510 6)2

3 1 2 10.02 VDS

4.55 V

ID(2510 6)2

3 1 2 10.02 (4.55) 54.5 A

Discussion.

The bias levels have changed by about 10%. Typically, component values will vary more than this, so there is little value in including effects in most circuits.

Now let’s repeat the same problem taking into account channel length modulation.



Problem: Find Q-pt (ID, VDS , VGS)

Approach: Find an equation for the load line. Use this to find Q-pt at intersection of load line with device characteristic.

Assumptions: 1. IG=IB=0.

Do we need assumption for the transistor region of operation?

Load Line Analysis.






2. No need for region assumption, will find solution directly.

Load Line Analysis.



Analysis: First, simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage

Load Line Analysis.







Analysis: First, simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage

Load Line Analysis.

0

3

V I R VEQ GSG EQ

V V VGS EQ








Check: The load line approach agrees with previous calculation. Q-pt: (50.0 A, 5.00 V) with VGS= 3.00 V

Discussion: Q-pt is clearly in the saturation region. Graphical load line is good visual aid to see device operating region.

@VDS=0, ID=100uA, @ID=0, VDS=10V

Plotting on device characteristic yields Q-pt at intersection with VGS = 3V device curve.

10ID100KVDS

Load Line Analysis.

From the KVL for the right loop, load line becomes

VDDIDRDVDS



Bias Analysis 2 - Four-Resistor Biasing (1)

Problem: Find Q-pt (ID, VDS)

Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region

Assumption: Transistor is saturated, IG=IB=0

Analysis: First, simplify circuit, split VDD into two equal-valued sources and apply Thevenin transformation to find VEQ and REQ for gate-bias voltage



0EQ GS D SV V I R

Left loop. Since IG=0,

STNGSn

GSEQ RVVK

VV 22

4VGS2510 6

3.9104

2V

GS 1

2

VGS20.05VGS 7.210



0EQ GS D SV V I R


STNGSn

GSEQ RVVK

VV 22

4VGS2510 6

3.9104

2V

GS 1

2

VGS20.05VGS 7.210

V66.2,V71.2 GS

V

If VGS= -2.71 , VGS<VTN and MOSFET will be cut-off. Thus

VGS2.66V and ID= 34.4 mA

Solution:



0EQ GS D SV V I R


STNGSn

GSEQ RVVK

VV 22

4VGS2510 6

3.9104

2V

GS 1

2

VGS20.05VGS 7.210

V66.2,V71.2 GS

V


VGS2.66V and ID= 34.4 mA

( ) 0V I R R VDD D D S DS

V08.6DS

V

We have VDS >VGS-VTN .

Hence saturation region assumption is correct.

Q-pt: (34.4 mA, 6.08 V) with VGS= 2.66 V

Solution:

Right loop.



• Estimate value of ID and use it to find VGS and VSB

• Use VSB to calculate VTN

• Find ID’ using last equation

• If ID’ is not same as original ID estimate, start again.

In previous example, the body terminal was connected to the source, so VSB = 0. Now let’s consider the case with

VGSVEQ IDRS6 22,000ID

VSBIDRS22,000ID

VTN VTOg( VSB

2F 2

F)

VTN 10.5( VSB

0.6 0.6)

ID'2510 6

2V

GS V

TN

2

Iterative solution can be found by following steps:

Bias Analysis 2 - Four-Resistor Biasing (2) Body Effect

0VSB


The iteration sequence leads to ID= 88.0 mA, VTN = 1.41 V,

VDSVDD ID(RDRS)10 40,000ID6.48V

We obtained that VDS>VGS-VTN. Hence saturation region assumption is correct.

Q-pt: (88.0 mA, 6.48 V)

Check: VDS > VGS - VTN, therefore still in active region.

Discussion: Body effect has decreased current by 12% and increased threshold voltage by 40%.

Bias Analysis 2 - Four-Resistor Biasing (2) Body Effect



Assumption: 1. IG=IB=0. 2.Transistor is saturated since VDS=VGS

Bias Analysis 3 – Two Resistor (saturation)




Analysis. No need for input loop: VDS=VGS

Output loop:

VDSVDD IDRD


VDSVDD IDRD

2

2 D

KnV V V V V RGS TNDDGS DS

21

2

4104106.23.3

GSV

GSV

V00.2,V769.0 GS

V


V00.2DS

VGS

V and ID= 130 mA

We obtained VDS>VGS-VTN. Hence saturation region assumption is correct.

Q-pt: (130 mA, 2.00 V)


Analysis. No need for input loop: VDS=VGS

Output loop:



Discussion of Four and Two-Resistor Biasing

Four resistor• Provide excellent bias for transistors in discrete circuits.• Stabilize bias point with respect to device parameter and temperature

variations using negative feedback.• Use single voltage source to supply both gate-bias voltage and drain

current.• Generally used to bias transistors in saturation region in amplifier circuits.

Two-resistor • Uses lesser components that four-resistor biasing and also isolates drain

and gate terminals.

• Feedback mechanism. Suppose, for some reason ID begins to increase. From it follows that VGS has to decrease, since Vg is constant. This will decrease the current ID due to current equation, thus restoring the existing state.

0EQ GS D SV V I R


Assumption: 1. IG=IB=0 2. Transistor is saturated.

Analysis.

Left loop: VGS=VDD=4 V

ID2502

AV2

(4 1)21.13mA

Bias Analysis 4 – One Resistor (triode)




Analysis.


ID2502

AV2

(4 1)21.13mA

DSVDRDIDDV Right loop:

V19.2DS

V

DIDS

V 16004




Analysis.


ID2502

AV2

(4 1)21.13mA

2

A4 1600 250 (4 1 )

2VDS

DS DS

VV V

2.3, 8.7 = 2.3VDS

V and ID=1.06 mA

We obtained VDS<VGS -VTN, transistor is in triode region

Q-pt:(1.06 mA, 2.3 V)


DSVDRDIDDV Right loop:

V19.2DS

V

DIDS

V 16004

We obtained VDS<VGS -VTN. Hence, saturation region assumption is incorrect.

Assume the triode region and use the triode region equation:


Bias Analysis 5 - Two-Resistor, PMOST

Assumption: 1. IG=IB=0

2. Transistor is saturated: VDS=VGS

Analysis.

Left loop: no need, VDS=VGS

Right loop: 15V (220k ) 0I VDSD

2A5015V (220k ) 2 02 2V

V VGS GS

0.369V, 3.45VVGS

Since VGS= -0.369 V is more than VTP= -2 V, we take VGS = -3.45 V

Then we can calculate ID = 52.5 mA.

Check:

Hence saturation assumption is correct.

Q-pt: (52.5 mA, -3.45 V)

VDS VGS VTP



Junction Field-Effect Transistors (JFET)

Chap 4-138


Junction Field-Effect Transistors (JFET)

n-channel JFET consists of:• n-type semiconductor block that houses

the channel region in n-channel JFET.• pn junction - forms the gate.• Source and drain terminals

Chap 4-139

• MOSFET devices are called FET because electric field is used to control the shape and hence the conductivity of the channel of one type charge carrier (p or n) in semiconductor device.

• There is another type of FET, which is not using MOS capacitor structure, however utilizes the electric filed effect: Junction Field-Effect Transistor.

• Less prevalent than MOSFET, JFET have many uses, especially in analog RF applications.• Can be of two types: n-channel and p-channel JFET.

Like a diode with enlarged n-type section and two n-terminals.


JFET Structure

• In triode region, JFET is a voltage-controlled resistor,

r - resistivity of channel

L - channel length

W - channel width between pn junction depletion regions

t - channel depth

• With no bias applied, a resistive channel exists. The current enters channel at the drain and exits at source.

• The resistance of the drain-source channel is controlled by changing the physical width of the channel through modulation of the depletion layers around pn-junctions (like squeezing a garden hose)

• Application of reverse bias to the gate-channel diodes causes the depletion layer to widen, reducing the channel width and decreasing the current.

• JFET is inherently a depletion-mode device – a voltage must be applied to turn the device off.

Chap 4-140

WL

tRCH


JFET: applying Gate-Source voltage

Chap 4-141

• vGS = 0. The channel width is W. It can conduct current well if vDS is applied.



Chap 4-142


• VP < vGS <0. The depletion layers width is increased. The channel width W’ < W, and channel resistance increases. Gate-source junction is reverse-biased, iG almost 0.




• VP < vGS <0. The depletion layers width is increased. The channel width W’ < W, and channel resistance increases. Gate-source junction is reverse-biased, iG almost 0.

• vGS = VP < 0. The depletion layer is max. Channel width – zero, region is pinched-off, channel resistance is infinite.

Chap 4-143


JFET: applying Drain-Source voltage

• With constant vGS, depletion region near drain increases with vDS

Chap 4-144




• At vDSP = vGS - VP , channel is totally pinched-off; iD is saturated. (the current does not stop: electrons are accelerated down the channel (V is large), are injected into the depletion region and swept to the drain)

Chap 4-145





• JFET also suffers from channel-length modulation like MOSFET at larger values of vDS.

Chap 4-146





• JFET also suffers from channel-length modulation like MOSFET at larger values of vDS.

Chap 4-147

http://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/jfet.htmlhttp://learnabout-electronics.org/fet_03.php

Simulation:

http://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/jfet.html

http://learnabout-electronics.org/fet_03.php


N-Channel JFET i-v Characteristics

Transfer Characteristics Output Characteristics

Chap 4-148

The JFET iv-characteristics are remarkably similar to the MOSFET characteristics (virtually identical).


N-Channel JFET i-v equationsEquations are similar to MOSFET except written slightly differently • For all regions :• In cutoff region: • In Triode region:

• In pinch-off region:

Explanation:

iG0 for v

GS0

iD0 for v

GSV

P V

P0

2

2

2 for and 02DSDSS

GS PD DS GS P GS P DSP

vIi v V v v V v V VV

2

1 1 for and 0GSDSD DSS GS P DS GS P

P

vi I v v V v v V

V

Chap 4-149

2 2

2 2

2

( ) ( ) = ,2 2

where ( ) , [10μA, 10A], [ 25V, 0]2

1 1GS GSn nD GS P P DSS

P P

nP PDSS DSS

K KV V I

KI V I V

v vi v

V V

Typically: [10 , 10 ], [-25V, 0V]DSS P

A AI V


P-Channel JFET

• Polarities of n- and p-type regions of the n-channel JFET are reversed to get the p-channel JFET.

• Channel current direction and operating bias voltages are also reversed.

Chap 4-150


JFET Circuit Symbols

• JFET structures are symmetric like MOSFETs.• Source and drain determined by circuit voltages.

Chap 4-151

n-channel p-channel


JFET n-Channel Model Summary

Chap 4-152


JFET p-Channel Model Summary

Chap 4-153


Biasing JFET (1)

• Assumptions: Gate-channel junction is reverse-biased, reverse leakage current of gate, IG = 0

N-channel JFET Depletion-mode MOSFET

Chap 4-154

22 2400 /( ) ( 5) 5000 5

2 2n

PDSS

K A VI V A mA


Biasing JFET (2) DIY

Chap 4-155


Region Assumption: JFET is pinched-off (saturation)

GS

2 23

Input loop: 0,

1 5 10 A 1000 15V

1.91V, 13.1V

G S D D S

GS GSGS DSS S

P

GS

I I I V I R

V VV I R

V

V

Since VGS = -13.1 V is less than VP= -5 V , we take VGS = -1.91 V (n-channel type!)

and, ID = IS = 1.91 mA.

Output loop:

VDSV

DD I

D(R

DR

S)12 (1.91mA)(3k)6.27V

VDS >VGS -VP. Hence pinch-off region assumption is correct and gate-source junction is reverse-biased by 1.91V.

Q-pt: (1.91 mA, 6.27 V)

Chap 4-156

Biasing JFET (3)


Internal Capacitances in Electronic Devices

• Limit high-frequency performance of the electronic device they are associated with.

• Limit switching speed of circuits in logic applications

• Limit frequency at which useful amplification can be obtained in amplifiers.

• MOSFET capacitances depend on operation region and are non-linear functions of voltages at device terminals.


NMOS Transistor Capacitances: Triode Region

Cox” =Gate-channel capacitance per unit area(F/m2).

CGC =Total gate channel capacitance.

CGS = Gate-source capacitance.

CGD =Gate-drain capacitance.

CGSO and CGDO = overlap capacitances (F/m).

CGSCGC

2CGSOW Cox"WL

2CGSOW

CGDCGC

2CGSOWCox"WL

2CGSOW

CSBCJASCJSW PS

CDBCJADCJSW PD

CSB = Source-bulk capacitance.

CDB = Drain-bulk capacitance.

AS and AD = Junction bottom area capacitance of the source and drain regions.

PS and PD = Perimeter of the source and drain junction regions.


NMOS Transistor Capacitances: Saturation Region

• Drain no longer connected to channel

CGS23

CGCCGSOW

CGDCGDOW


NMOS Transistor Capacitances: Cutoff Region

• Conducting channel region completely gone.

CGB = Gate-bulk capacitance

CGBO = gate-bulk capacitance per unit width.

CGDCGDOW

CGSCGSOW

CGBCGBOW


JFET Capacitances

• CGD and CGS are determined by depletion-layer capacitances of reverse-biased pn junctions forming gate and are bias dependent.

Chap 4-161


SPICE Model for NMOS Transistor

Typical default values used by SPICE:

Kn or Kp = 20 mA/V2

g = 0

l = 0

VTO = 1 V

mn or mp = 600 cm2/V.s

2FF = 0.6 V

CGDO=CGSO=CGBO=CJSW= 0

Tox= 100 nm


SPICE Model for JFET

• Typical default values used by SPICE:

Vp = -2 V

l = CGD = CGD = 0

Transconductance parameter BETA

BETA = IDSS/VP2 = 100 mA/V2

Chap 4-163

NJIT ECE271 Dr. Serhiy LevkovChap 4-1 Topic 4 Field-Effect Transistors ECE 271 Electronic Circuits...

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Transcript of NJIT ECE271 Dr. Serhiy LevkovChap 4-1 Topic 4 Field-Effect Transistors ECE 271 Electronic Circuits...