Neta Peled & Hillel Mendelson Supervisor: Mike Sumszyk Annual project " Video communication is useful for an enormous variety of fields: Biomedical, space exploration, entertainment, communication and much more. Video communication is useful for an enormous variety of fields: Biomedical, space exploration, entertainment, communication and much more. The project aims at improving video quality by removing the noise using the non linear diffusion algorithm.To improve video quality, we implemented semi implicit scheme of the non linear diffusion, which is an iterative algorithm that smoothes the image while keeping borders sharp. The project aims at improving video quality by removing the noise using the non linear diffusion algorithm.To improve video quality, we implemented semi implicit scheme of the non linear diffusion, which is an iterative algorithm that smoothes the image while keeping borders sharp. We implemented it on a ProcStarII board. We implemented it on a ProcStarII board. Original image Filtered image dt = 30 one iteration Filtered image dt = 30 one iteration Data from DVI video source is processed in real time on the FPGA to achieve better quality of video, and is then displayed on screen to show real time results. Data from DVI video source is processed in real time on the FPGA to achieve better quality of video, and is then displayed on screen to show real time results. The algorithm result is calculated by inversing a tri diagonal matrix and performing multiple transposes of entire frames. To do so in RT we use memory resources on the chip and DDR in double buffer configuration. The algorithm result is calculated by inversing a tri diagonal matrix and performing multiple transposes of entire frames. To do so in RT we use memory resources on the chip and DDR in double buffer configuration. DDR Bandwidth and restricted memory resources on the FPGA are major challenges. DDR Bandwidth and restricted memory resources on the FPGA are major challenges. Throughout the entire process synchronization methods must be applied Throughout the entire process synchronization methods must be applied Real time demands must be met consistent high throughput. Real time demands must be met consistent high throughput. Working with different clocks through the data path: memory clock, DVI clock and down rated DVI clock. Working with different clocks through the data path: memory clock, DVI clock and down rated DVI clock. We write all DDR controllers to meet functionality, timing and bandwidth demands We write all DDR controllers to meet functionality, timing and bandwidth demands Hardware: GiDEL ProcStarII board DVI transmitter / receiver daughter boards Altera StratixII FPGA Software: No software is needed Tools and environments: Matlab HDL Designer Modelsim Quartus Video source (DVI) T DVI IN DVI IN PIPE DVI OUT DVI OUT columns lines Freq controller: 4F to F T PIPE Freq Controller+T 4F to F data 24bit (RGB) 3bit DVI sync PLL Reset detector DVI Ctrl signals generator DVI sync 3bit 25.2MHz DVI clk DVI clk DDR 8 Double Buffers Gidels memory controller 180MHz StratixII data 24bit Dual Clock FIFO DDR WR controller DDR RD controller wr fin continue rd fin When finishing a frame: Each controller calculates its new address and waits for the other controller to finish. While waiting, the controller keeps sending continue signal to the other controller. Dual Clock FIFO Pipe Down-rate: down rates the original data path frequency into of its original value (DVI frequency DVI frequency) Up-rate: up rates the decreased data path frequency back to its original value (DVI frequency DVI frequency) First transpose: converts a 800x525 frame to a 525x800 frame Second transpose: converts a 525x800 frame to a 800x525 frame Combined transpose and up-rate: a combined controller that performs both up rate and transpose operations Perform preparation stages in Mram memory blocks, to allow performing transpose in DDR in real time