MV3018SOK Specification Ver 1 -...

MV3018SOK Specification Ver 1.02 Company Confidential Documentation L.1

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MV3018SOK

IMAGE CAPTURE DEVICE

MV3018SOK

Document No. : MV-S-210

MtekVision Co., Ltd.


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Contents

1. OVERVIEW.....................................................................................................................................................................5

2. I/O DEFINITION .............................................................................................................................................................7

2.1. PIN LAYOUT...............................................................................................................................................................7

2.2. PIN DESCRIPTION .....................................................................................................................................................7

2.2.1. Sensor Interface .............................................................................................................................................7

2.2.2. Host Interface .................................................................................................................................................8

2.2.3. LCD Interface..................................................................................................................................................8

2.2.4. System .............................................................................................................................................................9

2.2.5. Clock ................................................................................................................................................................9

2.2.6. Power ...............................................................................................................................................................9

3. ELECTRICAL CHARACTERISTICS ........................................................................................................................11

3.1. ABSOLUTE MAXIMUM RATINGS (DVSS = VSS= 0V) ...........................................................................................11

3.2. OPERATION CONDITION..........................................................................................................................................11

3.3. POWER CONSUMPTION ..........................................................................................................................................11

3.4. DC CHARACTERISTICS...........................................................................................................................................11

4. SYSTEM STRUCTURE AND INTEFACE ................................................................................................................12

4.1. HOST INTERFACE ..................................................................................................................................................12

4.1.1. Overview........................................................................................................................................................12

4.1.2. Host Interface Timing...................................................................................................................................13

4.2. SENSOR INTERFACE ...............................................................................................................................................14

4.2.1. Overview........................................................................................................................................................14

4.2.2. Sensor Interface Timing ..............................................................................................................................14

4.3. LCD INTERFACE .....................................................................................................................................................15

4.3.1. Overview........................................................................................................................................................15

4.3.2. LCD Interface Timing ...................................................................................................................................15

5. FUNCTIONAL DESCRIPTIONS................................................................................................................................17

5.1. FUNCTIONS .............................................................................................................................................................17

5.1.1. PREVIEW operation ....................................................................................................................................17

5.1.2. MPEGVIEW operation.................................................................................................................................17

5.1.3. BitBLT operation ...........................................................................................................................................18

5.1.4. SNAPSHOT operation.................................................................................................................................18

5.1.5. CAPTURE operation....................................................................................................................................18

5.1.6. JPEG operation ............................................................................................................................................18

5.1.7. MJPEG Encoding operation .......................................................................................................................18


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5.1.8. MJPEG Decoding operation .......................................................................................................................19

5.2. PRE-IMAGE PROCESSING AND SCALING OPERATION.............................................................................................20

5.3. JPEG CODEC ......................................................................................................................................................22

5.4. POST IMAGE PROCESSING......................................................................................................................................23

5.5. LCD CONTROLLER .................................................................................................................................................23

5.5.1. LCD Image Output Format .........................................................................................................................24

6. REGISTER BANKS.....................................................................................................................................................26

6.1. BANK 0 ....................................................................................................................................................................26

6.2. BANK 1 ....................................................................................................................................................................28

6.3. BANK 2 ....................................................................................................................................................................28

6.4. BANK 3 ....................................................................................................................................................................28

7. REGISTER DESCRIPTION........................................................................................................................................30

7.1. MV CONTROLLER REGISTERS ...............................................................................................................................31

7.2. SENSOR INTERFACE REGISTERS ...........................................................................................................................36

7.3. I2C CONTROLLER REGISTERS...............................................................................................................................38

7.4. PRIMARY SCALER REGISTERS ............................................................................................................................39

7.5. SECONDARY SCALER REGISTERS .......................................................................................................................40

7.6. JPEG CODEC ......................................................................................................................................................40

7.7. TD SCALER REGISTERS ......................................................................................................................................42

7.8. LCD CONTROLLER REGISTERS .............................................................................................................................45

8. PACKAGE INFORMATION........................................................................................................................................48

APPENDIX 1. TABLE CONTENT .....................................................................................................................................49

APPENDIX 2. FIGURE CONTENT ...................................................................................................................................49


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Documentation History

Date Version Author Description Remark

2005-02-21 Ver. 1.00 D.Y. Shin Initial release 2005-02-24 Ver. 1.01 D.Y. Shin Update power consumption 2005-03-15 Ver. 1.02 D.Y. Shin Correct register classification table of bank2


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1. Overview MV3018 is a Camera Control Processor providing the most efficient camera functions for portable terminal devices such as mobile

handsets. MV3018 provides rich video functions up to 30-frame display with minimized tasks in the handset main processor as well as

hardware based real-time JPEG compression and decompression. MV3018 directly transmits and previews the RGB data to the LCD

graphic memory by processing the sensor output data according to the cell phone’s command. MV3018 can allow the host processor to

download with scalable sized compressed data. In addition, MV3018 can download the compressed image to either store the original RGB

data or transfer the image to the LCD. This feature allows the main processor to minimize its function while obtaining the result of the image

process. MV3018 can support sensors up to 300K pixels with 1Mbit internal memory.

MV3018 utilizes 16-bit/18-bit data bus for communication with the main processor, including bus interface types such as Intel 80series,

Motorola 68 series, TI and AGERE base band chipsets. MV3018 provides features such as capturing and previewing 90, 180, 270-degree

images, which enables developers to be free from limitation of PCB design layout due to mechanical reasons by positioning sensors to fit

the design space. EZ-OSD technology provides Picture-in-Picture (a variable size window with overlay functions) and dynamic menu display

during image previewing. EZ-OSD allows the main processor to access OSD memory during MV3018 is in camera preview mode.

MV3018 is integrated with a hardware 2D graphic Acceleration Engine for gaming application. MV3018 provides precise power control

states, from standby state to full operation state.

KEY FEATURES

Image Sensor

CMOS/CCD type image sensor interface

Image size: VGA / CIF type

Image Effects

GAMMA enhance

Edge Enhance / Smoothing filter

Gray / negative / sepia / emboss / sketch / UV Selection

LCD

Main LCD 8 bit / 12 bit / 16 bit / 18 bit

Sub LCD 8 bit / 12 bit / 16 bit / 18 bit

176x220 resolution support at 30 fps mode

320x240 resolution support at 15 fps mode

Compression

JPEG encoding YCbCr422 up to VGA

90, 180, 270 degree rotate & mirror capture support up to QVGA

Free size real Zoom up to 8X with JPEG encoding

Free size JPEG encoding support


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Decompression

JPEG decoding (444/422/420/411) up to VGA

Moving Picture

MJPEG format

Hardware dedicated method

Software management method

Easy controllable Encoding & decoding frame rate

Display Management

EZ-OSD support: 13bit color 2 windows

OSD Window

Transparent Window

Super impose Window

16bit/18bit color interface support

4x digital zoom

2D graphics engine

BitBLT

Color conversion

Data Interface

Host I/F parallel 16bit / 18bit

Strobe function (FLASH)

5 GPIO

Power Management

I/O power supply: 1.7 ~ 3.0V

Separated I/O power support: SVDD (Sensor), MVDD (MCU), LVDD (LCD), RVDD (Regulator)

Core power is provided by internal voltage regulator

Standby current less than 100uA

Full operation current less than 35mA (under 20mA in the preview mode)

Package

8mm x 8mm, 81BGA 0.8mm pitch, Max 1.05mm Thickness


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TOP VIEW

2. I/O Definition 2.1. Pin Layout

A1 A2 A3 A4 A5 A6 A7 A8 A9

RESET DVSS DI0 DI2 DI4 DI6 PCLK HREF

SDA

B1 B2 B3 B4 B5 B6 B7 B8 B9

MA0 MVDD DI1 DI3 DI5 DI7 SVDD VSYNC

SCL

C1 C2 C3 C4 C5 C6 C7 C8 C9

MA1 MD16/ GPIO0

MD17/ GPIO1 DVSS LD15 LD14 LD13 DVSS

SMCKO

D1 D2 D3 D4 D5 D6 D7 D8 D9

MCS

MINT MREN VEO LD12 LD11 RVDD GPIO3

GPIO4

E1 E2 E3 E4 E5 E6 E7 E8 E9

MD0 MD1 MWEN LD10 LD9 LD8 LD16 GPIO2 (strobe)

VEO

F1 F2 F3 F4 F5 F6 F7 F8 F9

MD2 MD3 MD4 MD5 LD7 LD6 LD5 DVSS

CLKI

G1 G2 G3 G4 G5 G6 G7 G8 G9

MD6 MD7 MD8 LD17 LD4 VEO LD3 LD2

CLKO

H1 H2 H3 H4 H5 H6 H7 H8 H9

LVDD MD9 MD10 MD11 RVDD LD1 LD0 LCS2

DVSS

J1 J2 J3 J4 J5 J6 J7 J8 J9

DVSS MD12 MD13 MD14 MD15 LRS LREN LWEN

LCS1

Figure 1 Pin Layout (TOP VIEW)

2.2. Pin Description 2.2.1. Sensor Interface

There are a total of 14 sensor related signals. I2C signal that controls the sensor is an Open Drain Type, and it needs a pull up register.

# Name I/O Pin Type Description RESET A8 HREF I Line synchronization signal from sensor B8 VSYNC I Frame synchronization signal from sensor A3 DI0 I Pixel data bit 1 from sensor (LSB) B3 DI1 I Pixel data bit 2 from sensor A4 DI2 I Pixel data bit 3 from sensor B4 DI3 I Pixel data bit 4 from sensor A5 DI4 I Pixel data bit 5 from sensor B5 DI5 I Pixel data bit 6 from sensor A6 DI6 I Pixel data bit 7 from sensor B6 DI7 I Pixel data bit 8 from sensor (MSB) B9 SCL I/O Open-drain I2C clock (Full up register needed) Hi-Z A9 SDA I/O Open-drain I2C data line (Full up register needed) INPUT A7 PCLK I Schmitt Pixel clock from sensor C9 SMCKO O Sensor main clock output 0

Table 1 Sensor Interface Description


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2.2.2. Host Interface

There are 24 I/O signals needed for MCU interface. 2 address signals can access 4 banks. Each bank is a pointer to access LCD,

MV3018 internal buffer, registers, and special registers.

# Name I/O Pin Type Description RESET B1 MA0 I Schmitt HOST address bit 1 C1 MA1 I Schmitt HOST address bit 2 E3 MWEN I Schmitt Active low write signal D3 MREN I Schmitt Active low read signal D1 MCS I Schmitt Active low chip select signal D2 MINT O Active high interrupt signal 0 E1 MD0 I/O HOST data bit 1 INPUT E2 MD1 I/O HOST data bit 2 INPUT F1 MD2 I/O HOST data bit 3 INPUT F2 MD3 I/O HOST data bit 4 INPUT F3 MD4 I/O HOST data bit 5 INPUT F4 MD5 I/O HOST data bit 6 INPUT G1 MD6 I/O HOST data bit 7 INPUT G2 MD7 I/O HOST data bit 8 INPUT G3 MD8 I/O HOST data bit 9 INPUT H2 MD9 I/O HOST data bit 10 INPUT H3 MD10 I/O HOST data bit 11 INPUT H4 MD11 I/O HOST data bit 12 INPUT J2 MD12 I/O HOST data bit 13 INPUT J3 MD13 I/O HOST data bit 14 INPUT J4 MD14 I/O HOST data bit 15 INPUT J5 MD15 I/O HOST data bit 16 INPUT C2 MD16

GPIO0 I

I/O Schmitt MCU data bit 17(Just Input) / GPIO0: This is bi-functional signal. When it used by MD16, GPIO0 should be set by Input mode in order to conflict.

C3 MD17 GPIO1

I I/O Schmitt MCU data bit 18 (Just Input) / GPIO1: This is bi-functional signal. When it

used by MD17, GPIO1 should be set by Input mode in order to conflict.

Table 2 MCU Interface Description

2.2.3. LCD Interface

There are 23 I/O signals for LCD interface. CPU type LCD can be used, data lines are bi-directional and have internal Pull Down registers

to prevent current leakage.

# Name I/O Pin Type Description RESET J6 LRS O Address / data select 0 J8 LWEN O Active low write signal 1 J7 LREN O Active low read signal 1 J9 LCS1 O Active low Main LCD chip select signal 1 H8 LCS2 O Active low Sub LCD chip select signal 1 H7 LD0 I/O Pull-down LCD data bit 0 INPUT H6 LD1 I/O Pull-down LCD data bit 1 INPUT G8 LD2 I/O Pull-down LCD data bit 2 INPUT G7 LD3 I/O Pull-down LCD data bit 3 INPUT G5 LD4 I/O Pull-down LCD data bit 4 INPUT F7 LD5 I/O Pull-down LCD data bit 5 INPUT F6 LD6 I/O Pull-down LCD data bit 6 INPUT F5 LD7 I/O Pull-down LCD data bit 7 INPUT E6 LD8 I/O Pull-down LCD data bit 8 INPUT E5 LD9 I/O Pull-down LCD data bit 9 INPUT E4 LD10 I/O Pull-down LCD data bit 10 INPUT D6 LD11 I/O Pull-down LCD data bit 11 INPUT D5 LD12 I/O Pull-down LCD data bit 12 INPUT C7 LD13 I/O Pull-down LCD data bit 13 INPUT C6 LD14 I/O Pull-down LCD data bit 14 INPUT C5 LD15 I/O Pull-down LCD data bit 15 INPUT E7 LD16 I/O Pull-down LCD data bit 16 INPUT G4 LD17 I/O Pull-down LCD data bit 17 INPUT

Table 3 LCD Interface Description


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2.2.4. System

There are 8 system related signals. APPCLK(M3) can be used as a clock for another IC in the system. In this case, the frequency is the

multiple of the CLKI integer.

# Name I/O Pin Type Description RESET F9 CLKI I Crystal Master clock crystal input, Power group is LVDD. G9 CLKO O Crystal Master clock crystal output, Power group is LVDD. A1 RESET I Schmitt Reset C2 GPIO0 I/O General Programmable Input Output INPUT C3 GPIO1 I/O General Programmable Input Output INPUT E8 STROBE / GPIO2 I/O Light flash trigger signal / General Programmable Input Output INPUT D8 GPIO3 I/O General Programmable Input Output INPUT D9 GPIO4 I/O General Programmable Input Output INPUT

Table 4 System Interface Description

2.2.5. Clock

MV3018SOK’s crystal oscillation input range is maximum 40MHz. Input is CLKI, and output is CLKO. When using the crystal

oscillation device, refer to Figure 2 . The Values of Rfb, Rs, and C1, C2 may be further redefine to meet the frequency requirements of the

system. If the power of CLKI pin is 1.8V, the value of C1, C2 will be changed to 10pF.

Rfb C1,C2 Rs 2M 15 ~ 30pF 0

Table 5 Reference values for clock circuit

CLK

I

Crystal Oscillator

Rfb

C1 C2

Rs

CLKO

Figure 2 Crystal feedback circuit

2.2.6. Power

There are 7 groups, and a total of 14 power signals. Follow instructions in the following Table to connect RVDD, MVDD, LVDD, and

SVDD with the proper interface I/O voltage demanded by the system. AVSS should be separated from the digital ground.

# Name I/O Description B2, MVDD P MCU I/O power supply B7 SVDD P Sensor I/O power supply H1 LVDD P LCD I/O power supply

D7, H5 RVDD P Regulator power supply D4, G6, E9 VEO(CVDD) P Voltage regulator output * Embedded LDO voltage regulator’s power come from MVDD* A2, C4, C8 F8, H9, J1 DVSS P Ground

Table 6 Power Description


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Figure 3 The overview of chip power scheme

The Core voltage is 1.8V from regulator. Each I/O power is separated. Refer Figure 3

MV3018

Core Chip

LVDD(H1)

SensorMCU

Core

CVDD(D4,E9,G6)

for Filter Capacitor

MVDD(B2) SVDD(B7)

GND(A2,C4,C8,F8,H9,J1)

1.8

LCD

RVDD(D7,H5)


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3. Electrical Characteristics 3.1. Absolute Maximum Ratings (DVSS = VSS= 0V)

Parameter SYMBOL Rating UNITS IO Supply voltage VDDIO -0.3 to 4.5 V

Core Supply voltage VDDC -0.3 to 2.5 V Input voltage VIN -0.3 to VDDIO + 0.3 V

DC input current Iin +10 to -10 mA Operation temperature TOPR -40 to 80 C Storage temperature TSTG - 40 to +125 C

1)HBM ± 2000 2)MBM ± 200 Electrical Static Damage (ESD) 3)CDM ± 1000

V

Table 7 Absolute Maximum Ratings

1) HBM: Human Body Model, 2) MBM: Machine Body Model, 3) CDM: Charge Device Model

3.2. Operation Condition PARAMETER SYMBOL MIN TYP MAX UNITS IO Voltage1 VDDIO 1.7 2.8 3.0 V

Core Voltage VDDC 1.65 1.8 1.95 V In-out Range1 VIO VSS VDDIO V

Table 8 Operation Condition

1) VEP generally follows VDDIO. 2) VEO generally follows VDDC.

3.3. Power Consumption PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

1)Dynamic current 1 IDD1 VDDIO = max, VDDC = typ 2.2 mA 2)Dynamic current 2 IDD2 VDDIO = max, VDDC = typ 4.1 mA 3)Dynamic current 3 IDD3 VDDIO = max, VDDC = typ 9.4 mA 4)Dynamic current 4 IDD4 VDDIO = max, VDDC = typ 18.8 mA

5)Quiescent Current 1 IDDS1 VIN=VDD or VSS

VDDIO=max, VDDC = typ IOH=IOL=0

100 uA

Table 9 Power Consumption

1) Bypass mode power consumption when MREN / MWEN signal steadily operates in 5MHz. Actual frequency level is below the hypothetical level.

2) BitBLT operation power consumption. 3) Preview mode power consumption (PCLK=24MHz). 4) Power consumption when all blocks are operating. 5) All disable (standby mode).

3.4. DC Characteristics PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

High Level Input Voltage VIH VDDIO=MAX 0.8*VDDIO V Low Level Input Voltage VIL VDDIO=MIN 0.2V*DDIO V High Level Input Current IH VIN = VDDIO -10 10 uA Low Level Input Current IL VIN = VSS -10 10 uA

High Level Output Voltage VOH VDDIO=MIN IOH = -2mA VDDIO-0.6 V

Low Level Output Voltage VOL VDDIO=MIN IOL=2mA 0.4 V

Table 10 DC Characteristics


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4. System Structure and Inteface MV3018 consists of three internal bus structures, which are emb_bus for memory access, hsb_bus for HOST and internal bus for

communications between internal module. Figure 4 shows the conceptional structure of MV3018 and briefly describes the modules which

composes MV3018. The brief functional description of each module is as follows.

Sensor input is pre-processed at the Sensor PRE_CON of MV3018 and post-processed through Primary Scalar, Secondary Scalar. Super

Impose and scaling are mainly processed. After this, TD scalar transfers the image data which is saved in Embedded memory to LCD,

JPEG. It is designed to perform 2D processing such as BitBLT and OSD function simultaneously. MV3018 is designed to properly perform

the sensor control through I2C and for Host Controller / LCD controller to implement same functions as existing. For the control of MV3018,

macro function setting is to be implemented by MV Controller and it is supposed to manage all of timing and task of MV3018. Depending on

the scenario, the task should be controlled by each module. As the MV3018 is designed to implement best performance at the limited

hardware and bus structure, many scenarios can implement real-time operation. Various functions can be performed without frame skip.

Chapter 7 provides more detailed information to control each block.

Primary Scaler

JPEG (Enc,Dec)

TD Scaler

Host Ctrl.

LCD Ctrl.

Sensor PRE_CON

LCD

Embedded Memory

(16K x 64 = 1Mbit)

BaseBand Processor

SENSOR

Secondary ScalerI2C

PLL / CLKGEN

MV Controller

Figure 4 Functional Block Diagram

4.1. HOST Interface 4.1.1. Overview

HOST interface defines the electrical and physical specification, which is necessary for MCU to control MV3018. This format is


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compatible with i80 (Intel 80), M68, TI and Agere bus types. MCU controls MV3018 registers with HOST interface. Registers will be

described in the following chapters. In the camera mode, the internal and sensor register value can be set to control the MV3018 to execute

the JPEG CODEC operation, camera preview operation and display operation. When not in the camera mode, MV3018 operates in

BYPASS mode to minimize power consumption. MCU can directly control the LCD module. Figure 5 shows the concept of HOST

interface. It shows how the HOST interface signals are converted to LCD signals when MV3018 is in the BYPASS mode.

HOSTProcessor

MV3018

LCD

HO

ST I/F

MINTMCS

MRENMWEN

DATA

ADDR

LRENLWEN

DATA

LCSLRSLC

D I/F

Figure 5 HOST and LCD Interface

MWEN, MREN, MCS are active low signals. Chapter 4.1.2 describes the HOST interface timing information. MINT is used to interrupt

signal to HOST. When it is set by internal event, MCU should check the status register to process the event termination.

4.1.2. Host Interface Timing

Table 11 and Figure 6 describe the waveform and timing of signals for operating the HOST interface.

ITEM SYMBOL MIN TYP MAX UNIT System Cycle time tcycle 3 CLK Control setup time ts1 0 ns Control hold time th1 2 ns

Write enable low timing twl 20 ns Write enable high timing twh 20 ns

Write data setup time ts2 0 ns Write data hold time th2 2 ns

Read enable low timing trl 20 ns Read enable high timing trh 20 ns

Read out data access timing tda 40 ns Read out data hold timing tdh 10 ns

CLK is the system clock period of MV3018

Table 11 HOST Interface Timing Value

WRITE CYCLE

ts1

th2ts2

th1

tcycle

twl

twh

MD[15:0]

MA[1:0]

MWEN

MCS

READ CYCLE

ts1

th2ts2

th1

tcycle

trl

trh

MD[15:0]

MA[1:0]

MREN

MCS

tdhtda

Figure 6 HOST Interface Timing Diagram


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4.2. Sensor Interface 4.2.1. Overview

Sensor interface defines the electrical and physical specifications of MV3018 sensor control. Input image data format is 8bit alternate

YCbCr422, with resolution up to 640(H) X 480(V). MV3018 supplies the clock (SMCLK) to the sensor. It controls the internal register of the

sensor through the I2C bus master that is embedded in MV3018. After setting completion, the sensor supplies the YCbCr422 image data

and the synchronized pixel clock (PCLK) to MV3018.

Image Sensor Module

MV3018

LCD

Sensor I/F

SMCLK

SCLSDA

PCLK

DATA

LRENLWEN

DATA

LCSLRSLC

D I/FVSYNC

HSYNC

Figure 7 Sensor and LCD Interface

VSYNC is a synchronized signal to differentiate frames. HREF is a synchronized signal to differentiate lines. These signals are

synchronized with the pixel clock. In I2C communication SDA and SCL signals are used as data and clock. The minimum frequency of

SCL is 25Khz @ MCLK 25Mhz.

The image data received from the sensor interface is previewed on the LCD at 30fps through the SCALAR and IMAGE ENHANCER

(EDGE Enhance/Smooth, GAMMA, and Effect). This image is compressed into JPEG and is saved in the image buffer. The downloaded

JPEG data in the image buffer can be decompressed and displayed on the LCD.

4.2.2. Sensor Interface Timing

Table 12 and Figure 8 describe the sensor timing of MV3018. The sensor resolution is up to UXGA (640x480).

ITEM SYMBOL MIN TYP MAX UNIT PCLK Period Tpclk 30 ns

PCLK to data setup time Tps 10 ns PCLK to data hold time Tph 10 ns HREF high level period Threfh 640*Tpclk ns HREF low level period Threfl 50*Tpclk ns

HREF period Thref Threfh+Threfl ns Front blank period Tfblk Threfl ns Back blank period Tbblk Threfl ns

VSYNC high level period Ttvsync 10*Thref ns

Table 12 Sensor Interface Timing Values

Figure 8 describes the timing of the horizontal and vertical sync. The horizontal timing describes the relationship between the pixel data

and HREF. HREF and the pixel data should be synchronized with the pixel clock’s negative edge. This is due to the fact that MV3018 uses

the rising edge as a standard to process data. HREF is a HIGH active signal. The total number of pixels in the activate block is 640*2

(UXGA), Luminance (Y) is 640, and Chrominance (CbCr) is 640 each.

The vertical timing describes the relationship between the frame and line. VSYNC active block can either be HIGH or LOW.


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Tps

Threfh

Tph

Tpclk

Threfl

YCbCr PIXEL DATA Cb1 Y1 Cr1 Y2 Cb320 Y639 Cr320 Y640

Horizontal sensor timing (pixel by pixel)

PCLK

HREF

ThrefTfblk Tbblktvsynch

Vertical sensor timing (line by line )

HREF

VSYNC

1 2 3 479 480

480

YCbCr LINE DATA

: INVALID DATA : VALID DATA

Figure 8 Sensor Interface Timing Diagram

4.3. LCD Interface 4.3.1. Overview

LCD interface defines the electrical and physical specifications of MV3018 LCD control. LCD interface is defined as output signals

described in Figure 5 and Figure 7. The timing diagram is described in chapter 4.3.2. It examples when the MV3018 is in preview mode. If

MV3018 is in bypass mode, the timing depends on the main processor. LRS is the special line for indicating that the data is register. LCD

can directly write the value because MV3018 exports LRS as a register. LCD interface can be divided into preview and BYPASS. In

preview operation mode, MV3018 holds all the signals to control the LCD. At this time, MCU cannot directly write to the LCD. Two different

LCDs can be attached to MV3018. LCS1 and LCS2 are select line for each.

4.3.2. LCD Interface Timing

Figure 9 and Table 13 shows the preview timing diagram. In BYPASS mode, timing is dependent on MCU timing.

PREVIEW Operation

LCD Instruction Cycle LCD Data Cycle

t1

LRS

LCS

LWENt2

t3

t4t2

t3

t5

Figure 9 LCD Interface Timing Diagram when preview operation


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ITEM SYMBOL MIN TYP MAX UNIT LRS/LCS setup time t1 LWEN_High_Width Tclk

LWEN low width t2 LWEN_Low_Width+1 Tclk LWEN high width t3 LWEN_High_Width+1 Tclk

LRS hold time t4 1 Tclk LCS hold time from last LWEN t5 3 Tclk

The LWEN_Higth_Width and LWEN_Low_Width are the register of LCD_MODE_CTL (address is 0x00C0)

Tclk is internal operation clock period.

Table 13 HOST Interface Timing Value


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5. Functional Descriptions Each module of MV3018 exists in relatively independent form and is invoked by MV controller. Regarding the functional description, it will be

described by Scenario in MV Controller and described according to module in other operation.

5.1. Functions When scenario related bit is enabled into OPERATION_CTL register of MV Controller, the task invoking signal to each module is generated

by MVC. Most of the functions of MV3018 are operated by hardware but partially HOST control is needed and if necessary, HOST has to

write or read the data real-time.

5.1.1. PREVIEW operation

This scenario is implemented when the “ PREVIEW_EN “ of OPERATION_CTL register in MV Controller is enabled. At this moment,

Primary Scaler and TD Scaler are performed and displayed by LCD controller. Primary Scaler implements Super Impose & Scaling function

and TD scaler implements OSD function. Host can access embedded memory without PREVIEW interruption. In PREVIEW operation,

Super Impose and OSD functions can provide same performance as existing one.

MV3018

Sensor I/FHO

ST I/F

LCD

I/F

Primary Scaler

2D Scaler

HOST MainLCD

Image Sensor Module

OSD / Super

Impose

Figure 10 PREVIEW operation

5.1.2. MPEGVIEW operation

This scenario is implemented when the “ MPEGVIEW_EN “ of OPERATION_CTL register in MV Controller is enabled. MPEGVIEW

executes the function to transfer raw data as YUV 4:2:0 format so that MPEG encoding to HOST is available while operating PREVIEW.

MV3018

Sensor I/FHO

ST I/F

LCD

I/F

Primary Scaler

2D Scaler

HOST MainLCD

Image Sensor Module

YUV 4:2:0

Figure 11 MPEGVIEW operation


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MPEG encoding using raw data can be implemented at the HOST.

5.1.3. BitBLT operation

This scenario is implemented when the “ BitBLT2SRAM_EN “ or “BitBLT2LCD” of OPERATION_CTL register in MV Controller is

enabled. The difference between BitBLT2SRAM and BitBLT2LCD is whether it executes display function to LCD or not. Most of BitBLT

functions are executed by TD scaler.

5.1.4. SNAPSHOT operation

This scenario is implemented when the “ SNAPSHOT_EN “of OPERATION_CTL register in MV Controller is enabled. JPEG encoding of the

captured data is implemented through LCD controller simultaneously with display and written on the embedded memory. If the JPEG

encoding Q-Table value is low for high quality image, the result value can excess the size of embedded memory. In this case, MV3018

should send the data to HOST through interrupt and HOST should read the encoding data during JPEG encoding process.

5.1.5. CAPTURE operation

This scenario is implemented when the “ CAPTURE_EN “of OPERATION_CTL register in MV Controller is enabled and it does not

implement JPEG encoding differently with SNAPSHOT. The captured data remains in the embedded memory and can be encoded through

other operations like makeJPEG.

5.1.6. JPEG operation

JPEG operation has three scenario of “makeJPEG”, “Decode2SRAM” and “Decode2LCD”. “makeJPEG” operation encodes the data utilizing

JPEG encoder of MV3018 when the data to be JPEG encoded is completely written on embedded memory of MV3018. Usually, it is

implemented after Capture operation. With “Decode2SRAM” operation, HOST sends the JPEG decoding command to MV3018 after writing

the data to be decoded on the embedded memory and MV3018 executes JPEG decoding and writes the result on embedded memory.

“Decode2LCD” operation displays the result data through LCD controller simultaneously with decoding.

MV3018

HO

ST I/F

JPEGEncoder / Decoder

2D Scaler

HOSTRaw Data

Primary / SecondaryScaler LC

D I/F

MainLCD

DisplayJPEG

Figure 12 Decode2LCD operation

5.1.7. MJPEG Encoding operation

MJPEG encoding operation executes JPEG encoding while performing Preview function. The result of the process is transmitted to HOST

through interrupt and the HOST enables Motion JPEG by reading MJPEG encoding data. MV3018 allows up to 30 frames per second.

This operation is implemented when “ MJPEG_ENC_EN “bit of OPERATION_CTL register in MV Controller is enabled.


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MV3018

Sensor I/FHO

ST I/F

LCD

I/F

Primary Scaler

JPEG Encoder

HOST MainLCD

Image Sensor Module

JPEGdata

2D Scaler

Figure 13 MJPEG Encoding operation

5.1.8. MJPEG Decoding operation

MJPEG decoding operation displays the decoding data through LCD controller while decoding the MJPEG encoding data. This operation is

like combined Motion JPEG decoding process and display. This operation is implemented when “ MJPEG_DEC_EN “bit of

OPERATION_CTL register in MV Controller is enabled.

MV3018

Sensor I/FHO

ST I/F

LCD

I/F

Primary Scaler

JPEG Decoder

HOST MainLCD

Image Sensor Module

JPEGdata

2D Scaler

Figure 14 MJPEG Decoding operation


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5.2. Pre-Image Processing and Scaling operation The input image from sensor is filtered at enhancing part. At this process, the functions such as Y-gamma, Smooth and etc. are

implemented. From the next processing, image effect is added. Here are the sample images of Y-gamma which MV3018 utilizes.

Sensor input image is improved by the smooth filter to decrease input noise and Y-Gamma filter to sharpen the screen image.

MV3018 provides various image effect and the samples are as follows. Black & White, Sepia, Negative, Embossing, Sketch, Color

Selection as the order of the below images are available.

SSkkeettcchh

SSeeppiiaa BBllaacckk && WWhhiittee

CCoolloorr SSeelleeccttiioonn EEmmbboossssiinngg

NNeeggaattiivvee

Contrast

W

Saturation

(with grayscale)

Input


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MV3018 executes Color selection at UV plane with YUV format. It can define the selected area as multiple format of rectangle(or triangle)

and abstracts correct color. As the below UV plane explains, the simple rectangle format which existing CCP supports can’t allow to abstract

the exact color. It also supports Color de-selection.

After this, Image Masking and Sub-sampling operation is processed. Masking is cutting process by Offset and Size. Offset transfers Start

Point from 0,0 point to offset_x, offset_y. From the transferred Start point to Size_x, Size_y is the valid image data bypassed and the others

are disabled. Super Impose is implemented by Bit masking method. It protects to write after reading the bit which checks whether it is

updated or not from Bit Memory. The pixel protected to write is not available to update the data.

Address Map supports RGB565, YUV422 and YUV420 format and one start address point.

Point 1: highest position

Point 2: Left position of all points

Point 3: Lowest position

Point4 : Right position of all points

Available

1 2 3 4 5 6 7 8 9 a b c d e f

Point1 Point2

Point3 Point4

Cb (U)

Cr (V)f e d c b a 9

8

76 5 4 3 2 1 0

Input Image Input Image + SuperImpose Image


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5.3. JPEG CODEC As a block which executes compression/decompression of image data, it implements JPEG compression using sensor/HOST input image

data and after JPEG data decompression, it sends the output image data to Scalar block. It supports image overlay during executing Image

Data compression.

Encode maximum resolution is VGA(640 x 480)

Encode Image format YUV422

Encode Q-Table Programmable (255 step)

Decode Maximum resolutions are below

640 x 480 @ YUV444, HV Sampling rate 1:1



*Note In case of YUV420 Format, the image data from 352x288 up to 640x480 is scale downed by H/2, V/2 Image Size.

Encode with Time Stamp

Time Stamp window maximum size 500x32

Time Stamp Background & Text color programmable

Time Stamp Background & Text Transparency programmable

Time Stamp window position programmable

Time Stamp Image Bitmap Support

2004 / 08 / 05 2004 / 08 / 05 Figure 15 Encode with Time Stamp Function

FDCT/IDCT ZZ/IZZ Q/IQ VLC/VLD

Qtables2QtablesHuffman tables

Huffman tables

Huffman tables

4 Huffman tables

Figure 16 Structure of JPEG CODEC


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5.4. Post Image processing As a module which executes BitBLT-operation and preview operation, it reads 0~2 image data through embBUS and after image

processing by command, it saves the data at assigned destination. For specific operation, it is working with other modules(sensor/lcd

controller/jpeg).

Maximum resolution is 1023(10bit) x 1023(10bit)

Source image #1 supports YUV[4:2:0], YUV[4:2:2] and RGB[5:6:5] color format.

Source image #2 supports RGB[5:6:5] color format.

In OSD operation, source image #2 supports RGB[4:5:4] with alpha(3bit) format.

Destination image supports YUV[4:2:2], RGB[5:6:5] color format.

It supports BitBLT function(4bit).

For each source, it supports scale((8191/2048) ~ 1/2048)(with sub sampling).

In OSD operation, it doesn’t support the scale for source #2.

It supports Super-impose with chroma-key and alpha-blending.

It supports JPEG/LCD(enable/data/busy) Direct Path mode.

LCD direct data bus supports 18bit(RGB[6:6:6]) format.

JPEG direct data bus supports 8bit(Y,U,Y,V sequence) format only.

In OSD operation, it supports two windows. In this case, two blocks should be saved in sequence on the memory.

The images below show one of BitBLT function of Post-Image processing. Those are the result images after BitBLT function is executed.

In addition to this function, it maximizes image quality using Interpolation method for image enlargement. The post processing of the

captured image is magnified.

5.5. LCD Controller This module transmits RGB data to LCD and post-image processed data is displayed on the LCD through LCD Controller. LCD controller

allows multiple options to support various LCD modules

RGB 8bit, 12bit, 16bit, 18bit CPU Interface Preview support

RGB 8bit, 12bit supports dithering image.

Support multiple LCD data format (pixel align, bus align, merge mode)

Support multiple LCD command format

LCD write enable duty & cycle programmable

1) NOR operation 2) XOR operation 3) AND operation 4) OR opearation


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5.5.1. LCD Image Output Format

The table below shows the LCD Image Output Format which MV3018 can support. The Format consists of 3bit such as Pixel_align bit,

Bus_align bit and Merge bit.

Format Out Data width

Color ‘st 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

X,X,X X 8bit 1’st 0 0 0 0 0 0 0 0 0 0 R3 R2 R1 G3 G2 G1 B2 B1X,X,0 16bit 12bit 1’st 0 0 0 0 0 0 R4 R3 R2 R1 G4 G3 G2 G1 B4 B3 B2 B1

1’st 0 0 0 0 0 0 0 0 0 0 R4 R3 R2 R1 G4 G3 G2 G11,1,0 8bit 12bit

2’st 0 0 0 0 0 0 0 0 0 0 B4 B3 B2 B1 0 0 0 0

1’st 0 0 0 0 0 0 0 0 0 0 R4 R3 R2 R1 G4 G3 G2 G11,0,0 8bit 12bit

2’st 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B4 B3 B2 B1

1’st 0 0 0 0 0 0 0 0 0 0 R4 R3 R2 R1 0 0 0 0 0,1,0 8bit 12bit

2’st 0 0 0 0 0 0 0 0 0 0 G4 G3 G2 G1 B4 B3 B2 B1

1’st 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R4 R3 R2 R10,0,0 8bit 12bit

2’st 0 0 0 0 0 0 0 0 0 0 G4 G3 G2 G1 B4 B3 B2 B1

1’st 0 0 0 0 0 0 0 0 0 0 R4 R3 R2 R1 G4 G3 G2 G1

2’st 0 0 0 0 0 0 0 0 0 0 B4 B3 B2 B1 R4 R3 R2 R1

X,X,1 X 12bit

3’st 0 0 0 0 0 0 0 0 0 0 G4 G3 G2 G1 B4 B3 B2 B1X,X,,0 16bit 16bit 1’st 0 0 R5 R4 R3 R2 R1 G6 G5 G4 G3 G2 G1 B5 B4 B3 B2 B1

1’st 0 0 0 0 0 0 0 0 0 0 R5 R4 R3 R2 R1 G6 G5 G4X,X,,1 X 16bit

2’st 0 0 0 0 0 0 0 0 0 0 G3 G2 G1 B5 B4 B3 B2 B1X,X,0 18bit 18bit 1’st R6 R5 R4 R3 R2 R1 G6 G5 G4 G3 G2 G1 B6 B5 B4 B3 B2 B1

1’st 0 0 R6 R5 R4 R3 R2 R1 G6 G5 G4 G3 G2 G1 B6 B5 B4 B31,1,0 16bit 18bit

2’st 0 0 B2 B1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1’st 0 0 R6 R5 R4 R3 R2 R1 G6 G5 G4 G3 G2 G1 B6 B5 B4 B31,0,0 16bit 18bit

2’st 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B2 B1

1’st 0 0 R6 R5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0,1,0 16bit 18bit

2’st 0 0 R4 R3 R2 R1 G6 G5 G4 G3 G2 G1 B6 B5 B4 B3 B2 B1

1’st 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6 R50,0,0 16bit 18bit

2’st 0 0 R4 R3 R2 R1 G6 G5 G4 G3 G2 G1 B6 B5 B4 B3 B2 B1

1’st 0 0 0 0 0 0 0 0 0 0 R6 R5 R4 R3 R2 R1 G6 G5

2’st 0 0 0 0 0 0 0 0 0 0 G4 G3 G2 G1 B6 B5 B4 B3

1,1,0 8bit 18bit

3’st 0 0 0 0 0 0 0 0 0 0 B2 B1 0 0 0 0 0 0

1’st 0 0 0 0 0 0 0 0 0 0 R6 R5 R4 R3 R2 R1 G6 G5

2’st 0 0 0 0 0 0 0 0 0 0 G4 G3 G2 G1 B6 B5 B4 B3

1,0,0 8bit 18bit

3’st 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B2 B1

1’st 0 0 0 0 0 0 0 0 0 0 R6 R5 0 0 0 0 0 0

2’st 0 0 0 0 0 0 0 0 0 0 R4 R3 R2 R1 G6 G5 G4 G3

0,1,0 8bit 18bit

3’st 0 0 0 0 0 0 0 0 0 0 G2 G1 B6 B5 B4 B3 B2 B1

1’st 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6 R5

2’st 0 0 0 0 0 0 0 0 0 0 R4 R3 R2 R1 G6 G5 G4 G3

0,0,0 8bit 18bit

3’st 0 0 0 0 0 0 0 0 0 0 G2 G1 B6 B5 B4 B3 B2 B1

1’st 0 0 0 0 0 0 0 0 0 0 R6 R5 R4 R3 R2 R1 0 0

2’st 0 0 0 0 0 0 0 0 0 0 G6 G5 G4 G3 G2 G1 0 0

X,1,1 8bit 18bit

3’st 0 0 0 0 0 0 0 0 0 0 B6 B5 B4 B3 B2 B1 0 0

1’st 0 0 0 0 0 0 0 0 0 0 0 0 R6 R5 R4 R3 R2 R1

2’st 0 0 0 0 0 0 0 0 0 0 0 0 G6 G5 G4 G3 G2 G1

X,0,1 8bit 18bit

3’st 0 0 0 0 0 0 0 0 0 0 0 0 B6 B5 B4 B3 B2 B1

1’st 0 0 0 0 0 0 0 0 0 R6 R5 R4 R3 R2 R1 G6 G5 G4X,X,1 16bit, 18bit

18bit

2’st 0 0 0 0 0 0 0 0 0 G3 G2 G1 B6 B5 B4 B3 B2 B1


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* else combination format not support

LCD Command Output Format CMD_SEL 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

TYPE 3 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 0 0

TYPE 2 C16 C15 C14 C13 C12 C11 C10 C9 0 C8 C7 C6 C5 C4 C3 C2 C1 0

TYPE 1 0 C16 C15 C14 C13 C12 C11 C10 C9 0 C8 C7 C6 C5 C4 C3 C2 C1

TYPE 0 0 0 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1


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6. Register Banks MV3018 Memory Map has 4 Addressing bank with 3 functions in each bank. 3 functions are operated depending on the type of bank that

has been selected. Each bank is selected through address 3h. Bank 0 directly controls the LCD. Bank 1 controls MV3018 internal memory,

and is used to read and write the internal memory data. Bank 2 controls MV3018 registers. Bank 3 controls power registers and GPIO.

Address Bank 0 Bank 1 Bank 2 Bank 3 0h LCD Setting Buffer Address High Order/

Buffer Valid write data count Register Index Power Control

1h LCD Main R/W Buffer Address Low Order/ Buffer Valid read data count Register Parameter High (P1) GPIO Data R/W

2h LCD Sub R/W Buffer Data R/W Register Parameter Low (P0) GPIO Direction Control 3h Bank Select

6.1. Bank 0 Address Name Description 0h LCD Setting Used for LCD setting 1h LCD Main Data R/W Used for LCD1 Read/Write 2h LCD Sub Data R/W Used for LCD2 Read/Write. 3h Bank Select Used for switching Bank address

Bank 0 is used for LCD Interface. Write 0 in Bank Select Address (3h) to switch to Bank 0. It is used either to read from or write to the

LCD. Use Address 0 to control LCD_Setting. Address 1 and Address 2 can be used to the register that points to the LCD1 and LCD2.

Bank0 registers

Register Description Register Name RW Bits

Field Name Field Description

Used for LCD Setting

R [15:13] Reserved All zeros

RW [12] LRS_Polarity

LCD_DATA LRS polarity 0: command low level, data high level 1: data low level, command high level Default(0)

R [11] Reserved Zero

RW [9~10] LCD_Command_Sel

0: command type 0 1: command type 1 2: command type 2 3: command type 3 Default(0)

RW [8] LCD_Data_Conv

Data width conversion select 0: no conversion 1:16bit(RGB565) -> 18bit(RGB666) Conversion Default(0)


LCD Setting (0x0)

RW [0] LCD_RS

LCD RS pin control 0 : LCD register 1 : LCD GRAM data select Default(0)


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LCD COMMAND FORMAT CMD_SEL 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

TYPE 3 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 0 0TYPE 2 C16 C15 C14 C13 C12 C11 C10 C9 0 C8 C7 C6 C5 C4 C3 C2 C1 0TYPE 1 0 C16 C15 C14 C13 C12 C11 C10 C9 0 C8 C7 C6 C5 C4 C3 C2 C1TYPE 0 0 0 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1

CMD is processed to LCD in order of LCD_CMD9, LCD_CMD8, …., LCD_CMD0.

1) 80 System 16bit CPU Interface Instruction (Register)

MD15

MD14

MD13

MD8

MD9

MD10

MD11

MD12

MD2

MD3

MD4

MD5

MD6

MD7

MD1

MD0

InstructionBit LD17 LD1LD2LD3LD4LD5LD6LD7LD8LD9LD10LD11LD12LD13LD14LD15LD16 LD0

‘0’ ‘0’


‘0’ ‘0’


‘0’‘0’


‘0’ ‘0’

MD15

MD14

MD13

MD8

MD9

MD10

MD11

MD12

MD2

MD3

MD4

MD5

MD6

MD7

MD1

MD0

MD15

MD14

MD13

MD8

MD9

MD10

MD11

MD12

MD2

MD3

MD4

MD5

MD6

MD7

MD1

MD0

MD15

MD14

MD13

MD8

MD9

MD10

MD11

MD12

MD2

MD3

MD4

MD5

MD6

MD7

MD1

MD0

‘0’ ‘0’

Command Type 0

Command Type 1

Command Type 2

Command Type 3

2) 80 System 16bit CPU Interface data

To GRAM

RGB Assignment

LD17 LD1LD2LD3LD4LD5LD6LD7LD8LD9LD10LD11LD12LD13LD14LD15LD16 LD0

R5 R0R1R2R3R4 G0G1G2G3G4G5 B0B1B2B3B4B5

MD15

MD14

MD13

MD2

MD3

MD4

MD5

MD6

MD7

MD8

MD9

MD10

MD11

MD12

MD1

MD0


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6.2. Bank 1 Address Name Description

0h Buffer Address High Order

<Write operation> Used for setting Buffer Address [19:16]. Memory write operation enable : Buffer Address[31:30] = 10, Memory Single read operation enable : Buffer Address[31:30] = 01, Memory Burst read operation enable : Buffer Address[31:30] = 00, <Read operation> Buffer Valid write data count

1h Buffer Address Low Order

<Write operation> Used for setting Buffer Address [15:0] <Read operation> Buffer Valid read data count

2h Buffer Data R/W Used to Read/Write dedicated Buffer Address Data 3h Bank Select Used for switching Bank address.

Bank 1 is used for the internal buffer interface. Write 1 in Bank Select Address (3h) to switch to Bank 1. Use Address 0 and Address 1 to

set memory address. Use Address 2 to read or write memory.

For example, in order to write 0 in the internal memory 18000h, write 1 in Bank Select(Address 3h) and select Bank1. Write 8001h in the

upper buffer address(Address 0h) and 8000h in the lower buffer address(Address 1h). Designate write base address 18000h and 0 in

data(Address 2h).

6.3. Bank 2

Bank 2 is used for Register Interface. Write 2 in Bank Select Address (3h) to switch to Bank 2. If 16 bits of parameter is needed, set a

reasonable value in the Register Parameter 0. If 32 bits of parameter is needed, set Register Parameter0 and Register Parameter1.

Register Parameter1 becomes the high word value. Register type and function are explained in chapter 7.

6.4. Bank 3 Address Name Description 0h Power Control Used for Power Control 1h GPIO Data R/W Used for GPIO Read/Write 2h GPIO Direction Control Used for setting GPIO Direction 3h Bank Select Used for switching Bank address

Bank 3 is used for Special Register Interface. It is used for Power Control, and GPIO Control. Write 3 in Bank Select Address(3h) to

switch to Bank 3.



It is the register to implement clock control of MV3018.

RW [15] LCD_CS2_Off It makes LCD_CS2 signal output into 0. Default (0)

Power_CTL (0x0)

RW [14] LCD_Output_Off Among the LCD output signals, it makes LCD_RS, LCD_WEN, LCD_REN, LCD_CS1 signal output into 0. Default (0)

Address Name Description 0h Register Index Used for setting Register Index 1h Register Parameter 1 Used for setting Register Parameter 1 2h Register Parameter 0 Used for setting Register Parameter 0 3h Bank Select Used for switching Bank address


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R/W [13] LWEN_MASK_SEL In LCD bypass mode, when MWEN is bypassed to LWEN, the fore part of mask time of MWEN is selected. Default (0)

R/W [12] PCLK_INV

It selects whether reversing PCLK or not. 0: No-reverse 1: Reverse

RW [11] SCLK_Select

It selects the clock output to sensor. In case it is “1”, the internal PLL clock is output, it is “0”, PLL/OSC clock is output by “MISC_CTRL” SCLK_DIV of MVC register. In case it is “1”, the clock source which is internally used utilizes the output of Internal PLL regardless CLK_Source_Select. Default (0)

RW [10] CLK_Source_Select

It selects clock source for internal use. 0 : Utilize Oscillator output. 1 : Utilize Internal PLL output. Default (0)


RW [7] JPEG_CLK_Off It makes JPEG clock off. Default (0)

RW [6] TDS_CLK_Off It makes TD-scaler clock off. Default (0)

RW [5] SCALER_CLK_Off It makes Scaler clock off Default (0)

RW [4] HOST_CLK_Off It makes HOST controller, I2C controller, LCD controller, EMB (memory) bus interface clock off. Default (0)

RW [3] Sensor_CLK_Off It makes sen_clk for Scale off. Default (0)

RW [2] PLL_CLK_EN Enable / Disable clock to PLL block Default (0)

RW [1] MCLK_SEL

Main clock select 0 : MCLK 1 : PCLK

Default (0)

RW [0] OSC_CLK_EN Enable / Disable global clock to MV3018. Default (1)

It shows output or input data to GPIO pin.

R [15:10] Reserved All zeros GPIO_DATA_RW (0x1)

RW [9:0] GPIO_DATA It writes the output data to GPIO pin in Write Mode and reads the input data in Read Mode. Default (0)

It assigns GPIO register direction.

R [15:10] Reserved All ones GPIO_Direction (0x2)

RW [9:0] GPIO_DIR 0 : GPIO pin is set into output mode. 1 : GPIO pin is set into input mode.

Default (1)


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7. Register Description This chapter describes the registers which are used in Bank2 of MV3018.

Figure 12. shows the register outline which is defined and used at Bank2. MV controller is in charge of entire timing and scenario

information of MV3018. The addresses for 5 sub-modules are allocated in all of the registers.

0x0000

0x0020

0x0040

0x0060

0x0080

0x00A0

0x00C0

0x0030

0x00FF

S-Scaler

JPEG Encoder / Decoder

P-Scaler

I2C Controller

MV Controller

Sensor I/F

TD-Scaler

LCD Controller

Figure 17 Register classification for MV3018


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7.1. MV Controller Registers MV Controller controls entire hardware operation and timing and this module executes system functions such as Clock and Reset.

MV Controller has status register to check MV3018 status and sensor input status. Also, it is available to monitor embedded memory access

of internal hardware module. As a result, swift communication with host is possible.



These register is to reset the Internal module.


RW [7] I2C_RESET

This control bit resets I2C controller. Once this bit is set, I2C controller operates in reset status and this bit is cleared, it operates in normal. Default (0)

RW [6] HOST_RESET

This control bit resets Host Interface. Once this bit is set, Host Interface operates in reset status and this bit is cleared, it operates in normal. Default (0)

RW [5] LCD_RESET

This control bit resets LCD controller. Once this bit is set, LCD controller operates in reset status and this bit is cleared, it operates in normal. Default (0)

RW [4] JPEG_RESET

This control bit resets JPEG encoder and JPEG decoder. Once this bit is set, MV controller operates in reset status and this bit is cleared, it operates in normal. Default (0)

RW [3] TDS_RESET This control bit resets 2D-Scaler. Once this bit is set, it operates in reset status and this bit is cleared, it operates in normal. Default (0)

RW [2] SCALER_RESET

This control bit resets Sensor Interface, Primary SCALER, and Secondary SCALER. Once this bit is set, it operates in reset status and this bit is cleared, it operates in normal Default (0)

RW [1] MVC_RESET This control bit resets MV controller only. Once this bit is set, it operates in reset status and this bit is cleared, it operates in normal Default (0)

RESET_CTL (0x0000)

RW [0] SW_RESET

This register resets MV3018. Once this bit is set, all of hardware functions of MV3018 are in reset status and this bit is cleared, it operates in normal. Default (0)

OPERATION_CTL controls MV3018’s functions. To enable the functions, set the corresponding bit into “1” and to stop the functions, set it into “0”. The below registers should implement just one operation at one time.


RW [11] BitBLT2LCD_EN It executes BitBLT operation at TDS and displays the result data on LCD. Default (0)

RW [10] Decode2SRAM_EN It executes JPEG decoding and writes the result data on the internal memory. Default (0)

RW [9] BitBLT2SRAM_EN It executes Bit Block Transfer function. Default (0)

RW [8] MPEGVIEW_EN While operating in preview mode, it send the MPEG raw data to the Host. Default (0)

RW [7] MJPEG_DEC_EN It executes Motion-JPEG decoding Default (0)

RW [6] MJPEG_ENC_EN It executes Motion-JPEG encoding. Default (0)

RW [5] Decode2LCD_EN It executes JPEG decoding and sends the result data to LCD. Default (0)

OPERATION_CTL (0x0001)

RW [4] MakeJPEG_EN It executes JPEG encoding. Default (0)


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RW [3] CAPTURE_EN It controls Capture function. Default (0)

RW [2] SNAPSHOT_EN It controls Snapshot function. Default (0)

RW [1] PREVIEW_EN It performs Preview function of MV3018 Default (0)

RW [0] I2C_EN Control register for the I2C operation. Default (0)

These registers take part in ‘Interrupt_Status’ register operation. When the mask value of corresponding bit is set, the interrupt is generated. S/W is needed so that it can get the necessary interrupt to scenario.

RW [31] Vsync_Interrupt_Mask Default (0) R [30:24] Reserved All zeros RW [23] HrefCNT_Error_Mask Default (0) RW [22] JPEG_Enc_Error_Mask Default (0)

RW [21] JPEG_Dec_Header_Fail_Mask Default (0)

RW [20] JPEG_Dec_Image_Fail_Mask Default (0)

RW [19] MEM_PNT_Int_Mask Default (0) RW [18] MPEGVIEW_Ready_Mask Default (0) RW [17] MJPEG_Dec_Ready_Mask Default (0) RW [16] MJPEG_Enc_Ready_Mask Default (0) R [15:12] Reserved RW [11] BitBLT2LCD_ Mask Default (0) RW [10] Decode2SRAM_ Mask Default (0) RW [9] BitBLT2SRAM_ Mask Default (0) RW [8] MPEGVIEW_ Mask Default (0) RW [7] MJPEG_DEC_ Mask Default (0) RW [6] MJPEG_ENC_ Mask Default (0) RW [5] Decode2LCD_ Mask Default (0) RW [4] MakeJPEG_ Mask Default (0) RW [3] Capture_ Mask Default (0) RW [2] Snapshot_ Mask Default (0) RW [1] Preview_ Mask Default (0)

INTERRUPT_MASK (0x0002)

RW [0] I2C_Mask Default (0)

In case the interrupt mask is set and below cases occur, the hardware interrupt is generated and corresponding bit is set. Software checks the status register under interrupt service routine and to clear the register, it writes "1" and clears the interrupt. Lower 16 bit is generated in normal operation and upper 16 bit is generated in abnormal operation.

RW [31] Vsync_Interrupt It makes VSYNC signal generated from sensor into interrupt signal. Default (0)


RW [23] HrefCNT_Error This error occurs when HREF count value is less than 4h’s ‘HREF_COUNT_SET’ value. It shows the sensor is in malfunction. Default (0)

RW [22] JpegEnc_Error It shows that error occurs in JPEG encoding. Default (0)

RW [21] JPEG_Dec_Header_Fail It shows that error occurs at image header during JPEG decoding. Default (0)

RW [20] JPEG_Dec_Image_Fail It shows that error occurs in JPEG decoding. Default (0)

RW [19] MEM_PNT_Int

‘It occurs when the emb BUS master which is defined at ‘MEMORY_POINTER’ accesses the corresponding memory address. Default (0)

RW [18] MPEGVIEW_Ready It informs that it is ready to send the data in MPEG-Preview to HOST. Default (0)

RW [17] MJPEG_Dec_Ready

It informs that it is ready to receive the data from HOST while operating Motion JPEG decoding. This signal is generated when the TDS is completed. Default (0)

RW [16] MJPEG_Enc_Ready

It informs that the data is ready to be sent to HOST while operating Motion JPEG encoding. This signal is generated when the JPEG encoding is completed. Default (0)

R [15:11] Reserved

INTERRUPT_STATUS (0x0003)

RW [11] BitBLT2LCD_END It shows BitBLT2LCD operation is completed. Default (0)


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RW [10] Decode2SRAM_END It shows JPEG decoding operation is completed. Default (0)

RW [9] BitBLT2SRAM_END It shows Bit Block Transfer operation is completed. Default (0)

RW [8] MPEGVIEW_END It shows MPEG-Preview operation is completed. Default (0)

RW [7] MJPEG_Dec__END It shows Motion-JPEG decoding operation is completed. Default (0)

RW [6] MJPEG_Enc_END It shows Motion-JPEG encoding operation is completed. Default (0)

RW [5] Decode2LCD_END It shows that JPEG decoding is completed and the result data is sent to be displayed on LCD. Default (0)

RW [4] MakeJPEG_END It shows JPEG encoding operation is completed. Default (0)

RW [3] Capture_END It shows Capture operation is completed. Default (0)

RW [2] Snapshot_END It shows Snapshot operation is completed. Default (0)

RW [1] Preview_END It shows Preview operation is completed. Default (0)

RW [0] I2C_END It shows I2C operation is completed. Default (0)

It defines the number of HREF between two VSYNCs and sets. In case the number of sensor HREF is different from that of ‘HREF_COUNT_SET’, HREFCNT_ERROR interrupt occurs. Motion_Speed defines the number of frame to skip when Motion JPEG encoding / decoding, Preview, MPEGview are operated.

R [31:28] Reserved

RW [27:16] HREF_CNT_VAL If the value is “0”, HREFCNT_ERROR interrupt does not occur. When other value is set, it is operated. Default (0)

R [15:4] Reserved MOTION_SPEED (0x0004)

RW [3:0] Motion_Speed

Frame Skip Rate Parameter 0 : 0 VSYNC skip (30 f/s) 1 : 1 VSYNC skip (15 f/s) 2 : 2 VSYNC skip (10 f/s) 3 : 3 VSYNC skip (7.5 f/s) 4 : 4 VSYNC skip (6 f/s) 5 : 5 VSYNC skip (5 f/s) 6 : 6 VSYNC skip (4.28 f/s) 7 : 7 VSYNC skip (3.75 f/s) …… 15: 15 VSYNC skip Default (0)

During Motion JPEG decoding, it does not receive VSYNC from sensor. Therefore, this is the register provided internally to make VSYNC.

R [31:30] Reserved MJPEG_DEC_VSYNC (0x0005)

RW [29:0] VSYNC_PERIOD

Motion JPEG Decoding VSYNC period Parameter If the value is “0”, operation is disabled. When PCLK is 27Mhz, (1/27*10-6 * VSYNC_PERIOD) second Default (0)

It checks whether State Machine clear or Host access of MV Controller is overrun or underrun. MVC_CTL (0x0006)

R [31:20] Reserved


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R [19:18] MVC_Sate

It shows that MVC controller is in below operation. 0 : IDLE 1 : Scaler operation 2 : LCD PREVIEWoperation 3 : LCD MPEGVIEW operation 4 : LCD CAPTURE operation 5 : LCD MJPEG Encoder operation 6 : LCD MJPEG Decoder operation Default (0)

R [17] HostBus_OverRun

In case OverRun is generated when HostBus_Error_Check_Enable is “1”, it is set into “1”. It shows that error occurs due to the fast Write/Read operation. It is cleared when Hbus_Err_Chk_en is “0”. Default (0)

R [16] HostBus_UnderRun

In case UnderRun is generated when HostBus_Error_Check _Enable is “1”, it is set into“1”. It shows that error occurs due to the slow Write/Read operation. It is cleared when Hbus_Err_Chk_en is “0”. Default (0)

R [15:4] Reserved

RW [2] Hbus_Err_Chk_EN

When the value is “1”, it checks whether error in HOST operation due to Overrun / Underrun occurs or not. For normal operation, this bit should be enabled after memory_point interrupt is generated. Default (0)

RW [2] Hbus_write It informs whether the Host operation is read (0) or write (1). Default (0)

RW [1] Ready_Int_Timing_Adj

If the value is “1” and MPEGVIEW ready, MJPEG_Dec ready and scaler end signal are generated, Ready interrupt occurs. If it is “0”, LCD recognizes the generated end signal and Ready interrupt occurs. Default (0)

RW [0] MVC_StateMachine_Clear

If the value is set as “1”, END-State Machine of MV Controller is cleared. It is used to avoid that state machine of MV Controller is in stand-by mode when interrupt is not generated though operation stop. To write “0” allows it to execute normal operation. Default (0)

It shows the current HREF Counter value.


R [29:16] CUR_MEM_ADR

It keeps up showing [19:6] of memory address which master accesses through “Pointer_MASTER” and “Pointer_RW” in “Memory_POINTER”. It is useful when utilizing MEMORY_POINTER. This register operates when HostBus_Error_Check_Enable of MVC_CTRL is “1”.


CURR_ VAL (0x0007)

R [11:0] CURR_HREF_CNT It shows the current HREF count value. This register is intended to be used for various application.

When the specific internal module accesses one address of main memory, it is used to inform HOST about the status. It is used for memory control in SNAPSHOT, CAPTURE, JPEG encoding / decoding process.

R [31:25] Reserved

RW [24] Pointer_CHK_EN In case the memory access which is corresponding with current pointer value is generated, interrupt occurs by this bit. Default (0)

RW [23:21] Pointer_MASTER

It is utilized to assign specific master. 0 : Primary SCALER 1 : Host Interface 2 : JPEG Encoder / Decoder 3 : Two Dimension SCALER Default (0)

RW [20] Pointer_RW

It defines the read/write time of specific master. 0 : Read 1 : Write

Default (0)

MEMORY_POINTER (0x008)

RW [19:0] Pointer_ADDRESS It defines whether it generates MEM_PNT_INT or not when specific master accesses one memory address. Lower [2:0] is not used. Default (0)

Clock control register MISC_CTL (0x001D)

R [31:17] Reserved


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RW [16] Expansion_Mode 0 : 16 bit mode 1 : 18 bit Expansion Mode

Default (0) R [15:8] Reserved

RW [7] SEN_CLK_SEL

Main clock select 0 : PCLK 1 : MCLK

Default (0) R [6] Reserved

RW [5:3] SCLK_DIV

It sets division ratio of sensor output clock. 0 : OFF 1 : FOUT 2 : FOUT/2 3 : FOUT/4

Else: OFF Default (0)

RW [2:0] MCLK_DIV

It sets division ratio of MV3018 main clock. 0 : FOUT 1 : FOUT/2 2 : FOUT/4 3 : FOUT/8

Else: FOUT Default (0)

This register is for Internal PLL frequency setting of MV3018. PLL output frequency is FOUT=(M * FIN / (2 * P)). M : Main_Divider, Range : 1 ~ 10 P : Pre_Divider FIN : input frequency (min 2Mhz ~ max. 40Mhz) FOUT : min. 10Mhz ~ max. 80Mhz R [31:27] Reserved

RW [26:16] Main_Divider

It is utilized for PLL frequency setting. To get the stable clock, Main_Divider value should be less than 10. Default (16)

R [15:8] Reserved

PLL_CTL (0x001E)

RW [7:0] Pre_Divider It is utilized for PLL frequency setting. Default (4 )

It shows MV3018 Device ID.

R [31:16] Device_ID Default

DEVICE_ID (0x001F)

R [15:0] Revision_ID Default ( )

Table 14 MV Control Registers


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7.2. Sensor Interface Registers MV3018 Sensor Interface Module supports diverse forms of sensor input and it has several filters to support image quality improvement

and various effect insertion. Also, it executes screen cropping for Resizing and Rotation.


Bit Field Name Bit field Description

Sensor input control Register


RW [3] Vsync_falling

Do Not Set this value in VSYNC = 1 The timing reference to make vsync_clk for MVC 0 : rising timing, 1 : falling timing Default (0)

RW [2] Hsync_conv 0 : Non conversion, 1 : conversion

RW [1] Vsync_conv 0 : Non conversion, 1 : conversion Default (0)

SENSOR_CTL (0x0020)

RW [0] Strobe_on Strobe pulse enable control 0 : disable, 1 : enable Default (0)

Strobe control Register

RW [31:16] Strobe time Vsync to strobe rise time. the unit is Tpclk Default (0)

STROBE (0x0021)

RW [15:0] Strobe high Strobe pulse high period. The unit is Tpclk Default (0)

Image Filter

R [31:5] Reserved All zeros RW [4] H-Filter 0 : Disable , 1 : Enable

Default (0) – Must be 1.

RW [3] V-Filter 0 : Disable , 1 : Enable Default (0) – Must be 1.


FILTER (0x0022)

RW [0] GAMMA_EN Gamma control register 0 : disable, 1 : enable Default (0)

Sensor Input Width


SENSOR_WIDTH (0x0023)

RW [11:0] Last_mask Sensor H input size

Gamma Setting

RW [31:24] Gamma A The first Vertex of linear gamma curve Default (0)

RW [23:16] Gamma B The second Vertex of linear gamma curve Default (63)

RW [15:8] Gamma C The third Vertex of linear gamma curve Default (127)

GAMMA (0x0024)

RW [7:0] Gamma D The forth Vertex of linear gamma curve Default (191)

Effect Control Register

RW [31:24] Reserved All zeros

RW [23:16] Gamma E The Y’ value at 255 for linear gamma curve Default (0)

EFFECT_CTL (0x0025)



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RW [2:0] Effect_mode

Effect setting 000 : no effect 001 : Gray scale image 010 : Sepia image 011 : Negative image 100 : Emboss image 101 : Sketch image 110 : UV selection image 111 : UV de-selection image Default (0)

Effect Sepia Color Register


RW [15:8] Sepia_u U Color setting for Sepia mode Default (0)

EFFECT_SEPIA (0x0026)

RW [7:0] Sepia_v V Color setting for Sepia mode Default (0)

Effect UV Area Setting Register

RW [31:24] Point1 Point1 for Color selection (Highest point) {point1_u[7:4], point1_v[7:4]} Default (0)

RW [23:16] Point2 Point2 for Color selection (left-side of all points) {point1_u[7:4], point1_v[7:4]} Default (0)

RW [15:8] Point3 Point3 for Color selection (Lowest point) {point1_u[7:4], point1_v[7:4]} Default (0)

EFFECT_UV (0x0027)

RW [7:0] Point4 Point4 for Color selection (right-side of all points) {point1_u[7:4], point1_v[7:4]} Default (0)

Sensor Input primary scaler masking Size Register


RW [26:16] P_V_SIZE Sensor Vertical effect size setting register Default (0)


P_MASK (0x0028)

RW [10:0] P_H_SIZE Sensor Horizontal effect size setting register Default (0)

Sensor Input primary scaler masking Size Register


RW [26:16] P_V_OFFSET Sensor Vertical effect area start point setting register Default (0)


P_OFFSET (0x0029)

RW [10:0] P_H_OFFSET Sensor Horizontal effect area start point setting register Default (0)

Sensor Input secondary scaler masking Size Register


RW [26:16] S_V_SIZE Sensor Vertical effect size setting register Default (0)


S_MASK (0x002A)

RW [10:0] S_H_SIZE Sensor Horizontal effect size setting register Default (0)

Sensor Input secondary scaler masking Size Register


RW [26:16] S_V_OFFSET Sensor Vertical effect area start point setting register Default (0)


S_OFFSET (0x002B)

RW [10:0] S_H_OFFSET Sensor Horizontal effect area start point setting register Default (0)

Table 15 Sensor Interface Registers


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7.3. I2C Controller Registers I2C controller of MV3018 supports up to 7 bytes transmission. It also can adjust the I2C operation speed to support diverse I2C clock by

software.



I2C control register


RW [24:16] SCL_PERIOD I2C CLOCK SCL PERIOD/2 (internal clock unit) Default (200)

RW [15:4] Reserved

RW [3] SONY_MASTER

Configuration of I2C master for SONY sensor 0 : Normal sensor 1 : Sony sensor Default (0)

I2C_CTL (0x0030)

RW [2:0] I2C_NUM

Total number of I2C data 0 : 3 bytes 1 : not used 2 : 4 bytes 3 : 5 bytes 4 : 6 bytes 5 : 7 bytes Default (0)

I2C device address determines read/write operation. The number of byte to write depends on the value of I2C_NUM in register


W [23:16] DEV_ADDR Device Address Default (Not Defined)

W [15:8] REG_ADDR Register Address Default (Not Defined)

I2C_CTL_0 (0x0031)

W [7:0] I2C_DATA_1 Write Data - 1 Default (Not Defined)

I2C device address determines read/write operation. The number of byte to write depends on the value of I2C_NUM in register

RW [31:24] I2C_DATA2 Write Data - 2 Default (Not Defined)



I2C_CTL_1 (0x0032)

RW [7:0] I2C_WRDATA5 Write Data - 5 Default (Not Defined)

Read Data buffer after a read operation of I2C controller


RW [15:8] I2C_DATA_2 Read Data - 2 Default (Not Defined)

I2C_READ (0x0033)

R [7:0] I2C_DATA_1 Read Data - 1 Default (Not Defined)

Table 16 I2C Controller Registers


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7.4. Primary SCALER Registers Primary Scaler is operated preferentially in usual case and it supports Screen Rotation and Super Impose. Main function is to reduce

the input data into the size which user wants. Using P_RATIO and P_SHR_MODE, it helps to get diverse image size. In accordance with

purpose, input format can be converted into RGB565, YUV422, YUV420.

Primary Scaler resizing ratio


RW [29:16] P_VRATIO V-direction scale ratio Default (0)


P_RATIO (0x0040)

RW [13:0] P_HRATIO H-direction scale ratio Default (0)

Primary scaler mode Register


RW [9:8] P_SHR_MODE

Averaging scale mode 00 : no average 01 : 1/2 10 : 1/4 11 : 1/8 Default (0)

RW [7:6] PScale out Format

Scaler output format 0 : RGB565 1 : reserved 2 : YUV422 3 : YUV420


[3] SI_ON Super Impose on/off 0 : OFF, 1 : ON

P_MODE (0x0041)

RW [2:0] P_ROTATE

Rotate control register 000 : 0 degree 011 : 90 degree clock wise rotate 101 : 180 degree clock wise rotate 111 : 270 degree clock wise rotate 010 : 270 degree mirrored rotate 100 : vflip 110 : 90 degree mirrord clock wise rotate

Scaler output size register


RW [27:16] P_OUT_V Scaler output vertical size Default (0)


P_OUT_SIZE (0x0042)

RW [11:0] P_OUT_H Scaler output horizontal size Default (0)

Scaler output address

R [31:20] Reserved All zeros P_START_ADDR (0x004a)

RW [19:0] Pscale Start_addr Output start address, In case of YUV420, Y Output start address Default (0)


R [31:20] Reserved All zeros P_START_ADDR_U (0x004b)

RW [19:0] Pscale Start_addr_u YUV420 U Output start address Default (0)


R [31:20] Reserved All zeros P_START_ADDR_V (0x004c)

RW [19:0] Pscale Start_addr_v YUV420 V Output start address Default (0)

Table 17 Primary Scaler Registers


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7.5. Secondary SCALER Registers Secondary Scaler is utilized when the Primary Scaler is not available or it is need to output to LCD directly. The function of Secondary

Scaler is to reduce the input data into the size which user wants. Using S_RATIO and S_SHR_MODE, it helps to get diverse image size.

The output format to LCD is RGB666.



Secondary


RW [29:28] S_SHR_MOD

S-scaler averaging scale ratio 00 : no average 01 : 1/2 10 : 1/4 11 : 1/8 Default (0)

RW [27:14] S_VRATIO S-scaler vertical scale ratio Default (0)

S_SCALE (0x0060)

RW [13:0] S_HRATIO S-scaler horizontal scale ratio Default (0)

Scaler output size register


RW [27:16] S_OUT_V Scaler output vertical size Default (0)


S_OUT_SIZE (0x0061)

RW [11:0] S_OUT_H Scaler output horizontal size Default (0)

Table 18 Secondary Scaler Registers

7.6. JPEG CODEC In addition to the encoding, decoding functions, JPEG Codec of MV3018 has additional functions which makes diverse application available.

In Snapshot or MakeJPEG mode, hardware automatically adds the saved Time-Stamp into Image and executes encoding.



The quantization table for the JPEG encoding

R [31:8] Reserved All zeros ENC_Q_TABLE (0x0080) RW [7:0] ENC_Q_TABLE

Default (0x80) This register indicates the JPEG image size to be encoded

RW [31:16] ENC_V_SIZE Default (0x0280)

ENC_SIZE (0x0081)

RW [15:0] ENC_H_SIZE Default (0x01E0)

The start address to be written the JPEG data R [31:20] Reserved All zeros

ENC_OUT_ADDR (0x0083) RW [19:0] Out Address Encoded Data Write Buffer Address

Default (0) The length of the JPEG encoded data ENC_OUT_LENGTH

(0x0084) R [31:0] Bitstream_size Bit-Stream Size

Default (0) The start address of JPEG data to be decoded DEC_IN_ADDR



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(0x0085) RW [19:0] Decode Input Address Input address for decoding Default (0)

The decoding speed R [31:11] Reserved All zeros

DEC_Speed (0x0086) RW [10:0] Decode Address Decoding Speed

Default (0) The size of the original image

R [31:16] Real_V_SIZE Analyzed V size Default (0)

DEC_Real_HV (0x0087)

R [15:0] Real_H_SIZE Analyzed H size Default (0)

The size of the masked image that is the final decoded data

R [31:16] Mask_V_SIZE Masked V size Default (0)

DEC_Mask_HV (0x0088)

R [15:0] Mask_H_SIZE Masked H size Default (0)

The sampling factor information of the decoded JPEG data


R [7:4] H Sampling Factor Decoded H Sampling Factor Default (0)

DEC_Header_Info (0x0089)

R [3:0] V Sampling Factor Decoded V Sampling Factor Default (0)

The basic control register for encoding and decoding

RW [2] Encoder Header Save Encoder Header Save 1 : On, 0 : Off Default (1)

RW [1] Decoder Endian Decoder Endian Mode 1 : Big, 0 : Little Default (0)

Codec Config (0x008A)

RW [0] Encoder Endian Encoder Endian Mode 1 : Big, 0 : Little Default (0)

Table 19 JPEG Encoder and Decoder Registers

The transparency of the time-stamp image

RW [2] Zone1 Transparency Image Zone 1 Transparency 0 : 0%, 1 : 50% Default (0)

RW [1] Zone0 Transparency Image Zone 0 Transparency 0 : 100%, 1 : 50% Default (0)

TSTAMP_CTL (0x0090)

RW [0] TSTAMP ENABLE Time Stamp Window enable Default(0)

The offste value of the time-stamp image

RW [25:16] TSTAMP_V_OFFSET Time STAMP Vertical Offset Value Default (0x002)

TSTAMP_OFFSET (0x0091)

RW [9:0] TSTAMP_H_OFFSET Time STAMP Horizontal Offset Value Default (0x002)

The size of the time-stamp image

RW [25:16] TSTAMP_H_SIZE Time STAMP Height Default (0)

TSTAMP_SIZE (0x0092)

RW [9:0] TSTAMP_V_SIZE Time STAMP Width Default (0)

The color for the zone-0

RW [23:16] Cb Data 0 Cb Data 0 Value Default (1)

RW [15:8] Cr Data 0 Cr Data 0 Value Default (0)

TSTAMP_COLOR0 (0x0093)

RW [7:0] Y Data 0 Y Data 0 Value Default (0)

The color for the zone-1 TSTAMP_COLOR1 (0x0094)

RW [23:16] Cb Data 1 Cb Data 1 Value Default (1)


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RW [15:8] Cr Data 1 Cr Data 1 Value Default (0)

RW [7:0] Y Data 1 Y Data 1 Value Default (0)

The memory address to be written the time-stamp image Bitmap Mem Addr (0x0095) RW [8:0] Bitmap Mem Addr Bitmap Memory Address

Default (0)

The data of the time-stamp

W [31:16] Bitmap Memory Data Bitmap Memory Data Default (0)

Bitmap Mem Data (0x0096)

W [15:0] Bitmap Memory Data Bitmap Memory Data Default (0)

Table 20 JPEG Time Stamp Window Control Registers

7.7. TD SCALER Registers

TD SCALER is in charge of Post Image processing in MV3018 and has the function to display BitBLT and OSD. There are two

windows for OSD and it supports True color(RGB454). It uses 3 bit for alpha blending.


Field Name Field Description TDS instruction register R [31:7] reserved All zeros

RW [6:4] function selection

“000” : bitBLT operation selection “100” : copy from source #1 to destination without operation “101” : OSD enable “110” : super-impose enable without chroma-key “111” : super-impose enable with chroma-key others : reserved Default : 0x0

INSTRUCTION (0x00A0)

RW [3:0] BitBLT operation

“0000” : destination <= 0x0000(black) “0001” : destination <= ~(source #1 OR source #2) “0010” : destination <= ~source #1 “0011” : destination <= source #1 AND ~source #2 “0100” : destination <= ~source #2 “0101” : destination <= source #2 XOR pattern “0110” : destination <= source #1 XOR source #2 “0111” : destination <= source #1 AND source #2 “1000” : destination <= ~source #1 OR source #2 “1001” : destination <= source #1 AND pattern “1010” : destination <= source #1 “1011” : destination <= source #1 OR source #2 “1100” : destination <= pattern “1101” : destination <= ~source #1 OR source #2 OR pattern “1110” : destination <= 0xffff(white) “1111” : reserved Default : 0x0

chroma-data/mask register

RW [31:16] chroma-mask chroma mask(RGB[5:6:5] format mask) Default : 0x0000

CHROMA_DATA (0x00A1)

RW [15:0] chroma-data chroma value(RGB[5:6:5] format) Default : 0x0000

pattern value(RGB[5:6:5] format) for BitBLT operation R [31:16] reserved All zeros

PATTERN_DATA (0x00A2)

RW [15:0] pattern-data pattern data(RGB[5:6:5] format) Default : 0x0000


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alpha-blending data register (9 단계) for super-impose or OSD

RW [31:28] alpha #7 alpha-blending data(0 ~ 8) # only used OSD operation Default : 0x0







RW [3:0] alpha #0 alpha-blending data(0 ~ 8) # used OSD/super-impose operation Default : 0x0

ALPHA_DATA (0x00A3)

## alpha data transparency “0000” : 0% “0001” : 12.5% “0010” : 25% “0011” : 37.5% “0100” : 50% “0101” : 62.5% “0110” : 75% “0111” : 87.5% “1000” : 100% others : reserved information of source #1 image R [31:6] reserved All zeros

RW [5:4] pixel format

“00” : RGB[5:6:5] format “01” : reserved “10” : YUV[4:2:2] format “11” : YUV[4:2:0] format Default : 0x0

SRC1_CTL (0x00A4)

R [3:0] reserved All zeros image width of source #1 information R [31:10] reserved All zeros

SRC1_WIDTH (0x00A5)

RW [9:0] image width processing image width(pixel unit)(up to 1023) Default : 0x000

ratio X/Y of source #1 information R [31] reserved All zeros

RW [30:16] ratio Y scaling ratio of Y ## ratio Y = ((source #1 block y) * 2048)/(destination block y) Default : 0x00

R [15] reserved All zeros

SRC1_SCALE (0x00A6)

RW [14:0] ratio X scaling ratio of X ## ratio X = ((source #1 block x) * 2048)/(destination block x) Default : 0x00

Y start address of source #1 R [31:20] reserved All zeros

SRC1_START_ADDR (0x00A7) RW [19:0] start address

source #1 Y start address when YUV[4:2:0] format. source #1 start address of buffer #1 when others format (up to 1Mbyte) Default : 0x0000

SRC1_START_ADDR_U

U start address of source #1


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R [31:20] reserved All zeros (0x00A8)

RW [19:0] start address U source #1 U start address when YUV[4:2:0] format. not used when others format (up to 1Mbyte) Default : 0x0000

V start address of source #1 R [31:20] reserved All zeros

SRC1_START_ADDR_V (0x00A9) RW [19:0] start address V

source #1 V start address when YUV[4:2:0] format not used when others format (up to 1Mbyte) Default : 0x0000

image width of source #2 information R [31:10] reserved All zeros

SRC2_WIDTH (0x00AB)


ratio X/Y of source #2 information


RW [30:16] ratio Y scaling ratio of Y ## ratio Y = ((source #2 block y) * 2048)/(destination block y) Default : 0x00


SRC2_SCALE (0x00AC)

RW [14:0] ratio X scaling ratio of X ## ratio Y = ((source #2 block y) * 2048)/(destination block y) Default : 0x00

Start X/Y of window #0 register R [31:26] reserved All zeros

W [25:16] window #0 Start X Start of X pixel of window #0(pixel unit)(up to 1023) Default : 0x000

R [15:10] reserved All zeros

SRC2_WINDOW0_START (0x00AD)

W [9:0] window #0 Start Y Start of Y pixel of window #0(pixel unit)(up to 1023) Default : 0x000

end X/Y of window #0 register R [31:26] reserved All zeros

W [25:16] window #0 end X end of X pixel of window #0(pixel unit)(up to 1023) Default : 0x000


SRC2_WINDOW0_END (0x00AE)

W [9:0] window #0 end Y end of Y pixel of window #0(pixel unit)(up to 1023) Default : 0x000

Startl of X/Y of window #1 register R [31:26] reserved All zeros

W [25:16] window #1 Start X Start of X pixel of window #1(pixel unit)(up to 1023) Default : 0x000


SRC2_WINDOW1_START (0x00AF)

W [9:0] window #1 Start Y Start of Y pixel of window #1(pixel unit)(up to 1023) Default : 0x000

end of X/Y of window #1 register R [31:26] reserved All zeros

W [25:16] window #1 end X end of X pixel of window #1(pixel unit)(up to 1023) Default : 0x000


SRC2_WINDOW1_END (0x00B0)

W [9:0] window #1 end Y end of Y pixel of window #1(pixel unit)(up to 1023) Default : 0x000

start address of source #2 R [31:20] reserved All zeros

SRC2_START_ADDR (0x00B1) RW [19:0] start address source #2 start address(up to 1Mbyte)

Default : 0x0000

DST_CTL

information of destination image


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RW [5:4] pixel format

“00” : RGB[5:6:5] forma “01” : reserved “10” : YUV[4:2:2] format (include OSD) “11” : YUV[4:2:2] format(no OSD) Default : 0x0


(0x00B2)

RW [1:0] destination target

“00” : to memory “01” : to LCD module “10” : to JPEG module “11” : to LCD and JPEG module Default” : 0x0

block resolution(width/height pixel unit) information R [31:26] reserved All zeros

RW [25:16] block Height processing block width(pixel unit)(up to 1023) Default : 0x000


DST_SIZE (0x00B3)

RW [9:0] block Width processing block height(pixel unit)(up to 1023) Default : 0x000

image width(pixel unit) of destination information R [31:10] reserved All zeros

DST_WIDTH (0x00B4)


start address of destination image R [31:20] reserved All zeros

DST_START_ADDR (0x00B5) RW [19:0] start address destination start address(up to 1Mbyte)

Default : 0x0000

7.8. LCD Controller Registers LCD Controller Registers is utilized to control the output format and output method to Main / Sub LCD. MV3018 is designed to support

diverse LCD timing and command type. The Command Registers described in this chapter is designed to be output to LCD automatically

by Hardware.



LCD main control registers


RW [20] LCDDATA_HOLD _CON

LCD data hold time control 1 : more internal 1 clock hold 0 : nomal operation Default (0)

RW [19:16] LWEN_High_Width LWEN High pulse width Default (0)

RW [15:12] LWEN_Low_Width LWEN Low pulse width Default (0)

RW [11] LRS_Polarity LCD_DATA LRS polarity Default (0)

RW [10] PIXEL_ALIGN LCD pixel align mode Default (1)

RW [9] BUS_ALIGN LCD data align mode Default (1)

LCD_MODE_CTL (0x00C0)

RW [8] MERGE LCD data merge mode enable Default (0)


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RW [7:6] LCD_Command_Sel

0 : command type 0 1 : command type 1 2 : command type 2 3 : command type 3 Default (0)

RW [5:4] LCD_Data_Width

0 : 8 bits 1 : 16 bits 2 : 18 bits Default (1)

RW [3:2] Target_LCD_Color

0 : 256 colors 1 : 4000 colors 2 : 65000 colors 3 : 260000 colors Default (2)

RW [1] FIFO_control

< Write operation > 1 : internal FIFO pointer clear (software set, hardware auto clear) < Read operation > 1 : TDS or Sub Scaler write image data, FIFO overflow Default(0)

RW [0] TARGET_LCD

Target LCD 0 : main LCD 1 : sub LCD Default (0)

In PREVIEW or JPEG DECODE operation, start address or LCD specific command leads the pixel image data. LCD_CMD_CTL register stores these commands or address information, command option and write enable bits. According to this register, LCD commands are outputted before previewing pixel image


RW [27] SWE13 LCD_CMD13 Write enable Default (0)

RW [26] SRS13

LCD_CMD13 RS high/low option controller 0 : RS low output 1 : RS high output Default (0)


RW [24] SRS12 LCD_CMD12 RS high/low option controller Default (0)
















LCD_CMD_CTL (0x00C1)



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Command Register

RW [31:16] LCD_CMD_13 Command Register 13 Default (Not defined)

LCD_CMD_6 (0x00C2)


Command Register


LCD_CMD_5 (0x00C3)


Command Register


LCD_CMD_4 (0x00C4)


Command Register


LCD_CMD_3 (0x00C5)


Command Register


LCD_CMD_2 (0x00C6)


Command Register


LCD_CMD_1 (0x00C7)


Command Register


LCD_CMD_0 (0x00C8)



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8. Package Information This diagram is BGA 8mm x 8mm package mechanical drawing.

9 8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

TOP VIEW

8.00

8.00

0.80REF

0.80REF

0.80

0.80

0.96 ± 0.09

0.45 ± 0.05

Seating PLANE

0.40

DIA

. TYP

A1 Ball PAD CORNER

A1 Ball PAD CORNER

BOTTOM VIEW(81 solder ball)

SIDE VIEW

0.30 ± 0.05

PCB

Solder Ball Diameter/Height

Diameter = Height

After Refow

Solder Ball HeightAfter Ball Attach

A B

C

D

Ball Pitch A B C D

0.8mm 0.4mm 0.48mm(±0.05mm) 0.36mm (±0.05mm) 0.30mm (±0.05mm)


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APPENDIX 1. Table Content Table 1 Sensor Interface Description ............................................................................................................7

Table 2 MCU Interface Description ...............................................................................................................8

Table 3 LCD Interface Description ................................................................................................................8

Table 4 System Interface Description............................................................................................................9

Table 5 Reference values for clock circuit.....................................................................................................9

Table 6 Power Description.............................................................................................................................9

Table 7 Absolute Maximum Ratings............................................................................................................11

Table 8 Operation Condition........................................................................................................................11

Table 9 Power Consumption .......................................................................................................................11

Table 10 DC Characteristics........................................................................................................................11

Table 11 HOST Interface Timing Value .......................................................................................................13

Table 12 Sensor Interface Timing Values....................................................................................................14

Table 13 HOST Interface Timing Value .......................................................................................................16

Table 14 MV Control Registers....................................................................................................................35

Table 15 Sensor Interface Registers ...........................................................................................................37

Table 16 I2C Controller Registers ...............................................................................................................38

Table 17 Primary Scaler Registers..............................................................................................................39

Table 18 Secondary Scaler Registers .........................................................................................................40

Table 19 JPEG Encoder and Decoder Registers ........................................................................................41

Table 20 JPEG Time Stamp Window Control Registers..............................................................................42

APPENDIX 2. Figure Content Figure 1 Pin Layout (TOP VIEW) ..................................................................................................................7

Figure 2 Crystal feedback circuit ...................................................................................................................9

Figure 3 The overview of chip power scheme.............................................................................................10

Figure 4 Functional Block Diagram .............................................................................................................12

Figure 5 HOST and LCD Interface ..............................................................................................................13

Figure 6 HOST Interface Timing Diagram...................................................................................................13

Figure 7 Sensor and LCD Interface ............................................................................................................14

Figure 8 Sensor Interface Timing Diagram .................................................................................................15

Figure 9 LCD Interface Timing Diagram when preview operation ..............................................................15

Figure 10 PREVIEW operation....................................................................................................................17

Figure 11 MPEGVIEW operation.................................................................................................................17

Figure 12 Decode2LCD operation ..............................................................................................................18

Figure 13 MJPEG Encoding operation........................................................................................................19

Figure 14 MJPEG Decoding operation .......................................................................................................19

Figure 15 Encode with Time Stamp Function..............................................................................................22


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Figure 16 Structure of JPEG CODEC .........................................................................................................22

Figure 17 Register classification for MV3018..............................................................................................30

MV3018SOK Specification Ver 1 -...

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