MPS Software - Hardware

SNS Integrated Control System

MPS Software - Hardware

Coles Sibley

2000-0xxxx/vlb


MPS Software - Hardware

Application Software

IOC Software

MPS Hardware

Altera FPGA Code


MPS Software

(A Separate review will be held for Software)

Database (Oracle generated files)

Run Permit System» Application software

» SNL Programs

EPICS» MPS – PMC Driver Support (Stan Brown, LANL)

» Device Support

» Automated system checkout


ORACLE

EPICS database (From Template)

RPS configuration database

Alarms» Alarm actions

Access Security Files» Group, Machine, IP, etc.

IOC startup scripts

Archive files


MPS Software – Configuration files

Mode Mask Files» Global file, Contains ALL devices

MM Verification Files» IOC Specific, Mode verses MASK

IOC specific (MPS)Hardware Configuration Files» Version #

» Software id

» Serial #

» Allowable jumpers

» IOC Heartbeats


Run Permit System – Tasks

Machine Mode Setup» Machine Dump Selection» Beam Mode Selection (Power, Width restrictions)» Verifies machine setup before changing mode

Schedules Machine Sequence» Keeps Beam, RF, Modulator gates in sync» Schedules Pulse Profiles at requested rate» Calculates / verifies table checksums (pulse to pulse)

Operator Interface to MPS» Status / Trip Reset Displays» Mask / Trip limit Controls

Hardware configuration verification» SNL task scans IOC hardware configuration for verification


Run Permit System – Mode Definitions

Machine Modes» PPS /Beam Permit

» Ion Source

» D-Plate

» Linac Dump

» Injection Dump

» Ring

» Extraction Dump

» Target

Beam Modes» Off

» Standby (RFQ RF gate)?

» Diagnostics (10 usec)



» Full Pulse Width (1 msec)

» Low Power (7.5 kW)

» Medium Power (200 kW)

» Full Power (2 MW)


RPS – Operating Envelope Calculations

Safe Operating Reqion

0.1

1

10

100

0 200 400 600 800 1000

# of turns injected

Bea

m in

ject

ion

Rat

e

7.5 kW envelope

200 kW envelope

2 MW envelope

60 Hertz

Safe Operation

Wire Scanners


Pulse width – rep rate limitations

Pulse width indicated above is the integrated on time. Actual pulse width can increase according to the duty factor.

Width(usec) 7500 2.00E+05 2.00E+06

10 19.63 60.00 60.0050 3.93 60.00 60.00

100 1.96 52.36 60.001000 0.20 5.24 52.36

Max Rep Rate @ 1 GeV, 38.2ma


RTDL Data (24 bits + 8 bit CRC per frame)

1 - Time of day 1

2 - Time of day 2

3 - Time of day 3» Diagnostics and MPS will add fast counter times to time of day for time stamps

» IOC’s will update clocks at 60 Hz

4 - Event link period » (# psecs of ring revolution)

» Used to convert counters to real time, ->IOCname:EventLinkPeriod.VAL

5 - Operating mode » Defines beam dump in use and maximum beam power or maximum pulse length,

whichever can deliver least beam power

» MPS uses for Mode Masking

6 - 60 Hz phase error» 60 hz zero crossing delta in psec, ->IOCname:LinePhaseError.VAL

» Experimenters need value

» LLRF for lookup table correction?


RTDL Data (cont)

7 thru 14 - Pulse info» 8 frames can define a "standard" pulse (See next slide)» OR we could use the Pulse ID and EPICS waveform records

15 - IOC Reset Address» Utility module uses for hard reset

16 - Data Acquisition mode» Diagnostics

17 - Pulse ID» Software input from Run Permit System» Defines one of 8 possible pulse profiles» IOC’s can use for Event triggered Record Processing

18 thru 22 - Klystron_ok» 1 bit per klystron» Transmitter and modulator is logical OR of its klystron bits

23 Kicker charge command» Beam will come in 16.6 msec (Not required if kickers are always charged)

23 through 255 etc.


Beam Pulse, RR changes

Calc Pulse LengthUpdate tables

Calc Beam PowerUptade tables

P_ID1 dataP_ID2 data

..P_ID8 beam

off

*TGT 2 MW

*Ldmp 100 usec

*Ldmp 50 usec

*Ldmp 10 usec

1 - 1 Hz2 - 60 Hz3456 - 10 Hz.10.61 - Snapshot.121 - Singleshot. etc..600

1 Tab

le p

er M

ode

RTDL1RTDL2RTDL3RTDLn

TGT 2 MW

Ldmp 100 usec

Ldmp 50 usec

Ldmp 10 usec

1 - 1 Hz2 - 60 Hz3456 - 10 Hz.10.61 - Snapshot.121 - Singleshot. etc..600

1 Tab

le pe

r Mod

e

RTDL1RTDL2RTDL3RTDLn

Online TableOffline Table

Operator

Request

*Offline Table *Online Table

RTDL MasterP_RTDL_DATA =

&RTDL[MODE][ACTIVE]


MODE Changes

HQA MPS» Beam Off (Operator)

» Key Switch change– Will turn off beam

» FPL FAULT

» Delay

» Mode change

» FPSL OK

Run Permit» Monitor MODE inputs

» Verify Equipment status

» Verify Power levels

» Verify pulse width limits

» Calculate Table checksums

» Swap RTDL Pointers


EPICS Driver Support (Initialization)

Initialization» Check configuration registers and initialize if required

» Disable MPS Outputs

» Enable MPS Mask register writes

» Download Board specific mode masks

» Verify Masks

» Set default software masks

» Disable mode mask writes

» Enable MPS outputs


EPICS Driver Support (Interrupt)

Standard EPICS IO » Set / reset software masks

» Set IOC heartbeat register as required

» Enable / Disable MPS channels from Channel Access requests

Interrupts (60 Hz) Detection of RTDL Data Valid Event» Read and verify masks

» Read and verify modes

» Read cable connection status

» Read jumper status


Interrupt routines, Device support – Cycle start

Interrupts (60 Hz) Detection of CYCLE_START Event» Read FPS counters

» Read BPS counters

» Read Fault counters

» Read Status

» “Touch” IOC heartbeat register

» Inhibit beam if required for “Chatter Faults”, N trips in M seconds, etc. (Uses ENABLE / TEST input)


MPS Top Level Screen


Run Permit System – Operator Interface


Machine Protection System Hardware

1

32

MV2100 PPC Board

PC-MIP

PC-MIP

PMC Board

Technobox 96 channelreconfigurable IO module

P14

VME 64XBackplane

VME Chassis

FPS inputs

Latched inputs

RTDL

Event Link

FPS Carrier

FPS Carrier

LatchedCarrier

B

A C

D

A C

Z

Z

MPS Transition ChassisD

MPS InterfaceChassis

#1

LEDDiagnostic

Display

160 pin J2/P2Connector

Commercial HardwareSoftware design in progress

Prototype in house(LANL design)

Prototype at SNS (Oak Ridge)


SNS-MPS-VME module Input Signals

Eight (8) positive true, fail-safe fast protect latched inputs.

Eight (8) positive true, fail-safe fast protect auto reset inputs.

One 8 - MHz carrier input, FPAR link.

One 3 - MHz carrier input, FPL link.

One 16 - MHz carrier, bi-phase-mark modulated input event link.

One 10 - MHz carrier, bi-phase-mark modulated Real Time Data Link

One positive true, fail-safe PLC card bypass.

16 – (8, FPSL,8,FPS) Software bypass enable jumpers


SNS-MPS-VME module Output Signals

One 8 - MHz carrier output, FPAR (Interlocked).

One 8 - MHz carrier output, FPAR (fan out).

One 3 - MHz carrier output, FPL (Interlocked).

One 3 - MHz carrier output, FPL (fan out)

Two – Positive LOW, FPAR (Open Collector)

Two – Positive LOW, FPAR Status


SNS-MPS-VME Chassis Indicators

One LED per MPS Input» MPS Input Channel Status

» MPS Input Signal cable status

» MPS Mode Mask

» MPS Software Mask

Carrier Status (2 in, 2 out)

RTDL, Event Link Status (2)

MPS Mode in Use (5)

3U chassis, 1U would be nice


MPS Interface Chassis front panel

FPAR FPL

INOUTBuff OP

RTDL

ELCable Status

Machine Mode

Software Mask

Mode Mask

Input Status

IOC Heartbeat

68 pin SCSI PMCFront Panel

68 Pin SCSI P2transition module

50 Pin D typeFast Protect

50 Pin D typeBeam Permit

FPAR

FPL

FPL Status FPAR Status

Front View


MPS Interface Chassis PCB

Software bypassjumpers

PLC BypassIOC Heartbeat

50 pin D-typeto BPS Wago IO

block

50 pin D-typeto FPS Wago IO

block

68 pin SCSIto Transition module

P2 connector

68 pin SCSIto front panel PMC

connector

Dual OP LemoFPL Status

Dual OP LemoFPAR Status

Ground PlaneBreak

R11

D2

gnd

R18

R1

R3 D

9D

11

R31

D14

D16R7

D4

R16

R2

gnd

R4

R35

R13R5 R6

J 4

R39 R40

R49

R51

R45

R47

R9 R17

HC

PL2600

U7

D5

R46

R48

HC

PL2600

U8

D6

R10

R12

J P1

J P3

gnd

J P9

J P11

J P13

J P15

J P6

J P8

J P10

J P12

J P14

J P16

gnd

J P17

J P18

J1

XFMR

T1

J6

XFMR

T3

54A

LS05

U23

J 13

J 8

J 9

J 2SN

75A

LS194N

U4

74LS59

9

U30

gnd

J 11

54A

LS05

U25

R37

HC

PL2600

U15

D13

R21

R23

HC

PL2600

U17

D15

R25

R38

R22

HC

PL2600

U16

D10

R24

R26

HC

PL2600

U18

D12

HC

PL2600

U20

R32

HC

PL2600

U22

HC

PL2600

U9

D7

HC

PL2600

U10

D8

R8

74LS59

9

U37

gnd

SN74A

LS165N

U27

74LS59

9

U39

7405

U29

74LS59

9

U48

gnd

J3

74LS59

9

U43

XFMR

T2

J10

XFMR

T4

SN74A

LS165N

U24

75A

LS195

U5

SN75A

LS194N

U3

SN74A

LS1035

N

U6

SN74A

LS1035

N

U2

gnd

R27

R28

gnd

R36

74H

C24

0

U38

74H

C24

0

U46

74H

C24

0

U44

LEMO_2

P4

74H

C24

0

U47

LEMO_2

P6

74H

C24

0

U31

74H

C24

0

U34

R14 R43 R44

R52

R50

J P7HC

PL2600

U11

J P5

HC

PL2600

U12

R19

D1

R20

R55

J P2

J P4

R56

IDC2X32F

P5 P3

IDC2X20F

R41 R42

R30

HC

PL2600

U19

R29

R34

HC

PL2600

U21

R33

R15

DTYPE50MP1

HC

PL2600

U13

HC

PL2600

U14

D3

gnd

R54

54A

LS05

U26

54A

LS05

U28

74LS59

9

U45

75A

LS195

U1

gnd

74LS59

9

U41

U35

SCSI68

74H

C24

0

U42

74H

C24

0

U49

74H

C24

0

U50

74H

C24

0

U40

R53

DTYPE50MP2

U36

SCSI68

VMEGround

ChassisGround


Two ground planes, connectors tie to chassis, IC’s connected to VME ground

All inputs galvanically isolated

Outputs expected to be isolated

Shields, external grounds connect to Chassis ground, not directly to PCB ground

PCB ground connects to VME ground inside rack, Single point ground

MPS Grounding

VME

VME PS

MPS Chassis


MPS PMC Module (Also nice generic digital IO module)

PCI to LocalSlave

Bus Bridge

ProgramablePLL ClockGenerator

AlteraFLEX 10K

FPGA

2 - 100 nsec5 tap Delay

lines

128K x 16SRAM

SpecialReceiver

74FCT16245Buffers

Serial EPROM

68 Pin Front PanelConnector

64 Pin (P2)Rear IO connector

32 bit PCI Bus

16 Data

96

2

322

xx MHz

1 5

18 Addr12

64

33MHz

+5

1 5

Technobox Reconfigurable Digital IO PMC


PMC Module Screen dump (Success!)

Here is a screens dump of the MPS board configuration test:

--------------------------------------------------------------------------

snsELW> Starting program.....look for menu dialog on /tyCo/0 device

BusNo = 0, DevNo = 10, FuncNo = 0

Config Word: 108310B5

Vendor ID/Device ID: 108310B5

Config Word: 8001

Config Word: 100000

Config Word: 200000

Config Word: 0

Config Word: 8101

Bus:Defice 00:00 Vendor/Device ID:00031057 Stat/Cmd: 20A00006 BAR0:00000008

Bus:Defice 00:0D Vendor/Device ID:000010E3 Stat/Cmd: 02000007 BAR0:00001000

BAR1:00800001

Bus:Defice 00:0E Vendor/Device ID:00191011 Stat/Cmd: 02800007 BAR0:00801001

BAR1:00002000

Bus:Defice 00:10 Vendor/Device ID:108310B5 Stat/Cmd: 02800003 BAR1:00008001

BAR2:00100000 BAR3:00200000 BAR5:00008101


PMC Test Screen dump

--> Configuring Altera part using PPA mode and disk file data

--> Number of conguration bytes written: 112151

--> Testing Interrupt assertion from Altera to 9050

--> Testing 256KB SRAM starting at 100000

--> First, test using data read/write of standard patterns

--> Now performing address test - writing memory

--> Now performing address test - reading memory

--> SRAM test completed

--> Now testing 'mirror' register

--> Testing MAX902 circuit

**> Error, XMDAT and XTCLK FF's are not high. Found: 0

--> Altera design revision: 1

--> Testing Altera Reset function

--> Testing 100 ns delay lines

--> [email protected] MHz:PCIC: 2E97 PLLC: 10F Ratio: 0.99974847

. . .

--> Now testing p[63..48] loopback to p[47..32] on rear panel

Tests completed

value = 0 = 0x0


Test Procedures

Functionality

Noise immunity

Crossed cables

HF noise rejection

Frequency checks

Signal cross talk measurements

Signal level immunity


MPS Hardware Status

Technobox PMC 96 channel reconfigurable IO module» Commercial item, several in house for testing

P2 Transition module (Passive)» Designed at LANL. Prototype in house for testing

MPS Input Chassis Display board» Designed at SNS. Prototype fabricated and tested

MPS Input Chassis, Interface PCB» Designed at SNS. Prototype fabricated and partially tested

WAGO IO block» Commercial item, several in house for testing

Fiber Optic transmitters, receivers» Brookhaven design, well tested, procurement in progress


MPS Altera Code

Coles Sibley

2000-0xxxx/vlb


Altera Code Development

MAX Plus II version 10.0

Hierarchical Design

Design Entry» AHDL code

» Graphical input files

» (RTDL code from utility module design)


Altera Logic Design

PCI BUSControl

MPS MODERAM

Serial IN / OUT

MPS Heartbeat

MODECompare

MPS Inputs

MPS Counters

RTDL

EVENT Link

A[32], D[16]

A[32], D[16]

f

LocalDisplay

Out LinksIn Links

MPS Inputs

RTDLInput

EventLinkinput


PCI Bus Control (AHDL code)

Version Control» Date, version, ID, etc

Status Registers» Input, output, links, etc

Mode Readback» RTDL, Event Link, Combined

(IN Use)

Fault Counters Reset Registers Enable Registers

» Input channel enable, MASK write enable

Mask Registers Mask RAM Heartbeat Registers

One register per channel

Different “WRITE_MASKS” for resets, enables, etc

RAM writes are enabled, written to, locked


MPS Mode MASK RAM (Graphical)

Uses internal 10K70 LPM_RAM» Enable writes

» Download Mode Masks

» Verify Mode Masks

» Disable writes

Initializing RAM disables MPS carriers

Each RAM is 16 bits X 256 words

HI byte = MODE, Low byte = ~MODE

MODE Mask integrity verified pulse to pulse» MM_OK = MM[15..8] AND ~MM[7..0]


RTDL Receive Module (graphic and AHDL code)

Machine Mode, RTDL Frame # 5

Inputs » 10 MHz RTDL data» Sys reset

Module outputs» Data Valid» Xmiterr» Parameter ID (Frame #)» Data (24 bits)» CRC Error» XDATCLK» Frequency check

XMITERR – Aborts Beam

CRC Error – Aborts Beam

Frequency checks

Data -> 24 bits

High Middle Low

/(MODE) (MODE^2+1) (MODE)


Event Link Receiver (AHDL Code)

Similar to RTDL

Inputs» Event Link

» PLL Clock

» Delayed Data

Outputs» Event Valid

» Event Strobe (One per Mode)

» Xmitt error

» Frequency check


Mode Compare (Graphical)

Verifies Event_Link_MODE == RTDL_MODE 9 msec Heartbeat from Event link (Should get new mode and

RTDL at 120 Hz) Compares Time Of Day different from previous RTDL frame (No

stale data) Inputs

» RTDL data» Event strobe» Time of Day

Outputs» Mode OK» MODE


MPS Input Circuit (Graphical)

mps_reset[7]

mps_input[7]

mps_mm[7] mps[7]mps_sw_mask[7]

mps_jump[7]

mps_reset[7..0]

C

Q

K

JP

VCCmps_mm[7..0]

mps_sw_mask[7..0]

mps_input[7..0]

mps_jump[7..0]

+ Frequency verification Circuit on input carriers


MPS Output link logic (Graphical)

mps[7]

mps_program[1]

mps[3]

mps[5]

mps[4]

mps[6]

mps[1]

mps[0]

mps[2]

FAST_in_link

mps_mode_ok

IOC_Enable

p_mps_link_out

ioc_hb_jmp

ioc_hb_status

mps_mm_ok

mps_program[15..0]PLC_bypass

7

mps_input_stat

mps_sum


Fault Timer Circuits (Graphical)

Latches 16 MHz counter to record fault time

Latched on CYCLE_START Event, counter cleared at

CYCLE_START +1

Inputs» Input faults (from Input circuit)

» RTDL, Event Link Errors

» Fast Carrier Input fault detect

Outputs» Fault counter registers

» (MSB indicates input is faulted or not)


Serial IN-OUT (Graphical)

Sends serial data for display

Parallel Inputs, Serial Outputs» SW Mask

» Mode Mask

» Channel Status

» Link status

Serial Inputs, Parallel Outputs» Input cable status


MPS Heartbeat (Graphical)

Shuts off beam if IOC loses heartbeat (Reboot, crash, etc)

Inputs» Heartbeat Time

» IOC HB signal

» Reset

» HB Jumper

Outputs» Keep alive

» Status


FPGA Status

CODE approximately 75% complete» Basic functionality complete

10K70 Resources are:» ** DEVICE SUMMARY **

» Chip/ Input Output Bidir Memory Memory LCs

» POF Device Pins Pins Pins Bits % Utilized LCs % Utilized

» mps_test EPF10K70RC240-3 45 41 38 6144 33 % 2082 55 %

» User Pins: 45 41 38

Next Step» Finish Event Link

» Add timeouts, hardware error checks

» Run Simulations

MPS Software - Hardware

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