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MPC8555EConfigurable Development System
Reference Manual
SupportsMPC8555EMPC8541E
MPC8555CDSx3RMRev. 1, 11/2006
MPC8555E Configurable Development System Reference Manual, Rev. 1
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ContentsParagraphNumber Title
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Contents
About This Book
Audience .......................................................................................................................... xiiiOrganization..................................................................................................................... xiiiSuggested Reading........................................................................................................... xiv
General Information..................................................................................................... xivSignal Conventions .......................................................................................................... xivAcronyms and Abbreviations .......................................................................................... xiv
Chapter 1 Introduction
1.1 Background...................................................................................................................... 1-11.2 Scope................................................................................................................................ 1-11.3 Overview.......................................................................................................................... 1-11.3.1 Features........................................................................................................................ 1-21.3.2 Diagrams...................................................................................................................... 1-4
Chapter 2 Quick Start-Up Guide
2.1 Hardware List .................................................................................................................. 2-12.2 Hardware Installation....................................................................................................... 2-12.3 Quick Start-Up ................................................................................................................. 2-52.4 How to Re-Flash U-Boot/Linux Image Using U-Boot .................................................... 2-62.5 Default Switch Configuration Table ................................................................................ 2-7
Chapter 3 CDS Carrier Architecture
3.1 Overview.......................................................................................................................... 3-13.1.1 Board Measurements ................................................................................................... 3-13.1.2 Block Diagrams ........................................................................................................... 3-13.2 Carrier Pinouts ................................................................................................................. 3-33.3 System Logic ................................................................................................................... 3-33.3.1 System Address Map ................................................................................................... 3-43.3.2 System Logic Registers ............................................................................................... 3-53.3.2.1 Version Register (CM_VER)................................................................................... 3-53.3.2.2 General Control Register (CM_CSR)...................................................................... 3-6
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3.3.2.3 Reset Control Register (CM_RST).......................................................................... 3-63.3.2.4 LED Data Register................................................................................................... 3-73.3.2.5 PCI Control/Status Register..................................................................................... 3-73.3.2.6 DMA Control Register ............................................................................................ 3-83.4 CPM Connections ............................................................................................................ 3-93.5 ATM Interfaces .............................................................................................................. 3-123.6 Ethernet Ports................................................................................................................. 3-123.7 Local Bus ....................................................................................................................... 3-153.7.1 NCDS Local Bus Signals........................................................................................... 3-173.8 Clock.............................................................................................................................. 3-183.9 PCI-X ............................................................................................................................. 3-193.9.1 PCI Arbitration .......................................................................................................... 3-203.9.2 PCI-X System Control ............................................................................................... 3-213.10 Exceptions...................................................................................................................... 3-213.10.1 Software Triggered Exceptions.................................................................................. 3-233.11 Reset............................................................................................................................... 3-233.11.1 Software Triggered Resets ......................................................................................... 3-243.12 I2C ................................................................................................................................. 3-253.13 Configuration ................................................................................................................. 3-263.14 Power ............................................................................................................................. 3-283.14.1 +2.5-V Power............................................................................................................. 3-293.14.2 Power Management ................................................................................................... 3-293.15 Diagnostic Features........................................................................................................ 3-293.15.1 Analyzer Headers....................................................................................................... 3-293.15.2 Remote Debug Header............................................................................................... 3-333.15.3 Monitoring LEDs....................................................................................................... 3-33
Chapter 4 CDS Daughtercard Architecture
4.1 Mechanical Architecture.................................................................................................. 4-14.2 CDS Daughtercard (CDC) Block Diagram ..................................................................... 4-44.3 Processor .......................................................................................................................... 4-44.4 DDR Memory .................................................................................................................. 4-44.4.1 DDR Interface Termination ......................................................................................... 4-74.4.2 Recommended Part Numbers ...................................................................................... 4-84.5 Local Bus Interface .......................................................................................................... 4-84.5.1 Local Bus SDRAM Memory ..................................................................................... 4-104.6 Passive Connections ...................................................................................................... 4-104.7 Carrier Pinouts ............................................................................................................... 4-124.8 Clock.............................................................................................................................. 4-12
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4.9 PCI/PCI-X...................................................................................................................... 4-134.10 Reset............................................................................................................................... 4-134.11 Exceptions...................................................................................................................... 4-144.12 I2C ................................................................................................................................. 4-154.13 Configuration ................................................................................................................. 4-164.14 Power ............................................................................................................................. 4-164.14.1 Processor Core Power................................................................................................ 4-174.14.2 DDR VREF/Vt Power ............................................................................................... 4-184.15 Diagnostic Features........................................................................................................ 4-184.15.1 Logic Analyzer Header.............................................................................................. 4-184.15.2 JTAG Header ............................................................................................................. 4-194.15.3 LEDs .......................................................................................................................... 4-204.15.4 Test Points.................................................................................................................. 4-21
Chapter 5 Arcadia Motherboard Architecture
5.1 Features ............................................................................................................................ 5-15.2 Configurations ................................................................................................................. 5-25.2.1 CDS Motherboard........................................................................................................ 5-25.3 Architecture ..................................................................................................................... 5-35.4 Omni Bus ......................................................................................................................... 5-45.4.1 Parallel RapidIO .......................................................................................................... 5-55.4.2 Serial RapidIO ............................................................................................................. 5-65.4.3 PCI Express.................................................................................................................. 5-65.5 PCI/PCI-X Bus ................................................................................................................ 5-75.5.1 PCI Arbitration ............................................................................................................ 5-85.5.2 PCI Host Mode .......................................................................................................... 5-105.5.3 PCI Bridge ................................................................................................................. 5-105.5.4 PCI Interrupts............................................................................................................. 5-105.5.5 PCI Interrupt Bridge .................................................................................................. 5-135.5.6 PCI Configuration...................................................................................................... 5-135.5.7 PrPMC Connector...................................................................................................... 5-145.6 System Control .............................................................................................................. 5-145.7 Clocking......................................................................................................................... 5-155.8 Reset............................................................................................................................... 5-175.9 Power ............................................................................................................................. 5-185.10 Diagnostic Features........................................................................................................ 5-195.10.1 LEDs .......................................................................................................................... 5-195.10.2 JTAG.......................................................................................................................... 5-20
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5.11 Configuration ................................................................................................................. 5-215.11.1 Power Supply Force Header ...................................................................................... 5-235.12 Mechanical..................................................................................................................... 5-235.13 Motherboard Dimensions .............................................................................................. 5-245.14 Placement....................................................................................................................... 5-25
Chapter 6 CDS IOCard Architecture
6.1 Mechanical Properties...................................................................................................... 6-16.2 IOCard Connector............................................................................................................ 6-26.3 IOCard Connector Pinout ................................................................................................ 6-36.4 IO Power .......................................................................................................................... 6-3
Chapter 7 uTCOM Architecture
7.1 Overview.......................................................................................................................... 7-17.2 Mechanical Architecture.................................................................................................. 7-27.2.1 uTCOM Connector ...................................................................................................... 7-27.2.2 uTCOM Connector Signals ......................................................................................... 7-27.3 uTCOM Pinout ................................................................................................................ 7-3
Appendix A Revision History
A.1 Changes From Revision 0 to Revision 1 ........................................................................ A-1
Appendix B Pinouts
B.1 Carrier/DaughterCard Connectors Pinout........................................................................B-1B.2 IOCard Connector Pinout ................................................................................................B-5B.3 uTCOM Connector Pinout...............................................................................................B-6
Appendix C CDS Carrier BOM, Rev. 1.2
Appendix D CDS Carrier Schematics, Rev. 1.2
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Appendix E CDS Carrier BOM, Rev. 1.3
Appendix F CDS Carrier Schematics, Rev. 1.3
Appendix G CDS CDC BOM
Appendix H CDS CPU Schematics (CDC)
Appendix I CDS I/O Board Schematics
Appendix J CDS uTCOM Schematics
Appendix K CDS Arcadia BOM
Appendix L CDS Arcadia X3 Schematics
Glossary
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Figures
1-1 Carrier Block Diagram (Configuration 1)............................................................................... 1-41-2 Carrier Block Diagram (Configuration 2)............................................................................... 1-51-3 Daughtercard Block Diagram ................................................................................................. 1-52-1 Inserting Memory Module ...................................................................................................... 2-22-2 Removing Chassis Thumb Screws ......................................................................................... 2-22-3 Removing Chassis Top Cover................................................................................................. 2-22-4 Removing Chassis Side Panel................................................................................................. 2-32-5 Removing PCI Slot Bracket Screws ....................................................................................... 2-32-6 Install Carrier Card into PCI Slot............................................................................................ 2-42-7 Guide Pin Alignment .............................................................................................................. 2-42-8 Install PCI Bracket Screws ..................................................................................................... 2-53-1 Carrier Block Diagram (Configuration 1)............................................................................... 3-23-2 Carrier Block Diagram (Configuration 2)............................................................................... 3-33-3 Version Register (CM_VER) .................................................................................................. 3-53-4 Reset Control Register (CM_CSR)......................................................................................... 3-63-5 Reset Control Register (CM_RST) ......................................................................................... 3-63-6 Reset Control Register (CM_LED)......................................................................................... 3-73-7 PCI Control/Status Register (CM_PCI) .................................................................................. 3-73-8 Reset Control Register (CM_DMA) ....................................................................................... 3-83-9 CE/CPM Architecture ............................................................................................................. 3-93-10 CDS ATM Architecture ........................................................................................................ 3-123-11 CDS Ethernet Architecture (Configuration 1) ...................................................................... 3-143-12 CDS Ethernet Architecture (Configuration 2) ...................................................................... 3-143-13 CDS Local Bus Architecture................................................................................................. 3-163-14 CDS Clock Architecture ....................................................................................................... 3-193-15 CDS PCI Architecture........................................................................................................... 3-203-16 CDS Exception Architecture................................................................................................. 3-213-17 CDS Carrier Reset Architecture............................................................................................ 3-233-18 CDS Carrier I2C Architecture............................................................................................... 3-253-19 CDS Configuration Logic ..................................................................................................... 3-273-20 CDS Power Architecture....................................................................................................... 3-284-1 Daughtercard Placement ......................................................................................................... 4-24-2 CDC with 783 BGA Processor Example ................................................................................ 4-34-3 Daughtercard Block Diagram ................................................................................................. 4-44-4 CDS Memory Architecture ..................................................................................................... 4-54-5 CDC Memory Termination ..................................................................................................... 4-74-6 CDS Local Bus Architecture................................................................................................... 4-94-7 CDS Dual-PCI Architecture.................................................................................................. 4-13
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4-8 CDS Daughtercard Reset Architecture ................................................................................. 4-144-9 CDS Daughtercard I2C Architecture .................................................................................... 4-155-1 CDS-Compatible Arcadia Block Diagram.............................................................................. 5-35-2 Arcadia RapidIO Port Connections......................................................................................... 5-55-3 Arcadia PCI Arbitration Domains........................................................................................... 5-95-4 Arcadia PCI Interrupts Domains........................................................................................... 5-115-5 Arcadia PCI Clock Domains................................................................................................. 5-155-6 Arcadia Clock Architecture .................................................................................................. 5-175-7 Arcadia Reset Architecture ................................................................................................... 5-185-8 Arcadia ATX Chassis Mounting Holes ................................................................................. 5-245-9 Component Placement .......................................................................................................... 5-256-1 CDS IOCard Block Diagram .................................................................................................. 6-16-2 CDS IOCard Physical Dimensions ......................................................................................... 6-27-1 CDS uTCOM/TCOM Interface .............................................................................................. 7-1
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Tables
2-1 Default Status of Processor Board (CPU Card) Switches....................................................... 2-72-2 Default Status of Carrier Board Switches (Configuration 1) .................................................. 2-92-3 Default Status of Arcadia Board Switches (Arcadia C3.n)................................................... 2-103-1 Memory Map........................................................................................................................... 3-43-2 Cadmus Address Map ............................................................................................................. 3-53-3 CM_VER Field Descriptions .................................................................................................. 3-53-4 CM_CSR Field Descriptions .................................................................................................. 3-63-5 CM_RST Field Descriptions................................................................................................... 3-63-6 CM_LED Field Descriptions .................................................................................................. 3-73-7 CM_PCI Field Descriptions.................................................................................................... 3-83-8 CM_DMA Field Descriptions................................................................................................. 3-93-9 CDS CPM/CE Connection Options ...................................................................................... 3-103-10 CPM Port Routing for FCC1 in ATM622/UTOPIA 8 Mode................................................ 3-103-11 CPM Port Routing for FCC2 in ATM155 Mode................................................................... 3-103-12 CPM/CE Switch Summary ................................................................................................... 3-113-13 ATM Port Overview.............................................................................................................. 3-123-14 PHY Address Options (Configuration 1) ............................................................................ 3-133-15 CDS TSEC Interface Summary ............................................................................................ 3-153-16 CDS Carrier Local Bus Signals ............................................................................................ 3-163-17 CDS Cxx Local Bus Signals ................................................................................................ 3-173-18 CLA Mapping ....................................................................................................................... 3-183-19 CDS Clock Requirements Summary..................................................................................... 3-193-20 CDS PCI Properties .............................................................................................................. 3-203-21 CDS Exception Properties .................................................................................................... 3-223-22 CDS Reset Sources ............................................................................................................... 3-243-23 CDS Reset Outputs ............................................................................................................... 3-243-24 CDS I2C Bus Properties ....................................................................................................... 3-263-25 CDS Configuration Parameters............................................................................................. 3-263-26 CDS Available Power ........................................................................................................... 3-283-27 CDS Local Bus ‘STAT’ Header Definition........................................................................... 3-303-28 CDS Local Bus ‘ADDR’ Header Definition......................................................................... 3-313-29 CDS Local Bus ‘DATA’ Header Definition .......................................................................... 3-323-30 CDS Remote Header ............................................................................................................. 3-333-31 CDS Debug Header Definition ............................................................................................. 3-333-32 CDS LEDs............................................................................................................................. 3-334-1 CDS DDR SDRAM Properties ............................................................................................... 4-64-2 CDS DDR SDRAM Compatibility ......................................................................................... 4-84-3 CDS Daughtercard Local Bus Signals .................................................................................. 4-10
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4-4 CDS Daughtercard Connector Overview.............................................................................. 4-114-5 CDC Clocks .......................................................................................................................... 4-124-6 CDC PCI2 IDSEL Mapping ................................................................................................. 4-134-7 CDS Exception Properties .................................................................................................... 4-154-8 CDS Daughtercard I2C Bus Properties................................................................................. 4-164-9 CDC Available Power ........................................................................................................... 4-174-10 CDC VDD (Vcore) Encoding Table ..................................................................................... 4-174-11 CDC ADC Current Measurement Conversion Table............................................................ 4-184-12 CDS Daughtercard P6860 Analyzer Header Definition ....................................................... 4-194-13 CDS JTAG Header................................................................................................................ 4-194-14 CDS COP Header Definition ................................................................................................ 4-204-15 CDC Diagnostic LEDs.......................................................................................................... 4-204-16 CDS Test Point List............................................................................................................... 4-215-1 Arcadia Architecture Feature Summary ................................................................................. 5-45-2 Arcadia Parallel RapidIO Connector Definition..................................................................... 5-55-3 Arcadia Serial RapidIO Connector Definition........................................................................ 5-65-4 Arcadia PCIExpress Connector Definition ............................................................................. 5-65-5 Arcadia PCIBus Name Examples ........................................................................................... 5-85-6 PCI Arbitration Ports .............................................................................................................. 5-95-7 Arcadia 3.1 Interrupt Assignments ....................................................................................... 5-125-8 PCI Configuration Addresses................................................................................................ 5-145-9 PCI Clock Domain Summary ............................................................................................... 5-165-10 Arcadia Slot Power Availability............................................................................................ 5-195-11 Arcadia Diagnostic LEDs ..................................................................................................... 5-195-12 Arcadia Diagnostic LEDs: PCI Speed Encoding.................................................................. 5-205-13 Arcadia JTAG Chain ............................................................................................................. 5-205-14 Arcadia Configuration Switches ........................................................................................... 5-215-15 Arcadia Power Supply Force Header.................................................................................... 5-236-1 CDS IOCard Connector Details .............................................................................................. 6-27-1 CDS uTCOM Connector Details ............................................................................................ 7-27-2 uTCOM Pin Routing to TCOM Board (P1 Connector) .......................................................... 7-37-3 uTCOM Pin Routing to TCOM Board (P2 Connector) .......................................................... 7-5B-1 Daughtercard Connector (Left) Definition and Pinout ...........................................................B-1B-2 Daughtercard Connector (Right) Definition and Pinout .........................................................B-2B-3 Daughtercard High-Speed Connector Definition and Pinout .................................................B-3B-4 IOCard Connector Definition and Pinout ...............................................................................B-5B-5 uTCOM Connector (Right) Definition and Pinout .................................................................B-6F-1 Differences Between Carrier Card Rev. 1.2 and Rev. 1.3....................................................... F-1
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About This BookThe primary objective of this reference manual is to define the functionality of the MPC8555E configurable development system (CDS). It is also intended to describe in detail the configurability of the CDS through the description of individual components and their interchangeability. Included is detailed descriptions of the physical design, device architecture, and testing/debugging procedures.
AudienceIt is assumed that the reader understands operating systems, microprocessor system design, and the basic principles of RISC processing.
OrganizationFollowing is a summary and a brief description of the major parts of this reference manual:
• Chapter 1, “Introduction,” provides a high-level description of features and functionality of the CDS. Included is a list of the configurable features, as well as basic block diagrams.
• Chapter 2, “Quick Start-Up Guide,” describes step-by-step how to bring up a CDS development board.
• Chapter 3, “CDS Carrier Architecture,” describes in detail the CDS carrier system. It describes the physical layout and assembly, as well as basic and detailed system architecture. It elaborates on usage and testing/debugging procedures.
• Chapter 4, “CDS Daughtercard Architecture,” covers the CDS daughtercard design in more detail. It describes the physical layout as well as part connections and device interfaces. It includes a detailed description of the system architecture, along with the device configuration and debugging procedures.
• Chapter 5, “Arcadia Motherboard Architecture,” describes the design information on the Arcadia reference platform.
• Chapter 6, “CDS IOCard Architecture,” describes in detail the IOCard. It elaborates on the physical architecture and device connections, as well as the power management and usage.
• Chapter 7, “uTCOM Architecture,” describes the uTCOM interface, as well as its physical properties.
• Appendix A, “Revision History,” describes the major differences between revisions of this reference manual.
• Appendix B, “Pinouts,” contains detailed pinout specifications for the CDS. It includes:— Carrier/daughtercard connectors pinout— IOCard connector pinout— uTCOM connector pinout
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• Appendix C, “CDS Carrier BOM, Rev. 1.2”• Appendix D, “CDS Carrier Schematics, Rev. 1.2” • Appendix E, “CDS Carrier BOM, Rev. 1.3” • Appendix F, “CDS Carrier Schematics, Rev. 1.3” • Appendix G, “CDS CDC BOM”• Appendix H, “CDS CPU Schematics (CDC)”• Appendix I, “CDS I/O Board Schematics”• Appendix J, “CDS uTCOM Schematics”• Appendix K, “CDS Arcadia BOM”• Appendix L, “CDS Arcadia X3 Schematics”• This reference manual also includes a glossary.
Suggested ReadingThis section lists additional reading that provides background for the information in this manual as well as general information about the architecture.
General Information
The following documentation provides useful information about the CDS architecture:• The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition,
by International Business Machines, Inc. For updates to the specification, see http://www.austin.ibm.com/tech/ppc-chg.html.
• Computer Architecture: A Quantitative Approach, Third Edition, by John L. Hennessy and David A. Patterson.
• Computer Organization and Design: The Hardware/Software Interface, Second Edition, by David A. Patterson and John L. Hennessy.
Signal Conventions
OVERBAR An overbar indicates that a signal is active-low.lowercase_italics Lowercase italics is used to indicate internal signals.lowercase_plaintext Lowercase plain text is used to indicate signals that are used for configuration.
Acronyms and AbbreviationsTable i contains acronyms and abbreviations used in this document.
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Table i. Glossary of Terms
Term Description
ATM Asynchronous transfer mode
CARRIER HIP-compliant HIPcard such as CDS, Elysium, etc.
CDC CPU daughtercard
CDS Configurable development system; customer development system
CPM Communications processing machine
Daughtercard CPU-specific daughtercard which connects to a carrier board
DDR Double-data rate
GMII Gigabit media-independent interface
HIP Hardware interoperability platform
IOCARD IO breakout card for a carrier board
LB Local bus (that is, Flash/SRAM/SDRAM interface)
MAC Media access control
MII Media-independent interface
Motherboard HIP-compliant motherboard such as Arcadia, etc.
OUI Organizationally unique identifier
PC-1600 DDR providing 1600 MB/s bandwidth (@8 bytes/clk = 200 MHz)
PC-2100 DDR providing 2100 MB/s bandwidth (@8 bytes/clk = 266 MHz)
PHY Physical interface
PM Performance monitor
RIO RapidIO
TSEC Triple-speed Ethernet controller (10/100/1G speeds)
TWG Technical working group
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Chapter 1 Introduction
1.1 BackgroundThe configurable development system (CDS) was developed to support a wide range of Power Architecture™ processors, such as the MPC8555E and the MPC8541E. . The system is primarily a development and evaluation system, which is enhanced by its modular design, making it highly configurable.
1.2 ScopeThis reference manual describes the Freescale CDS development platform. It provides details on the MPC8555E CDS hardware configuration and functionality. It is intended primarily as a guide for hardware and software designers.
1.3 OverviewThe CDS system is the middle ground between evaluation and test boards. It is more configurable and flexible than an evaluation board, but it is not as configurable as a test board, in which every component can be tested and examined. Where it lacks configurability, its design has options for the most common settings.
Two MPC8555E CDS development system configurations are described. The configurations consist of different board revisions which are referenced throughout this manual as Configuration 1 or Configuration 2. The configurations are:
• Configuration 1— Arcadia, Rev. 3.1— Carrier card, Rev. 1.2— CPU card, Rev. 1.1— I/O card, Rev. 1.1
• Configuration 2— Arcadia, Rev. 3.1— Carrier card, Rev. 1.3— CPU card, Rev. 1.1
Refer to Appendix F, “CDS Carrier Schematics, Rev. 1.3,” Table F-1, for hardware differences between carrier card, Rev. 1.2 and Rev. 1.3.
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1.3.1 Features
NOTEThe CDS system can be configured to boot as MPC8555E or MPC8541E. The CDS system by default is configured as MPC8555E. To evaluate the CDS system as MPC8541E, refer to Section 2.5, “Default Switch Configuration Table,” switch-4, bit-4 on CPU card.
A CDS system includes the following features:• Processor-specific daughtercard, featuring
— One or more Freescale MPC8555E processor(s)— ECC-compatible DDR-I (processor-specific type)— Test features (JTAG, P6880 passive probe for critical routes only)
– P6880 ‘banjo’ header probing critical signals only– All other debug is via carrier or DIMM debug module
— Local support for secondary interfaces (such as PCI) as needed– PCI32 header (3.3 V, 32-bit, PCI-X, 33/66 MHz compatible) where required
— Local switching power supply, supplying VDD (VCORE)– Supplies up to 15 W (~1.1 V at 12 A)– Derivable from +5 or +3.3 V (not +12 V)– Programmable voltage via I2C configuration
— I2C bus– ID EEPROM (256b) for card at 0x50– Configurable EEPROM (8K) for CPU at 0x57– Memory SPD EEPROM for memory at 0x51– Voltage monitoring– Configuration control
— Local bus generation– Includes any necessary demultiplexing– Local SDRAM support (as appropriate)
— High-speed/high-density connectors for all CPU signals except core power and memory— Configuration options
– Switch programmable defaults– I2C remote configuration/override
— Debug support– JTAG (COP) header– Monitoring LEDs
• Carrier board— Supports numerous processor daughtercards
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— Supports two Ethernet ports on the carrier card at MII/GMII, and two Ethernet ports on the I/O adapter at MII/GMII, 10/100 or 1G rates (Configuration 1).
NOTEIn Configuration 1, Ethernet port #4 on the I/O card is not functional.
— Supports all four Ethernet ports on the carrier card. MII/GMII on Ethernet ports #1 and #2. RGMII on Ethernet ports #3 and #4, 10/100 or 1G rates (Configuration 2).
— Quickswitch-controlled routing of selected CPM signals between uTCOM header and local peripherals (optical ATM OC3/OC12 and/or 10/100 console Ethernet).
— UTOPIA L2/AdTech connector for OC12 ATM port— Supports USB connector (as wires only—USB PHY is on the daughtercard, if needed)— Supports serial port for Linux/U-Boot console I/O— Differential probing on receive path with Tek P6880— PCI/PCI-X 32/64 bits, 33/66 MHz
NOTEPCI arbitration is not supported on the carrier card. The MPC8555CDS board does not support PCI-X mode.
— Includes IO adapter board (Configuration 1)
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1.3.2 Diagrams
Figure 1-1 is a diagram of the CDS system for Configuration 1.
Figure 1-1. Carrier Block Diagram (Configuration 1)
CPUDaughtercard
PCI-X+2.5-VPower
LocalClock
H/SClock
Flash
GBit#1
GBit#2
UART
GBit#3
RST
10/100#4
USB
QuadPHY
IOCard
NVRAM
DEBUG
MUX uTCOM
OC3ATMPHY
OC12ATMPHY
AdTech
BU
F
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Figure 1-2 is a diagram of the CDS system for Configuration 2.
Figure 1-2. Carrier Block Diagram (Configuration 2)
Figure 1-3 is a diagram of a CDS daughtercard, or a CDC.
Figure 1-3. Daughtercard Block Diagram
This representation shows only one design, other daughtercards can be designed for different CPUs.
CPUDaughtercard
PCI-X+2.5-VPower
LocalClock
H/SClock
FlashGBit#2
GBit#1
QuadPHY
NVRAM
DEBUG
MUX uTCOM
OC3ATMPHY
OC12ATMPHY
AdTech
BU
F
GBit#3
GBit#4
UART
PCI/X
Vtt
DDR SDRAM DIMM
VTTPower
CorePower
JTAG
I2C ID
DEBUGCPU
or
CPU/Bridge
LBIF
Header(Left)
CFG
Header(Right)
Local Mem
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Chapter 2 Quick Start-Up GuideThis chapter provides a step-by-step guide for bringing up a CDS.
2.1 Hardware ListThe hardware configurations consist of different board revisions which are referenced throughout this manual as Configuration 1 or Configuration 2. Refer to Appendix F, “CDS Carrier Schematics, Rev. 1.3,” Table F-1, for hardware differences between carrier card, Rev. 1.2 and Rev. 1.3. The configurations are:
• Configuration 1— Arcadia, Rev. 3.1— Carrier card, Rev. 1.2— CPU card, Rev. 1.1— I/O card, Rev. 1.1
• Configuration 2— Arcadia, Rev. 3.1— Carrier card, Rev. 1.3— CPU card, Rev. 1.1
The CDS system is installed in a PC box and includes a power supply. The CDS system is preloaded with U-boot and Linux BSP.
2.2 Hardware Installation Remove the CDS system chassis from the cartons and perform the following steps:
NOTEThe carrier card and processor card are packaged together.
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1. Insert memory module, noting the correct KEYING orientation, and snap into the socket. See Figure 2-1.
Figure 2-1. Inserting Memory Module
2. To remove the top chassis cover, stand chassis on end and remove the two top thumb screws located in back of the chassis. See Figure 2-2.
Figure 2-2. Removing Chassis Thumb Screws
3. Slide top cover toward the back while lifting, and remove. See Figure 2-3.
Figure 2-3. Removing Chassis Top Cover
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4. Remove both side covers by lifting straight up. See Figure 2-4.
Figure 2-4. Removing Chassis Side Panel
5. Now lay chassis on the side with the motherboard exposed.6. Remove PCI bracket screws. See Figure 2-5.
Figure 2-5. Removing PCI Slot Bracket Screws
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7. Insert carrier card assembly into the PCI Slot 1. See Figure 2-6 and Figure 2-7.
NOTEThe alignment pins to guide the carrier card into the proper position are on the Arcadia motherboard.
Figure 2-6. Install Carrier Card into PCI Slot
Figure 2-7. Guide Pin Alignment
8. Push the carrier card assembly down firmly to fully seat connectors.
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9. Re-install the PCI bracket screws. See Figure 2-8.
Figure 2-8. Install PCI Bracket Screws
2.3 Quick Start-Up1. Connect the CDS system to a 120-V AC power source. (For outside the U.S., a 240-V power supply
must be installed in the box and connected to an AC power source.)2. Connect the null modem serial cable between the carrier board COM1 port and the PC workstation
serial port (COM1 or COM2).3. Start up the terminal emulator program, (i.e., HyperTerminal) and setup the PC terminal program
to use the following settings:— Bits per second: 115200— Data bits: 8— Parity: none— Stop bits: 1— Flow control: none
4. Turn on the CDS system by pushing the power switch on the front of the PC box.5. After power-up by default, the system autoboots in Linux. However, if the autoboot is halted, the
user should see the U-boot prompt. The following is only an example of a U-boot screen dump at bootup. The actual screen dump may vary depending on specific system configurations.
U-Boot 1.1.3 (FSL Development) (Oct 27 2006 - 10:43:18)
CPU: 8555, Version: 1.1, (0x80790011)
Core: E500, Version: 2.0, (0x80200020)Clock Configuration:
CPU: 833 MHz, CCB: 333 MHz,
DDR: 166 MHz, LBC: 83 MHz
L1: D-cache 32 kB enabled I-cache 32 kB enabled
Board: CDS Version 0x13
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CPU Board Revision 0.0 (0x0000) PCI1: 32 bit, 33 MHz, sync
PCI2: 32 bit, 66 MHz, async
I2C: readyDRAM: Initializing
SDRAM: 64 MB
DDR: 256 MB
FLASH: 16 MBL2 cache 256KB: enabled
In: serial
Out: serialErr: serial
Net: TSEC0: PHY is Marvell 88E1145 (1410cd4)
TSEC1: PHY is Marvell 88E1145 (1410cd4)TSEC0, TSEC1
The IP address of the board is currently set to 169.254.113.58
The MAC address is 00:04:9F:00:28:C8If they don't match your network environment, please change them in U-Boot and kernel manually.Hit any key to stop autoboot: 0
=>
6. By typing ‘boot’ at command prompt the system will boot to Linux.
2.4 How to Re-Flash U-Boot/Linux Image Using U-BootThere are two banks of Flash memory in the CDS system, and are selected by switch 2, bits 1 and 2 on the carrier card. Following are the instructions to program the U-boot binary file Linux image into the bank of Flash memory as sent from the factory:
• To re-flash the U-boot follow steps 1 to 7.• To re-flash Linux image follow steps 8 to 12.• Requirement:
— A running TFTP server who hosts the u-boot.bin file— The running U-boot should have the correct ‘ipaddr’, ‘serverip’, and ‘netmask’ parameters.
The parameters can be modified by command ‘setenv <VARIABLE NAME> <VARIABLE VALUE>’
1. Boot the CDS with U-boot, hit any key to stop the timer2. tftp 1000000 u-boot.bin3. prot off all4. erase fff80000 ffffffff5. cp.b 1000000 fff80000 800006. reset7. The new U-boot will boot up, hit any key to stop the timer8. tftp 1000000 vmlinux.2199. tftp 2000000 ramdisk.u-boot
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10. erase ff800000 ffdfffff11. cp.b 1000000 ff800000 1fffff12. cp.b 2000000 ffa00000 3fffff
Steps 13 to 16 are required to update the environment variables.13. setenv bootargs root=/dev/ram rw console=ttyS1,11520014. setenv bootcmd bootm ff800000 ffa0000015. saveenv16. reset
2.5 Default Switch Configuration TableThe CDS system has several options for the switch settings to allow users to easily change the configuration. Table 2-1, Table 2-2, and Table 2-3 show the default switch settings for targeted applications. For the processor board (CPU card) switches shown in Table 2-1 and the carrier board switches shown in Table 2-2, in order to set an option value to 1, set the switch to ON; to set an option value to 0, set the switch to OFF. For the Arcadia board switches shown in Table 2-3, in order to set an option value to 1, set the switch to ON; to set an option value to 0, set the switch to OFF.
Table 2-1. Default Status of Processor Board (CPU Card) Switches
SW Bit NameDefault (1 = ON)
Note
1 1 PCI1 bus impedance 1 0 25 Ω1 42 Ω (Default)
2 PCI1 debug enable 1 Default
3 DDR debug enable 1
4 Memory debug enable 1
5 Local bus hold LWE[0:1] 1 00 One extra delay01 Two extra delays10 Three extra delays11 Default/specified AC timing
6 1
7 PCI1 clock select 1 1 Sync (use SYSCLK) default0 Async (use PCI1CLK)
8 PCI2 clock select 0 1 Sync (use SYSCLK) 0 Async (use PCI2CLK) default
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2 1 Core voltage 1 10011 1.200 V
2 0
3 0
4 1
5 1
6 Local bus size 1 0 8-bit Flash1 16-bit Flash (default)
7 Memory ECC Mux 1 0 Switch MECC to debug header1 Connect MECC to DIMM, normally
8 PCI dual 1 1 PCI1 is 32-bit, PCI2 is 32-bit0 PCI1 is 64-bit (or 32-bit), PCI2 is OFF
3 1 Reserved 0 00 (default) Reserved
2 0
3 Core clock PLL[0:1] 0 00 2:1 01 5:2 (default)10 3:111 7:2
4 1
5 CCB clock PLL[0:3] 1 0000 16:10010 2:10011 3:10100 4:10101 5:10110 6:11000 8:1 1001 9:11010 10:1(default)1100 12:1Rest Reserved
6 0
7 1
8 0
4 1 Boot sequencer [0:1] 1 01 Standard I2C EEPROM10 Extended I2C EEPROM11 No EEPROM
2 1
3 CPU boot enable 1 Halt CPU until external host enable itAllow CPU to run immediately after reset
4 Processor identity — 0 MPC8541E1 MPC8555E
5 PCI host/agent 1 0 = Agent1 = Host (default)
6 Boot location 1 000 Boot from PCI bus #1001 Boot from DDR010 Boot from PCI bus #2101 Boot from local bus, 8-bit110 Boot from local bus, 16-bit111 Boot from local bus, 32-bit
7 1
8 0
Table 2-1. Default Status of Processor Board (CPU Card) Switches (continued)
SW Bit NameDefault (1 = ON)
Note
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Table 2-2. Default Status of Carrier Board Switches (Configuration 1)
SW Bit NameDefault(1 = ON)
Note
1 1 SYSCLK SEL 0 0 PCICLK used for SYSCLK1 LCLCLK used for SYSCLK
2 Synchronizer 1 1 Must be 1 at all times (PHY CLK/FPGA CLK)
3 Reserved 1 See Note 1
4 Local clock S(2:0) 0 01 Part of 33 MHz SYSCLK
5 1
6 1
7 Local clock R(4:3) 0 00 Part of 33 MHz SYSCLK
8 0
2 1 Boot select 0 00 Flash bank 1, bank 2 available 01 Flash bank 2, bank 1 available10 Promjet, bank 1 available11 Promjet, bank 2 available
2 0
3 NVRAM enable 1 0 NVRAM disable1 NVRAM available
4 Event select 1 0 UDE1 SRESET
5 Reserved 1 1 Reserved
6 Reserved 1 1 Reserved, see Note 2
7 User defined 0 00 User defined, software readable
8 0
3 1 Reserved 1 1 Reserved
2 DUART output select 1 0 DUART channel #2 to 2x5 (AT) headerDUART channel #1 to DB9 connector
1 DUART channel #2 to DB9 connectorDUART channel #1 to 2x5 (AT) header
3 ATM 2 enable 1 0 ATM2/155 enabled1 ATM2/155 disabled
4 ATM 1 width 1 0 ATM1/16-bit IO enabled1 ATM1/16-bit IO disabled
5 ADTech select 0 0 AdTech disabled1 AdTech enabled
6 FE select 0 0 FCC3->Cicada MII#4 enabled1 FCC3->Cicada MII#4 disabled
7 ATM2 select 1 0 FCC2->PMC 155M ATM enabled1 FCC2->PMC 155M ATM disabled
8 ATM1 select 1 0 FCC1->PMC 625M ATM enabled1 FCC1->PMC 625M ATM disabled
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b
4 1 Local clock R(2:1) 1 10 Part of 33 MHz SYSCLK
2 0
3 Local clock V(6:1) 0 001000 Part of 33 MHz SYSCLK
4 0
5 1
6 0
7 0
8 0
Notes:1. SW1(3) for Configuration 2 is PCI CLK SEL and must be set to 1.
2. SW2(6) for Configuration 2 is PCI Select PCI = 1 and PCIX = 0.
Table 2-3. Default Status of Arcadia Board Switches (Arcadia C3.n)
SW Bit NameDefault(1 = ON)
Note
1 1 TSI310: BAR_EN 0 0 BAR0 disabled1 BAR0 enabled
2 Secondary bus internal arbiter enable
TSI310: S_INT_ARB_EN
0 0 Use internal arbiter1 Use external arbiter
3 Physical width of the PCI-X deviceTSI310: 64_BIT_DEVICE
0 0 Bridge is a 64-bit bus1 Bridge is a 32-bit bus
4 Opaque region enable
TSI310: OPAQUE_EN
0 0 Opaque memory enable1 Opaque memory enable
5 Secondary PCI IDSEL remapTSI310: IDSEL_REROUTE_EN
0 0 IDSEL remap mask is 0000_00001 IDSEL remap mask is 22F2_0000
6 Secondary high-speed rate select
TSI310: S_SEL100
1 0 PCI-X highest speed is 133 MHz1 PCI-X highest speed is 100 MHz
7 Primary configuration busyTSI310: P_CFG_BUSY
0 0 Primary side responds to configuration cycles normally
1 Primary side configuration cycles are retried until bit 2 of the miscellaneous control registers is set to 0 by a secondary configuration cycle write
8 Primary driver mode controlTSI310: P_DRVR_MODE
0 0 Normal impedance1 Lower impedance for heavier loads
Table 2-2. Default Status of Carrier Board Switches (Configuration 1) (continued)
SW Bit NameDefault(1 = ON)
Note
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2 1 ARC0 0 0 SIOINT -> PCIB3_INT01 SIOINT -> PCIB3_INT1
2 ARC1 1 Reserved
3 ARC2 1 Reserved
4 1 G0 1 User defined
5 1 G1 1 User defined
6 2 LPCWP* 1 User defined
7 Reserved 1 N/A
8 Reserved 1 N/A
3 1 Isolate slow PCI bus segment
ISOLATE_3_4
0 0 PCIB3 connected to PCIB41 PCIB3 isolated from PCIB4
2 TSI310 PCI bridge enableBRIDGE_EN*
0 0 PCI bridge responds to config cycles1 PCI bridge ignores all config cycles
3 PCI A (fast) bus speed force
PCIA_FRC1
11 00 AUTO (33 MHz when M66_EN input is 0 or 66 MHz when M66_EN is a 1 (M66_EN pin is three-stated)
01 PCIA forced to 66 MHz PCI mode (M66_EN pin is three-stated)
10 PCIA forced to 33 MHz PCI mode (M66_EN pin is driven with logic 0)
11 PCIA forced to 33 MHz PCI mode (M66_EN pin is driven with logic 0)
4 PCI A (fast) bus speed force
PCIA_FRC0
5 RTK8139 Ethernet enableENET_DIS*
1 0 RealTek 8139 may be accessed1 RealTek 8139 cannot be accessed
6 PCI bus interrupt connectionPCI_INT_BRIDGE*
0 0 PCIA and PCIB interrupts are directly connected (wire-or’d)
1 PCIA and PCIB interrupts are isolated
7 3 PrPMC IDSEL enabledPRPMC_IDSELEN*
1 0 PrPMC can be target selected1 PrPMC cannot be target selected
8 4 MONARCH* 1 0 PrPMC is PCIB controller1 PrPMC is not PCIB controller
Notes:1. Software-defined switches.
2. Optional feature.
3. Some PCI devices do not allow their own IDSEL to be asserted when operating as the PCI host; if so, use this switch to disable IDSEL. Not applicable for PCI agents.
4. This switch configures the MPMC card into the system controller, a mode which is required for normal PCI use. Disabling is provided for testing purposes only.
Table 2-3. Default Status of Arcadia Board Switches (Arcadia C3.n) (continued)
SW Bit NameDefault(1 = ON)
Note
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Chapter 3 CDS Carrier ArchitectureThis chapter describes in detail the CDS carrier system. It describes the physical layout and assembly, as well as basic and detailed system architecture. This chapter elaborates on usage and testing/debugging procedures.
The CDS carrier is the backbone of the CDS system. It facilitates communication between the components as well as with outside parts through the PCI port.
3.1 OverviewThe following sections give the CDS board measurements and block diagram.
3.1.1 Board Measurements
For the CDS carrier, the mechanical dimensions are driven by the RapidIO Hardware Interoperability Platform standard. The placement of the RapidIO header (redefined for the CDS system as a flexible high-speed port), the additional power connectors, and the guide pins are detailed in this manual.
3.1.2 Block Diagrams
Figure 3-1 is a diagram of the CDS board for Configuration 1.
CDS Carrier Architecture
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Figure 3-1. Carrier Block Diagram (Configuration 1)
CPUDaughtercard
PCI-X+2.5 VPower
LocalClock
H/SClock
BU
F
Flash10/100#4
QuadPHY
IOCard
NVRAM
DEBUG
MUX uTCOM
OC3ATMPHY
OC12ATMPHY
AdTech
USB
GBit
RST
#3
GBit#1
GBit#2
UART
CDS Carrier Architecture
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Figure 3-2 is a diagram of the CDS system for Configuration 2.
Figure 3-2. Carrier Block Diagram (Configuration 2)
3.2 Carrier PinoutsFor a detailed pinout, including the numbering, refer to Appendix B.1, “Carrier/DaughterCard Connectors Pinout.”
3.3 System LogicThe CDS board contains an FPGA/CPLD called Cadmus which collects various logic and performs system control functions, including:
• System reset sequencer• System logic address map• PCI bus speed monitor• LED monitors• Peripheral bus development (chip select, address align)• System controls
CPUDaughtercard
PCI-X+2.5-VPower
LocalClock
H/SClock
FlashGBit#2
GBit#1
QuadPHY
NVRAM
DEBUG
MUX uTCOM
OC3ATMPHY
OC12ATMPHY
AdTech
BU
F
GBit#3
GBit#4
UART
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3.3.1 System Address Map
Table 3-1 describes the CDS memory map as implemented for U-Boot and Linux platform. Cadmus uses the local bus chip selects to implement the following two critical features:
• Boot flash redirection• Cadmus register intervention
Most chip-selects are passed through to the device as-is, with the exception of LCS3. This chip-select is used to implement the Cadmus register set and is shared with the external 4-KB NVRAM device.
Table 3-1. Memory Map
Chip Select
Description Base Address1
1 The CADMUS registers are connected to CS3 on the CDS. The new memory map places CADMUS at 0xF8000000.
Size
LCS0 Flash (boot bank) 0xFF80_0000 -----0xFFFF_FFFF 8M
LCS1 Flash (2nd bank) 0xFF00_0000 -----0xFF7F_FFFF 8M
LCS3 NVRAM/CADMUS1 0xF800_0000 ----- 0xF80F_FFFF 1M
LCS2 SDRAM2
2 Base Register 2 and Option Register 2 configure the SDRAM. The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xF0000000.
Note: These addresses are specific to the addresses specified by Linux, other OS/Boot code may/will use different base addresses.
Note: Addresses may vary widely by processor and bridge logic that is present on the CDC; refer to the specification for details.
0xF000_0000 ----- 0xF7FF_FFFF 128M
— PCI2 IO 0xE300_0000 ----- 0xE3FF_FFFF 16M
— PCI1 IO 0xE200_0000 ----- 0xE2FF_FFFF 16M
— CCSR 0xE000_0000 ----- 0xE00F_FFFF 1M
— PCI2 MEM 0xA000_0000 ----- 0xBFFF_FFFF 512M
— PCI1 MEM 0x8000_0000 ----- 0x9FFF_FFFF 512M
— DDR 0x0000_0000 ----- 0x7FFF_FFFF 2G
LCS4 Reserved
LCS5 UTCOM
LCS6 UTCOM
LCS7 Reserved
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3.3.2 System Logic Registers
The system logic contains several software-accessible registers which are accessed from the base address described in Section 3.3.1, “System Address Map.” Table 3-2 shows the address map of the Cadmus device.
3.3.2.1 Version Register (CM_VER)
The version register contains the board and CPLD revision information.
NOTEThe board revision applies only to the carrier, because different CPU daughtercards could be present. The I2C-based CDC ID EEPROM can be queried for further details.
Table 3-2. Cadmus Address Map
Base Address Offset
Register Access Reset
0x00 System version register (CM_VER) R 0x11
0x01 General control/status register (CM_CSR) R/W 0x00
0x02 Reset control register (CM_RST) R/W 0x00
0x03 Reserved — —
0x04 Reserved — —
0x05 LED data register (CM_LED) R/W 0x00
0x06 PCI control/status register (CM_PCI) R/W 0x00
0x07 DMA control register (CM_DMA) R/W 0x77
0x08-0xFF Reserved Reserved Undefined
0 1 2 3 4 5 6 7
R ID VER
W
Reset 0x10
Offset 0x00
Figure 3-3. Version Register (CM_VER)
Table 3-3. CM_VER Field Descriptions
Bits Name Description
0–3 ID Board identification
4–7 REV Revision number (starts with 0)
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3.3.2.2 General Control Register (CM_CSR)
The CM_CSR register contains various control and status fields, as described below.
3.3.2.3 Reset Control Register (CM_RST)
The reset control register contains enables and assertion bits for reset controls.
0 1 2 3 4 5 6 7
R USER -rsv- -rsv- EPHY(4:2) LED
W
Reset 0 0 0 0 0 0 0 0
Offset 0x01
Figure 3-4. Reset Control Register (CM_CSR)
Table 3-4. CM_CSR Field Descriptions
Bits Name Description
0–1 USER Reflects the settings of the USER switches on the carrier. Software may make use of these bits; CDS does not do anything with them.
2–3 Reserved
4–6 EPHY This field sets the most-significant 3 bits of the Ethernet PHY address (the least 2 bits are internally used to select 1 of 4 PHY devices).
7 LED If set, the internal LED buffers are driven by the contents of the CM_LEDCTL register; if clear (default), the contents are driven by various activities.
0 1 2 3 4 5 6 7
R XRSTEN PHYRST ATM1RST ATM2RST MEMRST UTRST -rsv- SRESET
W
Reset 0 0 0 0 0 0 0 0
Offset 0x02
Figure 3-5. Reset Control Register (CM_RST)
Table 3-5. CM_RST Field Descriptions
Bits Name Description
0 XRSTEN This bit, if set, allows the NVRAM watchdog timer to function as a general reset input.
1 PHYRST This bit allows software to issue a reset to the Ethernet PHY.
2 ATM1RST This bit allows software to issue a reset to the FCC1/ATM1 PHY.
3 ATM2RST This bit allows software to issue a reset to the FCC2/ATM2 PHY.
4 MEMRST This bit allows memory devices on the daughtercard to be reset (the carrier does not make use of it).
5 UTRST This bit allows the TCOM/ECOM boards (via the uTCOM adapter) to be individually reset.
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3.3.2.4 LED Data Register
The LED data register can be used to directly control the LED monitoring outputs, when CM_XCSR[LED] is set to one.
3.3.2.5 PCI Control/Status Register
The PCI control/status register monitors and controls the PCI environment.
6 HRESET This bit allows a device to assert HRESET to itself. As HRESET may be a level-sensitive signal (device-dependent), it is a self-resetting bit.
7 SRESET This bit allows a device to assert SRESET to itself. As SRESET may be a level-sensitive signal (device-dependent), it is a self-resetting bit.
0 1 2 3 4 5 6 7
R LED
W
Reset 0 0 0 0 0 0 0 0
Offset 0x05
Figure 3-6. Reset Control Register (CM_LED)
Table 3-6. CM_LED Field Descriptions
Bits Name Description
0–7 LED Corresponding values for CDC monitoring LEDs L0–L7. Setting a bit to one illuminates the LED.
0 1 2 3 4 5 6 7
R M66O PCIXCO M66S DUAL PSPEED PCIX PCIEN
W 0 0
Reset 0 0 0 0 0 0 0 0
Offset 0x06
Figure 3-7. PCI Control/Status Register (CM_PCI)
Table 3-5. CM_RST Field Descriptions (continued)
Bits Name Description
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3.3.2.6 DMA Control Register
The DMACTL register allows limited control and exercise of the DMA interface of various processors (where supported).
Table 3-7. CM_PCI Field Descriptions
Bits Name Description
0 M66O If set, the M66EN signal is forced low; otherwise, the M66EN pin is three-stated and the PCI bus speed is set by the daughtercard settings and/or the PCIXCAP/PCIXCO settings.Note: It is a violation of PCI protocol to change M66EN after PCIRST has been released; the effects of this bit are system-dependent.
1 PCIXCO If set, the PCIXCAP signal is forced low; otherwise, the PCIXCAP pin is three-stated and the PCI bus speed is set by the daughtercard settings and/or the M66EN/M66O settings.Note: It is a violation of PCI protocol to change PCIXCAP after PCIRST has been released; the effects of this bit are system-dependent.
2 M66S M66EN sense. If set to 1, PCI V2.3 mode or earlier is operating at 66 MHz; otherwise, 33 MHz is selected.
3 DUAL Daughtercard has selected dual PCI-mode (if any).
4–5 PSPEED PSPEED indicates the detected PCI speed, as follows:PCI:00 33 MHz01 66 MHz1X ReservedPCI-X:00 33 MHz01 66 MHz1X Reserved
6 PCIX If set, the PCI edge connector is connected to a PCI-X backplane; otherwise, conventional PCI is active.
7 PCIEN Reflects the status of the PCIEN switch. If 0, the PCI backplane is assumed active; otherwise, it may not be present.
0 1 2 3 4 5 6 7
R -rsv- DMARQ0 DMACK0 DMADN0 -rsv- DMARQ1 DMACK1 DMADN1
W
Reset 0 1 1 1 0 1 1 1
Offset 0x07
Figure 3-8. Reset Control Register (CM_DMA)
CDS Carrier Architecture
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3.4 CPM ConnectionsThe CDS carrier supports some peripherals for evaluating Ethernet and ATM interfaces for those processors which support CPM or CPM-compatible communications machines. If the CPUCard does not support this interface, the signals are simply ignored (that is, MPC8555E CDS daughterboard only supports FCC1 and FCC2; FCC3 is not supported on the MPC8555E device).
All other interfaces are evaluated and supported on external IO cards, such as the ECOM and TCOM. This allows evaluation of the SCC, multi-PHY, and other interfaces. To support this facility, selected signals are extracted from the CPM pins and either routed to the appropriate interface or to the uTCOM header. The overall logic is shown in Figure 3-9.
Figure 3-9. CE/CPM Architecture
The processor CE/CPM (if any) signals are largely routed directly to the uTCOM connector, with the exceptions noted in Table 3-9.
Table 3-8. CM_DMA Field Descriptions
Bits Name Description
15
DMARQ0DMARQ1
Sets the corresponding DMARQ line to the value written
26
DMACK0DMACK1
Reflects the status of the corresponding DMACK line
37
DMADN0DMADN1
Reflects the status of the corresponding DMADN line
FCC2
FCC1
FCC3
ATM622 Mbps
PHY
ATM155 Mbps
PHY
Enet10/100bT
PHY
uTCOM HeaderOthers
(Not Supported on MPC8555E/41E)
⊗
⊗
⊗
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The specific CPM/CE port bits that need to be switched for each mode are listed in Table 3-10 and Table 3-11.
Table 3-9. CDS CPM/CE Connection Options
CE/CPM Port
Definition SwitchSwitch = 0Definition
Switch = 1Definition
Notes
FCC1 OC12 SW3–8 622 Mbps ATM PHY uTCOM UTOPIA 8 onlyAdtech support
FCC2 OC3 SW3–7 155 Mbps ATM PHY uTCOM No UTOPIA connectionNo Adtech support
FCC3 10/100 SW3–6 FEthernet uTCOM FCC 3 not supported on MPC8555E/41E
Table 3-10. CPM Port Routing for FCC1 in ATM622/UTOPIA 8 Mode
ATM SignalGroup Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA(15:0) PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25
TXSOC PA29
TXENB PA31
TXPRTY PD16
TXADD(4:0) PD19 PD7 PC7 PC13 PC15
TXCLAV PA30
TXCLK PC20
RXDATA(15:0) PA17 PA16 PA15 PA14 PA13 PA12 PA11 PA10
RXSOC PA27
RXENB PA28
RXPRTY PD17
RXADD(4:0) PD18 PD29 PC6 PC12 PC14
RXCLAV PA26
RXCLK PC21
Table 3-11. CPM Port Routing for FCC2 in ATM155 Mode
ATM SignalGroup Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA(15:0) n/a PB22 PB23 PB24 PB25 PD31 PD22 PB26 PB27
TXSOC PB30
TXENB PD30
TXPRTY PC4
TXADD(4:0) PD7 PD19 PC9 PC11 PC17
TXCLAV PD25
TXCLK PC18
RXDATA(15:0) N/A PB21 PB20 PB19 PB18 PD21 PD20 PD15 PD14
RXSOC PB31
RXENB PD24
RXPRTY PC1
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Because not all of the CPM signals are optionally re-routed, some of the connections sent to the uTCOM header are from the switch device, and others are from the CPM port of the processor. This is summarized in Table 3-12.
RXADD(4:0) PD29 PD18 PC10 PC23 PC16
RXCLAV PB29
RXCLK PC19
Table 3-12. CPM/CE Switch Summary
Port Bits Type
PA 0-5 Switched
6-9 Pass-through
10-31 Switched
PB 4-6 Switched
7 Pass
8-27 SW
28 Pass-through
29-31 Switched
PC 0-1 Pass-through
2-21 Switched
22-31 Pass-through
PD 4 Pass-through
5-6 Switched
7 Pass-through
8-11 Switched
12-13 Pass-through
14-18 Switched
19 Pass-through
20 Switched
21 SW
22-28 Pass
29 Pass-through
30 Switched
31 Pass-through
Table 3-11. CPM Port Routing for FCC2 in ATM155 Mode (continued)
ATM SignalGroup Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDS Carrier Architecture
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3.5 ATM InterfacesThe CDS carrier card provides two dedicated ATM ports, one at 622 Mbps and the other at 155 Mbps. The general architecture is shown in Figure 3-10.
Figure 3-10. CDS ATM Architecture
Table 3-13 describes the details of the ATM interface.
3.6 Ethernet PortsIn Configuration 1, the CDS carrier card provides four 10/100 1GB-baseT Ethernet ports. Two are located on the basic carrier board and the other two on the IOCard expansion. The four ports are controlled by a Cicada CS8204 quad-PHY, which in turn receives data from three dedicated MII/GMII daughtercard connections.
In Configuration 2, all four Ethernet ports on the carrier card are supported by a Marvell 88E1145. MII/GMII on Ethernet ports #1 and #2. RGMII on Ethernet ports #3 and #4, 10/100 or 1G rates.
Table 3-13. ATM Port Overview
Feature ATM1 ATM2
CE/CPM connection FCC1 FCC2
UTOPIA interface 16 8
Adtech support? Yes No
PHY PMC-Sierra PM5357 PMC-Sierra PM5384
Optical transceiver Agilent HFBR-5208M Agilent HFBR-5805
From
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FCC2
FCC1PM5357
622 MbpsHFBR-58208M
PM5384155 Mbps
HFBR-5805
AdT
ech
CDS Carrier Architecture
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NOTEIn Configuration 1, TBI, RTBI, RMII, and RGMII interface modes are not supported.
In Configuration 1, Ethernet port #4 on the I/O card is not functional.
In Configuration 2, RGMII is supported only on Ethernet ports #3 and #4.
The fourth port is optionally extracted from the FCC3 pins on port B pins of the CPM engine as detailed in Section 3.4, “CPM Connections.” In addition to the special pins, the fourth port is only connected as a 10/100baseT port.
The PHY addresses are numbered 0–3, corresponding with the 4 internal PHY devices. The MSB bits (3 of them) of the address can be changed by writing to the CM register, however the lower 2 bits are always mapped internally by the CIS8204 as shown in Table 3-14. The Ethernet PHY addresses are fixed in Configuration 2.
These connections and the interface logic are shown in Figure 3-11 for Configuration 1 and Figure 3-12 for Configuration 2.
Table 3-14. PHY Address Options (Configuration 1)
CM_CSR EPHY[4:2] CIS8204 Port PHY Address
000 (Default) 0 0x00
1 0x01
2 0x02
3 0x03
001 0 0x04
1 0x05
2 0x06
3 0x07
... ... ...
111 0 0x1C
1 0x1D
2 0x1E
3 0x1F
CDS Carrier Architecture
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Figure 3-11. CDS Ethernet Architecture (Configuration 1)
Figure 3-12. CDS Ethernet Architecture (Configuration 2)
125 MHz
RJ45 +MAG
RJ45 +MAG
RJ45 +MAG
RJ45 +MAG
IOCardCADMUS
EPHY_ADR[4:2]
⊗
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10/100
MI
TSEC2
TSEC1
CIS8204
PHY
0
1
2
3
Port
125 MHz
RJ45 +MAG
RJ45 +MAG
RJ45 +MAG
RJ45 +MAG⊗
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RGMII 10/100
MI
GMII TSEC2
GMI/RGMII
RGMII
TSEC1
Marvell88E1145
0
1
2
3
Port
CDS Carrier Architecture
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Table 3-15 summarizes the connections to the TSEC interface and associated PHY.
Each TSEC has LEDs to monitor activity in the RJ45 connector.
3.7 Local BusThe CDS carrier card provides a local bus, which supports commonly required memory and other devices. It does so at a significantly slower speed than the CPU daughtercard, and only expects that the daughtercard present a consistent address interface at a high bus load. The local bus includes:
• Two separate, bootable banks of Flash memory— AMD Am29LV641DH-120 (or faster)— 64 Mb each— 8- or 16-bit access sizes supported
• One bank of RTC/NVRAM— Maxim DS1553WP, 8KB with battery backup
• Three Mictor headers for local bus debug• uTCOM interface port• ATM PHY registers
Table 3-15. CDS TSEC Interface Summary
TSEC SignalTSEC Signal Type
TSECx Bus Connect
DescriptionCS8204 PHY or
Marvell 88E1145
Notes
TSECx_TXD[7:0] O 7–0 Transmit data inputs TXD[7:0] 3
TSECx_TX_EN O 8 Transmit enable input TX_EN
TSECx_TX_ER O 9 Transmit error input TX_ER
TSECx_TX_CLK I 10 N/A N/A 1
TSECx_GTX_CLK O 11 Transmit clock output GTX_CLK
TSECx_CRS I 12 Carrier sense CRS
TSECx_COL I 13 Collision detect COL
TSECx_RXD[7:0] I 21–14 Receiver data output RXD[7:0]
TSECx_RX_DV I 22 Receiver data valid output RX_DV
TSECx_RX_ER I 23 Receiver error output RX_ER
TSECx_RX_CLK I 24 Receiver clock output RX_CK
MDC O Management data clock MDC
MDIO I/O Management data I/O MDIO
GTX_CLK125 I Reference 125 MHz clock N/A 2
Notes:1. TX_CLK is not used in GMII mode, only MII.
2. Reference clock is derived from the global 125-MHz reference clock.
CDS Carrier Architecture
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The bus is treated as a general-purpose interface and leaves decisions such as chip select to the daughtercard. The connections and accompanying interface logic is shown in Figure 3-13.
Figure 3-13. CDS Local Bus Architecture
Table 3-16 lists the pins of the daughtercard connector.Table 3-16. CDS Carrier Local Bus Signals
Signal Group Signal Name Signal Count Notes
Address LB_A(0:31) 32 LB_A0 is MSB
Data LB_D(0:31) 32 LB_D0 is MSB
Data parity LB_DP(0:3) 4 LB_DP(0) pairs with LB_D(0:7), etc.
Output enable LB_OE 1
Write strobes LB_WE(0:3) 4
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CS[0:7]
ADDRCADMUS
Flash #1
Flash #2
PromJet
NVRAM
Logic An.
PHYs
DATA
CLA
OTHER
uTCOM
CDS Carrier Architecture
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3.7.1 NCDS Local Bus Signals
The CDS local bus generates several signals in the pins of Table 3-16. Table 3-17 describes these signals.
Chip selects LB_CS0 8 Connects to Flash device #1 (carrier card)
LB_CS1 Connects to Flash device #2 (carrier card)
LB_CS2 Connects to SRAM/SDRAM port (CPU card)
LB_CS3 Connects to RTC/NVRAM
LB_CS4 Connects to uTCOM port
LB_CS5 Reserved
LB_CS6 Reserved
LB_CS7 Reserved
Address latch LALE 4 For systems with multiple LALE signals implemented only LALE is guaranteed; LALE(1:n) are for reference purposes only.
Control LBCTL 1
Misc LGP(0:5) 6
Clock LB_CLK 1 Signals such as LB_CLK(1:2) are optional
Device size LBSZ(0:1) 2 Local bus device width control:00 = 8-bit01 = 16-bit10 = 32-bit11 = Reserved
Subtotal 95
Spares 5
Total 100
Note: The signal names do not necessarily map directly to the equivalent signal names on the daughtercard.
Table 3-17. CDS Cxx Local Bus Signals
Signal Name Description Notes
CLA(23:0) CDS local address CLA(23) is MSB
LB_RD Local bus read/output enable
LB_WR Local bus write
FLASH0_CS Flash bank 0 chip select Default boot device
FLASH1_CS Flash bank 1 chip select Alternate boot
PJET_CS PromJet chip select External boot select
NVRAM_CS NVRAM/RTC chip select
Table 3-16. CDS Carrier Local Bus Signals (continued)
Signal Group Signal Name Signal Count Notes
CDS Carrier Architecture
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Table 3-18 is an example of how the local bus address (LB_A(0:31)) is converted into the size-aligned address suitable for the local bus.
3.8 ClockThe CDS carrier board contains four independent clock domains:
SYSCLK –for CPU and/or alternate PCI clockPCICLK –for primary PCI bus125-MHz reference –for PHY reference clocksTimebase/performance monitor clock –miscellaneous
Note that the daughtercard may elect to generate or derive any other subsidiary clocks for its own purpose.
The SYSCLK signal is generally the primary clock source for the Freescale PowerPC processor and is typically related to the PCICLK of the carrier board by some configurable ratio.
In a HIP environment, the PCICLK source from the PCI edge connector may be 0 MHz (that is, PCI disabled), 33, or 66 MHz.
The 125-MHz PHY reference clock (fixed frequency), the 16-MHz timebase reference (fixed frequency), and the external high-speed reference clock are independent.
ATM1_CS ATM PHY #1 chip select ATM622 Mbps device
ATM2_CS ATM PHY #2 chip select ATM155 Mbps device
ATM1X_CS AdTech PHY chip select AdTech external chip select
Table 3-18. CLA Mapping
LBSZ(0:1) Setting CLS Generation
00 (8-bit) CLA(23) = LB_A(8)CLA(22) = LB_A(9)...CLA(01) = LB_A(30)CLA(00) = LB_A(31)
01 (16-bit) CLA(23) = LB_A(7)CLA(22) = LB_A(8)...CLA(01) = LB_A(29)CLA(00) = LB_A(30)
10 (32-bit) CLA(23) = LB_A(6)CLA(22) = LB_A(7)...CLA(01) = LB_A(28)CLA(00) = LB_A(29)
11 Reserved
Table 3-17. CDS Cxx Local Bus Signals (continued)
Signal Name Description Notes
CDS Carrier Architecture
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The CDS carrier clock resources are summarized in Table 3-19.
The overall clock architecture is shown in Figure 3-14.
Figure 3-14. CDS Clock Architecture
The clock logic is straightforward. The primary SYSCLK is taken from the local clock (ICS I CPICLK signal, depending on whether the PCI bus is active. The local clock is sent to the CDC (regardless of the PCI clock) to support asynchronous PCI/processor operations.
The 125-MHz clocks are used to drive the PHYs.
3.9 PCI-XThe CDS card provides a standard PCI edge connector for use in PCI or PCI-X motherboards. As a HIP-compatible card, CDS must operate without the presence of the PCI bus. Therefore, while signals such as PCIRST and PCICLK may be used, the carrier must contain additional circuitry to allow it to operate without the presence of the bus signals
Table 3-19. CDS Clock Requirements Summary
Clock Signal Frequency Range Voltage Level Require Notes
PCICLK 33/66 MHz 3.3V LVTTL PCI interface of daughtercard
SYSCLK 10–200 MHz 3.3V LVTTL
PHYCLK 125 MHz 3.3V LVTTL QuadPHY on CDS main board
RTC_CLK 16 MHz 3.3V LVTTL Timing base for the performance monitor
CDC
125 MHzOSC
PCICLK
PCICLK
ICS
525-
02
16 MHzOSC
GTX_CLK
RTC_CLK
I2C/Switch
PCISLOT
SYSCLK
LocalBus
LBCLK
MUX
CDS Carrier Architecture
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NOTEIt is not possible to disable the PCI bus when an active PCI bus is present on the motherboard; that is, there is no isolation circuitry between the processor PCI interface and the PCI edge connector, so when CDS is plugged into a PCI slot, it must be configured to be PCI enabled.
The general PCI architecture is shown for Rev. 1.1 CDC in Figure 3-15.
Figure 3-15. CDS PCI Architecture
The connections for the PCI bus are summarized in Table 3-20. Except as noted, connections are point to point from the card edge connector to the daughtercard connector.
3.9.1 PCI Arbitration
PCI cards cannot provide system-side bus arbitration and HIP cards do not even require the bus to be present. Due to this, CDS does not provide any sort of PCI arbitration controls, even if the processor or daughtercard could handle it. Regardless of the ability to supply arbitration, the CPU or the bridge on the
Table 3-20. CDS PCI Properties
Edge Connection Destination Notes
PCICLK To local clock/PCI clock switch 1
PCIRST CM FPGA for local/debug reset merging, then to daughtercard (as HRESET)
C/BE[7:0]FRAME STOP PERR SERR IDSEL PAR
PAR64 REQ64 ACK64 REQ GNT
To daughtercard
DEVSEL IRDY TRDY M66EN PCIXCAP
To daughtercard and CM (through passive probes)
Note:
1. Per the PCI specifications, the effective clock trace length from the edge connector to the MPC85X0 (including intervening connection control logic) must be 5 cm (2.5”).
LocalClock
PCI Edge Connector
LocalReset
SYSCLK
PCIRST
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PCIother
PCICLK
CDS Carrier Architecture
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daughtercard can be configured to act as a system host: accepting inbound PCI traffic and performing system enumerations.
This does not mean that the CDS cannot function as the PCI host, in fact in most shipped system, the CDS will be the PCI host. Arbitration and host/agent functions are associated, but entirely separable.
3.9.2 PCI-X System Control
PCIXCAP settings are determined by the daughtercard. The CM FPGA has the capability to overdrive the PCIXCAP and M66EN signals (to force them low). See the system logic registers for further details.
This is only useful if the card will be asserting system reset for other devices, and making changes is only useful before a reset.
3.10 ExceptionsCDS collects several exception (interrupts and signals) from various resources and presents them to the daughtercard for handling. Monitored interrupt sources include:
• PCI interrupts INT(A:D)• Ethernet Quad-PHY• ATM PHYs• Periodic timer interrupt• Debug events
Figure 3-16 shows the overall interrupt architecture.
Figure 3-16. CDS Exception Architecture
PCIX EDGE
INTA
INT
B
INT
D
PC
I_V
IO
INT
C
Quad
2CPUCard
IRQ
0:11
UDE
IOCard
SRESET
ATM PHYS ENet PHY
RTC/RAM
PBSW
RMT
CDS Carrier Architecture
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The resulting connections and notes are listed in Table 3-21.Table 3-21. CDS Exception Properties
CDC Signal Connection Routing Notes
IRQ0 INTA PCI edge connector INTA 1, 2
IRQ1 INTB PCI edge connector INTBPCI2 slot connector INTB
1, 2, 7
IRQ2 INTC PCI edge connector INTCPCI2 slot connector INTC
1, 2, 7
IRQ3 INTD PCI edge connector INTDPCI2 slot connector INTD
1, 2, 7
IRQ4 Reserved Reserved 3
IRQ5 MDINT On-board QuadPHY 3
IRQ6 ATMINT ATM PHY interrupt 3
IRQ7 CMINT CPLD interrupt (typically DMA) 3
IRQ8 Reserved Reserved 3
IRQ9 NVINT NVRAM/RTC periodic interval timer 3
IRQ10 DEBUG Debug event switch (s/w managed) 5
IRQ11 PCI2_INTA Second PCI bus slot interrupts 3, 4
UDE UDE Open-drain drive from remote header
SRESET EVE1 Debounced push button switch 6
Notes:
1. PCI interrupts INTA–INTD are very weakly pulled-up with a 100-KΩ resistor so that the signals do not float low. This is in technically a violation of the PCI specification for plug-in cards, but is required for PCI-based HIP cards. The maximum of 4 slots produces a maximum effective pullup of 50 KΩ in addition to the HIP motherboard pullup, if any. The overall effect is deemed negligible. INTA–INTD must be driven, if at all, on the daughtercard with an open-drain driver in order to assert interrupts to remote hosts. The carrier does not enforce how this is implemented.
2. These interrupts should be programmed to active-low, level-sensitive modes for PCI compatibility.
3. Unused interrupts are pulled high; the carrier need not add pullups to unused resources.
4. PCI2 interrupts are optional sources, from daughtercards with secondary PCI slot capability.
5. The software debug event is strictly a debounced switch from the viewpoint of the board and the processor; software must handle the ‘debug’ aspects. Or, just ignore it.
6. The event switch is assignable to IRQ10 or SRESET.
7. For the second PCI/PCI2 slot, if any.
CDS Carrier Architecture
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3.10.1 Software Triggered Exceptions
Software can trigger an IRQ9 event by writing to appropriate registers in the Dallas DS1553WP non-volatile SRAM/RTC. The following sequence is recommended:
Set the WatchDog Register (offset 0x1FF7 from the LCS2* base (typically 0xFD00_0000)) toRB(1:0) = %00 (1/16 second resolution)BMB(4:0) = %00001 (minimum delay)WDS = %0 (assert IRQ9)
After 1/16 of a second, the IRQ9 interrupt will be asserted. The IRQ9 handler must clear the interrupt by disabling the WatchDog timer, by writing a zero to the WatchDog Register.
3.11 ResetThe reset architecture of CDS is shown in Figure 3-17.
Figure 3-17. CDS Carrier Reset Architecture
The CDS has two separate resets, POR_RST and SYS_RST. The only difference between the two is that POR_RST resets the I2C configuration-override logic. This allows software to configure the board and still assert reset to begin repeatable tests. Asserting POR_RST removes software overrides and then equivalently resets the target.
In addition, the system logic contains software-programmable registers which allow individual reset outputs to be asserted.
Reset sources are listed in Table 3-22, while reset outputs are listed in Table 3-23.
ResetCTL Logic
Config
Various
PowerOn
ResetCTL
ResetSequencer
DebugPort
IOCard
ResetForce
Resets
POR_RST
CDS Carrier Architecture
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3.11.1 Software Triggered Resets
Software can trigger most reset events by writing to a register in the system logic. A self-reset can be achieved in the following ways:
• Assert the HRESET_REQ signal (processor-dependent)• Assert the CM_RST[SYS_RST] bit (motherboard-dependent)• Use the NVRAM watchdog timer
The first option is processor-specific, consult the processor’s reference manual for details. The second option is detailed in the system logic section (refer to Section 3.3, “System Logic”). For a detailed pinout, including the numbering, refer to Appendix B.1, “Carrier/DaughterCard Connectors Pinout.”
The third option, using the NVRAM watchdog timer, can be triggered by writing to appropriate registers in the Dallas DS1553WP non-volatile SRAM/RTC. The following sequence is recommended:
1. Enable the WatchDog reset in the System Control register CM_RST (see Section 3.3.2, “System Logic Registers”).
Table 3-22. CDS Reset Sources
Source How Asserted Type
Carrier Power cycle POR_RST
Remote control port High-to-low transition of RMT_POR POR_RST
Remote control port High-to-low transition of RMT_RST SYS_RST
Processor High-to-low transition of HRESET_REQ SYS_RST
NVRAM watchdog High-to-low transition of NVRST (maskable) SYS_RST
Table 3-23. CDS Reset Outputs
Signal Description How Asserted Notes
CFGRST Configuration logic reset Power cycle or RMT_POR assertion
HRESET Processor hard reset Power cycle, HRESET_REQ, RMT_POR or RMT_RST
CFGDRV Configuration logic HRESET (asserted for one extra cycle)
ATM1_RST Reset ATM1 PHY device HRESET or CM_RST[ATM1_RST] asserted
ATM2_RST Reset ATM2 PHY device HRESET or CM_RST[ATM2_RST] asserted
ENET_RST Reset quad Ethernet PHY HRESET or CM_RST[ENET_RST] asserted 1
SYSRST Motherboard reset HRESET or CM_RST[SYS_RST] asserted 2
MEM_RST Memory device reset HRESET or CM_RST[MEM_RST] asserted 3
UTCOM_RST UTCOM_RST HRESET or CM_RST[UTC_RST] asserted
Notes:1. Reset will affect all (up to four) Ethernet devices using the four-port PHY.
2. Non-standard on true HIP motherboard, but implemented on Arcadia-class motherboard.3, If any; mostly only registered DIMMs will implement the reset input.
CDS Carrier Architecture
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2. Set the WatchDog Register (offset 0x1FF7 from the LCS2* base (typically 0xFD00_0000)) to:RB(1:0) = %00 (1/16 second resolution)BMB(4:0) = %00001 (minimum delay)WDS = %1 (assert NVRST (which will assert HRESET to the processor and other devices)).
NOTEThe system startup code must initialize the WatchDog timer by writing a zero to the WatchDog register. Otherwise, the system will continually reset until power is cycled (because this is, as you might have guessed, a watchdog timer).
3.12 I2CCDS makes extensive use of the I2C bus for a variety of purposes, including:
• System configuration• Non-PCI (local) clock speed selection• Remote control bus• Module and system identification
Many of these functions are also available on the daughtercard, so familiarity with the CDC card in use is assumed. All current carrier cards implement the architecture of the I2C bus as shown in Figure 3-18.
Figure 3-18. CDS Carrier I2C Architecture
Table 3-24 contains a summary of the various features of the I2C devices. Refer to the programming manual for detailed programming information, and refer to other sections of this manual for details on how the I2C-control features are implemented (specifically, Section 3.13, “Configuration”).
DebugControlConn.
RemoteControlDrive
CADMUS
Configs
IDEEPROM Buffer
I2CToDaughtercard
Offboard
CDS Carrier Architecture
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3.13 ConfigurationThe CDS contains many configuration options to allow it to adapt to the user's application. Many of these options are static: set at startup and remain unchanged. Others are asserted during the reset sequence (generally, this occurs on the processor/system bridge, that is, on the CDC) and after reset is concluded, revert to some other function.
Table 3-24. CDS I2C Bus Properties
I2C Device I2C Device I2C Address Data Size Notes
CDC system ID EEPROM AT24C64A 0x56 (1010_110x) 8192
Remote control/configuration port PCA9557 0x1C (0011_100x)0x1D (0011_101x)0x1E (0011_110x)0x1F (0011_111x)
8 1, 2
Notes:
1. CDC daughtercards may also have configuration switches, at addresses 0x18.01B.2. These devices are at different addresses and have different programming sequences as compared to
the Elysium use of dual PCF9555s.
Table 3-25. CDS Configuration Parameters
Configuration Option Config. SignalControl Method
I2C Config PortSwitch Default
Dev Bits
ATM1 mux disable ATM1_SEL Switch or I2C 0x24 0 SW3(8) 1 = CPM->ATM1
ATM2 mux disable ATM2_SEL Switch or I2C 1 SW3(7) 1 = CPM->ATM2
FE mux disable FE_SEL Switch or I2C 2 SW3(6) 1 = CPM->FE
ADTech select ADT_SEL Switch or I2C 3 SW3(5) 0 = AdTech NOT active
ATM1 width ATM1_16BIT Switch or I2C 4 SW3(4) 1 = ATM1 16-bit IO
ATM2 enable ATM2_EN Switch or I2C 5 SW3(3) 1 = ATM2 enabled
Uart_Sel Switch or I2C 6 SW3(2) 1 = Uart_Sel
Reserved Switch or I2C 7 SW3(1) 1 = Reserved
User-defined USERMODE(0:1) Switch or I2C 0x25 1–0 SW2(8:7) 00 = User defined
Reserved Switch or I2C 2 SW2(6) 1 = Reserved 1
Reserved Switch or I2C 3 SW2(5) 1 = Reserved
Event select EVE_SEL Switch or I2C 4 SW2(4) 1 = EVE = SRESET
NVRAM disable NVRAM_DIS Switch or I2C 5 SW2(3) 1 = NVRAM available
Flash boot select ROMMODE(0:1) Switch or I2C 7–6 SW2(2:1) 00 = Standard Flash
Local clock V(6:1) select LCLK_V(6:1) Switch or I2C 0x26 5–0 SW4(3:8) 001000 = Part of 33MHz SYSCLK
Local clock R(2:1) select LCLK_R(2:1) Switch or I2C 7–6 SW4(1:2) 10 = Part of 33MHz SYSCLK
CDS Carrier Architecture
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CDS uses part of the reset sequence to support the options in the table above, as well as to allow hardware/software to easily change the configuration. The reset logic is executed by three-state transceivers receiving signals from the MPC85xx. The transceivers are, in turn, controlled by the CFGDRV signal, as in Table 3-25. The reset values which are configured using I2C switches, are shown in Figure 3-19.
Figure 3-19. CDS Configuration Logic
The output buffer depends on the inputs, whether multipurpose or dedicated. The buffer is driven only during CFGDRV for multi-purpose inputs, but always driven for dedicated inputs.
The I2C control device powers up as an input, preventing it from interfering with either the weak external pulldown or the switch-selected, normal-strength pullup resistors. The exception is when the active drive is enabled. With the I2C three-stated, the buffer converts a resistive high or low into a clean LVTTL configuration level.
Local clock R(4:3) select LCLK_R(4:3) Switch or I2C 0x27 1–0 SW1(7:8) 00
Local clock S(2:0) select LCLK_S(2:0) Switch or I2C 4–2 SW1(4:6) 011
Reserved Switch or I2C 5 SW1(3) 1 = Reserved 2
Synchronizer SYNCHRO Switch or I2C 6 SW1(2) 1 = Non-synchronized
PCI enable PCIEN Switch 7 SW1(1) 0 = PCI environment
Ext ref clock enable MCLK_DIS Install R168 0 Ω
Notes:1. SW1(3) for Configuration 2 is PCI CLK SEL and must be set to 1.2. SW2(6) for Configuration 2 is PCI Select PCI = 1 and PCIX = 0.
Table 3-25. CDS Configuration Parameters
Configuration Option Config. SignalControl Method
I2C Config PortSwitch Default
Dev Bits
Processor
CTL
cfg_pin
OVDD
CFG_DRV
I2CI2C
Groundor or
Device
CFGRST
CDS Carrier Architecture
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Once a particular I2C control output has been programmed, the rail-to-rail output FETs in the PCA9557 will overdrive the weaker pullup/pulldowns, granting the I2C output register direct control over the configuration logic.
Note that the I2C I/O controller outputs remain constant even when HRESET is asserted. Only a power-up reset, or the special POR_RST signal (effectively CFGRST) can reset the I2C I/O device to three-state, allowing the user-specified switch settings to take effect.
This allows the remote control system to configure the board but not have to monitor reset events (via COP or switch) and be required to intervene and reconfigure the board. This allows for the remote control system to configure the board, while removing the need for a reset monitor or reconfiguration.
3.14 PowerThe power provided to the CDS system is standard, 5 and 3.3 V. It is delivered through the HIP power connectors, though additional power (if necessary) must be obtained from the PCI/PCI-X connector which can provide 5, 3.3, and 12 V as required. Table 3-20 shows the power architecture.
Figure 3-20. CDS Power Architecture
Table 3-26 summarizes the power available to CDS cards.Table 3-26. CDS Available Power
Power Source Current Power
5 V HIP 2 x 7.8 A 78 W
PCI 5 A 25 W
Total 20.6 A 103 W
3.3 V HIP 2 x 7.8 A 52 W
PCI 7.6 A 25 W
Total 23.2 A 77 W
PCI HIP
+3.3 V
+5 V
CDC
CDS
CPU
OVDD
Switcher(+2.5 V)
VCoreSwitcher
CDS Carrier Architecture
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The power budget must be compared to the two separate 5-/3.3-V rating limits (78 W + 52 W and 103 W + 77 W, respectively) to determine if the board can be operated in a non-PCI-based environment.
3.14.1 +2.5-V Power
The +2.5-V power source is supplied by a switching power supply module. It supplies +2.5-V power to components on the carrier as well as the daughtercard, generally for I/O power or miscellaneous discrete logic. The output voltage is not digitally adjustable, though resistor options are provided for minor tweaking/experimentation. The current is measured in the same way as the processor core power.
3.14.2 Power Management
There are no power management facilities on CDS.
3.15 Diagnostic FeaturesCDS contains as many debug/analysis support features as may be reasonably accommodated in the compact size allocated to it. The following features are supported:
• Local bus analyzer header• Remote control port• LEDs
Note that features such as DDR memory bus and COP/JTAG ports are handled on the daughtercard; see the respective section/reference manual for details.
3.15.1 Analyzer Headers
The local bus may be debugged using three Mictor headers, compatible with Tektronix and Agilent logic analyzers. No shrouds are provided, but a dual footprint is provided to support installation of either the small Tektronix or the larger Agilent shrouds. Table 3-27, Table 3-28, and Table 3-29 show the pinouts for the local-bus debug headers.
+12 V HIP — —
PCI 1 A 12 W
Total 1 A 12 W
–12 V HIP — —
PCI 1A 12 W
Total 1A 12 W
Table 3-26. CDS Available Power (continued)
Power Source Current Power
CDS Carrier Architecture
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Table 3-27. CDS Local Bus ‘STAT’ Header Definition
Pin Signal Mictor Definition
3 LBCLK2 Even clock
4 LBCTL Even D15 (MSB)
5 WE3/BS3 Even D14
6 WE2/BS2 Even D13
7 WE1/BS1 Even D12
8 WE0/BS0 Even D11
9 CDC_SPR1 Even D10
10 CDC_SPR2 Even D9
11 Even D8
12 Even D7
13 Even D6
14 GPL5 Even D5
15 GPL4 Even D4
16 GPL3 Even D3
17 GPL2 Even D2
18 GPL1 Even D1
19 GPL0 Even D0 (LSB)
36 LALE Odd clock
35 Odd D15 (MSB)
34 RD Odd D14
33 WR Odd D13
32 DP3 Odd D12
31 DP2 Odd D11
30 DP1 Odd D10
29 DP0 Odd D9
28 Odd D8
27 CS7 Odd D7
26 CS6 Odd D6
25 CS5 Odd D5
24 CS4 Odd D4
23 CS3 Odd D3
22 CS2 Odd D2
21 CS1 Odd D1
20 CS0 Odd D0 (LSB)
CDS Carrier Architecture
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Freescale Semiconductor 3-31
Table 3-28. CDS Local Bus ‘ADDR’ Header Definition
Pin Signal Mictor Definition
3 LACLK Even clock
4 LCL_RST Even D15 (MSB)
5 IRQ0 Even D14
6 TP28 Even D13
7 Even D12
8 Even D11
9 Even D10
10 Even D9
11 Even D8
12 CLA23 (MSB) Even D7
13 CLA22 Even D6
14 CLA21 Even D5
15 CLA20 Even D4
16 CLA19 Even D3
17 CLA18 Even D2
18 CLA17 Even D1
19 CLA16 Even D0 (LSB)
36 PCICLK Odd clock
35 CLA15 Odd D15 (MSB)
34 CLA14 Odd D14
33 CLA13 Odd D13
32 CLA12 Odd D12
31 CLA11 Odd D11
30 CLA10 Odd D10
29 CLA9 Odd D9
28 CLA8 Odd D8
27 CLA7 Odd D7
26 CLA6 Odd D6
25 CLA5 Odd D5
24 CLA4 Odd D4
23 CLA3 Odd D3
22 CLA2 Odd D2
21 CLA1 Odd D1
20 CLA0 (LSB) Odd D0 (LSB)
CDS Carrier Architecture
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Table 3-29. CDS Local Bus ‘DATA’ Header Definition
Pin Signal Mictor Definition
3 Even clock
4 LB_D0 (MSB) Even D15 (MSB)
5 LB_D1 Even D14
6 LB_D2 Even D13
7 LB_D3 Even D12
8 LB_D4 Even D11
9 LB_D5 Even D10
10 LB_D6 Even D9
11 LB_D7 Even D8
12 LB_D8 Even D7
13 LB_D9 Even D6
14 LB_D10 Even D5
15 LB_D11 Even D4
16 LB_D12 Even D3
17 LB_D13 Even D2
18 LB_D14 Even D1
19 LB_D15 Even D0 (LSB)
36 Odd clock
35 LB_D16 Odd D15 (MSB)
34 LB_D17 Odd D14
33 LB_D18 Odd D13
32 LB_D19 Odd D12
31 LB_D20 Odd D11
30 LB_D21 Odd D10
29 LB_D22 Odd D9
28 LB_D23 Odd D8
27 LB_D24 Odd D7
26 LB_D25 Odd D6
25 LB_D26 Odd D5
24 LB_D27 Odd D4
23 LB_D28 Odd D3
22 LB_D29 Odd D2
21 LB_D30 Odd D1
20 LB_D31 Odd D0 (LSB)
CDS Carrier Architecture
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Freescale Semiconductor 3-33
3.15.2 Remote Debug Header
This 2x5-pin right-angle Berg header is used for special test environments. Table 3-30 shows the pin definitions.
The connectors are physically arranged as shown in Table 3-31.
3.15.3 Monitoring LEDs
CDS has numerous LEDs dedicated to monitoring system status, as described in Table 3-32.
Table 3-30. CDS Remote Header
Pin Signal Definition
1 SCL I2C serial clock
2 SDA I2C serial data
3 GND System ground
4 GND System ground
5 N/C
6 N/C
7 RMT_UDE UDE drive (open-drain). Pulled up to 3.3 V.
8 N/C
9 RMT_RST Open-collector active-low reset input. Pulled up to ~3 V.
10 RMT_POR Open-collector active-low power-on reset input. Pulled up to ~3 V.
Table 3-31. CDS Debug Header Definition
1 2
3 4
5 6
7 8
9 10
Table 3-32. CDS LEDs
LED Label LED No. Definition
OVDD N/A OVDD (+2.5-V power) operational
VDD3 N/A VDD3 (+3.3-V power) operational
L0_VDD 0 VDD (processor core) power operational
L1_PCIEN 1 PCI bus enabled
L2_PCI 2 PCI bus activity detected
L3_SLEEP 3 Processor halted/idle
L4_RESET 4 Reset asserted
CDS Carrier Architecture
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Note that software can override the functions of LEDs 0–7 and replace them with user-defined activity.
L5_CLK 5 Clock active
L6_MEM 6 Flash/local-bus memory active
L7_MISC 7 Miscellaneous reporting
Table 3-32. CDS LEDs (continued)
LED Label LED No. Definition
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Freescale Semiconductor 4-1
Chapter 4 CDS Daughtercard ArchitectureThe following sections will cover the CDS daughtercard (CDC) design in more detail. Note that, because the daughtercard is the most interchangeable part of the CDS system, this section will be more general. Refer to the data sheets for more detail on a particular daughtercard.
The CDS system supports a variety of processors, both individual and integrated devices. Since there is one unique daughtercard for each unique processor footprint, each card will be slightly different.
This chapter provides details on what is supported on specific cards for the processor-specific daughtercard hardware.
4.1 Mechanical ArchitectureThe CPU daughtercard is sized and placed as shown in Figure 4-1.
CDS Daughtercard Architecture
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4-2 Freescale Semiconductor
Figure 4-1. Daughtercard Placement
335
[13.
25]
RJ4
5
RJ4
5Q
PH
Y
HIP
HIP
Mic
tor
Mic
tor
130
[5.2
]
Fla
sh
IO M
odul
e
UA
RT
P68
80
FC
I uT
CO
M (
Rea
r)
FCI Right
Samtec
Qui
ck
FCI Left
Sw
itch
HF
BR
HF
BR
Pro
mJE
T
Fla
sh
NV
RA
M
Dau
ghte
rcar
d
P68
80
Pow
er
ATM
PH
YAT
MP
HY
AdT
ech
FP
GA
Samtec Diff
CDS Daughtercard Architecture
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Freescale Semiconductor 4-3
The daughtercard’s large dimension allows multiple cards to be inserted into the Arcadia HIP motherboard, but it is not big enough to restrict access to the carrier communication components. The CDC dimensions are as follows:
• Component height at the top: 15 mm• Component height at the bottom: 4 mm
Figure 4-2 shows the placement of the processor on the daughtercard..
Figure 4-2. CDC with 783 BGA Processor Example
120.0[4.7]
1 cm2
1 in.2
P6880
130.0 [5.1]
160.0 [6.3]
Right-Angle PCI
102.0[4.0]
18.0
90°-Angle DIMM
Heatsink/Fan
CDS Daughtercard Architecture
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4.2 CDS Daughtercard (CDC) Block DiagramFigure 4-3 is a diagram of a CDS daughtercard or a CDC.
Figure 4-3. Daughtercard Block Diagram
This representation is only one, others can be designed for different CPUs.
4.3 ProcessorThe different processors is the primary reason for the existence of the daughtercard, and thus will vary widely in different CDCs. In general, each daughtercard will connect most of its signals to the appropriate ports on the high-density connector. Any bus which does not interface smoothly with the daughtercard/carrier architecture will be handled locally on the daughtercard. This can include:
• Secondary PCI buses• Special power management interface• Compact Flash/IDE interface• Wireless interfaces
4.4 DDR MemoryThe SDRAM connection of DDR-I is handled locally on the CDC. On CDS boards, the processor/DDR interface is connected to the JEDEC DDR SDRAM DIMM socket, capable of holding a maximum of 2 GB of memory. The memory interface includes all the necessary power and is routed to achieve maximum performance on the memory bus.
Further debugging support is handled by expansion logic analyzer interface cards installed in the DIMM socket.
The general DDR SDRAM architecture is shown in Figure 4-4.
PCI/X/Ex
Vtt
DDR SDRAM DIMM
VTTPower
JTAG
I2C ID
CFG
DEBUGCPU
or
CPU/Bridge
LBIF
Local Mem
CorePower
Header(Right)
Header(Left)
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Freescale Semiconductor 4-5
Figure 4-4. CDS Memory Architecture
The memory subsystem bus is single-endedly terminated via series and parallel terminations. Power for the termination plane (VTT) is supplied through a National LP2995, which supplies up to 1.5 A continuously (3 A transient response). This is sufficient for the upper limit generally expected for DDR termination, while actual termination power requirements are significantly less.
In addition, the LP2995 supplies VREF to the processor and DIMMs. The VREF/VTT levels are adjustable using a resistor to alter the threshold slightly. By default, VREF is set to 1.25 V.
As shown in Figure 4-4, the DDR SDRAM parity/ECC pins (MECC[7:0]) are used to display debugging information in certain debug modes. In such a case, the MECC pins must be disconnected from the memory interface (since CB[7:0] from the DDR memories are bidirectional) and routed to the debugging interface connector.
The processor supplies two differential clocks to the memory modules. These signals are not parallel terminated. The signals are described in Table 4-1.
Processor DDR DIMM
MRAS RASCASWECKE[1:0]
A[14:0]
DQ[63:0]
DQS[0:8]DM[8:0]
CB[7:0]
MCASMWE
MCKE[1:0]MCS[1:0]MCS[2:3]MA[14:0]MBA[1:0]
MDQS[8:0]MDM[8:0]
MDQ[63:0]
MCK[0:1]MCK[0:1]
MSYNC_OUT
MVREF
MEM_RST
I2C_SDAI2C_SCK
S[1:0]
BA[1:0]
MCK[2:3]
MSYNC_IN
MCK[2:3]
MECC[7:0]
CK[0:1]CK[0:1]
RESET
SDASCL
VREF
Vte
rm R
esis
tors
and
Dec
oupl
ing
LP2995
VTT
VREF’
Rte
rm
Rte
rmR
term
Rte
rm
VDDQ
MDEBUG QS HeaderMDBG
S[3:2]
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Table 4-1. CDS DDR SDRAM Properties
DDR SDRAM Signal
Description JEDEC DDR SDRAM Module Pin Notes
MRAS Row address strobe RAS 154
MCAS Column address strobe CAS 65
MCS0MCS1
Module bank 0 chip selectModule bank 1 chip select
S0S1
157158
MCS2MCS3
Module bank 2 chip selectModule bank 3 chip select
S2S3
71, 163
MWE Write enable WE 63
MCKE[0:1] Clock enable CKE0CKE1
21111
MDA[0:13] Address A[0:13] 48, 43, 41, 130, 37, 32, 125, 29,122, 27, 141, 118, 115, 103,
MDA14 Address A14 N/A 1
MBA[0:1] Bank select BA0, BA1 59, 52
MDQ[0:63] Memory data DQ[0:63] 2, 4, 6, 8, 94, 95, 98, 99,12, 13, 19, 20, 105, 106, 109, 110,23, 24, 28, 31, 114, 117, 121, 123,33, 35, 39, 40, 126, 127, 131, 133,53, 55, 57, 60, 146, 147, 150, 151,61, 64, 68, 69, 153, 155, 161, 162,72, 73, 79, 80, 165, 166, 170, 171,83, 84, 87, 88, 174, 175, 178, 179
MDQS[0:8] Data strobes (low) DQS[0:8] 5, 14, 25, 36, 56, 67, 78, 86, 47
MDM[0:8] Data strobes (high)/data mask DM[0:8](DQS[9:17])
97, 107, 119, 129, 149, 159, 169, 177, 140
MECC[0:7] ECC data/check bits/debug CB[0:7] 44, 45, 49, 51, 134, 135, 142, 144
MCK[0]MCK_B[0]
Differential clocks CK0CK0
137,138
3
MCK[1]MCK_B[1]
Differential clocks CK1CK1
16,17
3
MCK[2]MCK_B[2]
Differential clocks CK2CK2
76,75
3
MCK[3:5]MCK_B[3:5]
Differential clocks N/A 3
MSYNC_OUT Reference clock output N/A
MSYNC_IN Reference clock input N/A
MVREF SSTL-2 reference voltage VREF 1
MEM_RST Reset RESET 10
I2C_SDA SPD I2C SDA SDA 91
CDS Daughtercard Architecture
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4.4.1 DDR Interface Termination
The termination of the DDR interface is critically important because of its ability to operate at high speeds. The general architecture of the termination is shown in Figure 4-5.
Figure 4-5. CDC Memory Termination
Unlike most series termination usage, for DDR control signals, the 22-Ω termination resistors (1%) are placed near the DDR DIMM. This facilitates routing breakout, which improves the signal integrity of data. This improvement matches the loaded impedance of unidirectional signals on the DIMM (address, command, chip-select).
I2C_SCK SPD I2C SCK SCL 92
N/A SPD write protect WP 90
<var> SPD address SA[0:2] 181, 182, 183 2
GVDD Memory IO power VDDQ 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180
GVDD Memory power VDD 7, 38, 46, 70, 85, 108, 120,148
GND Ground GND 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176
NC VDDID 82
SPD EEPROM power VDDSPD 184
Notes:1. MA14 unused with current JEDEC DDR modules. MA14 is brought out to a termination resistor in the event a standard MA14
is defined for DDR SDRAM modules.2. Address = 3B001 for DIMMs #1.
3. Clock (0:2) for DIMM #1 only. The remaining clock outputs are terminated to ground through a capacitor.
Table 4-1. CDS DDR SDRAM Properties (continued)
DDR SDRAM Signal
Description JEDEC DDR SDRAM Module Pin Notes
Processor
Control 27 Ω
VTTDIMM
22 Ω
27 Ω
Signal
DataSignal
27 p
F
22W22 Ω
Optional
0.1 μF
0.1 μF
0.1 μF
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4-8 Freescale Semiconductor
A 22-Ω resistor is selected to match the processor impedance to the PWB impedance, but can be trimmed or altered as necessary. After daisy-chaining the control signals, the line is extended to a 27-Ω resistor (also 1%) which connects directly to the VTT termination plane.
4.4.2 Recommended Part Numbers
For performance and compatibility purposes, only the devices shown in Table 4-2 are guaranteed to work. Other devices may operate, but architectural issues may affect performance.
4.5 Local Bus InterfaceThe local bus interface of many processors varies widely, including:
• Direct connections for the Tsi106/Tsi107 family• 32-bit multiplexed address/data of the MPC85xx family
To accommodate this flexibility, each daughtercard is responsible for presenting an abstract interface to the carrier board. This interface is designed around a typical Flash/IO-device interface.
For processors which may support high-speed SRAM or SDRAM on their local bus, the daughtercard is responsible for isolating the high-speed devices from the relatively slower-speed local bus (with respect to the carrier board). This has the advantage of supporting the flexibility of the processor local bus interface. It also electrically isolates the high-speed devices from the carrier, which tends to reduce the upper bound of their operating speed.
In addition to the standard interface signals, an additional set of signals (LB_SIZ(1:0)) are generated on the daughtercard. These signals indicate the width of the access to the boot flash and other carrier peripherals. The carrier is responsible for adjusting the local bus interface to those devices, so that they
Table 4-2. CDS DDR SDRAM Compatibility
Manufacturer Size Type Speed Part Number
Samsung 512 MB Unbuff, nonECC DDR400 M368L6523BTM-C(L)CC/C4M368L6423FTN-C(L)CC
DDR333 M368L6423FTN-C(L)B3
DDR266 M368L6423FTN-C(L)AA
512 MB Unbuff, ECC DDR400 M381L6423FTN-C(L)CC
DDR333 M381L6423FTN-C(L)B3
DDR266 M381L6423FTN-C(L)AA
1 GB Unbuff, nonECC DDR400 M368L2923BTM-C(L)CC/C4
Unbuff, ECC DDR400 M381L2923BTM-C(L)CC/C4
Hynix 512 MB Unbuff, nonECC DDR400 HYMD564646A8J-D43
Unbuff, ECC HYMD564726A8J-D43
1 GB Unbuff, nonECC HYMD512646A8J-D43
Unbuff, ECC HYMD512726A8J-D43
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interface properly with the peripherals supported on the carrier. If differing access sizes are needed, LB_SIZ can be generated dynamically, however, it is typically only set to one particular size.
NOTEThe data bus size option only affects how the CDC and carrier provide access to Flash memory (particularly for boot code). It does not affect the ability to generate cycles of any size to other devices; in particular, to the uTCOM/TCOM devices and/or anything else attached to the CPM interface.
Figure 4-6 shows the local bus implementation for the CDC. See Table 3-16 for a description of the local bus interface signals.
Figure 4-6. CDS Local Bus Architecture
Pro
cess
or
LAD[0:31]
LA[27:31]
LBCTL
LALE
SDRAM
LatchDeMux
A
Buf
Q
B
LE
DIR
D Y
DQ[31:0]
A[15:0]
LCS[0:7]
LB_A[27:31]
LB_D[0:31]
LB_DP[0:7]
Buf
LB_A[0:26]
Constant
A10, WE,RAS, CAS
LB_OE, LB_WE
LB_CS
LBCLK
LB_CLK
CLK
LGPL
LB_GPL
LBSYNC
LB_LALE
LMA[0:31]
Buf
LB C
onne
ctor
LB_LBCTL
LB_SZ[0:1]
Buf
Delay
LDP[0:7]
CSLCS2
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Table 4-3 lists the daughtercard connector pins.
The local bus should be routed with careful attention to loading, which is nominally from 6–24 pF. The design goal is 166-MHz operation. The buffered local bus signals are much less critical, typically operating 90–120 ns Flash devices, etc.
4.5.1 Local Bus SDRAM Memory
NOTEParity/ECC is not supported on this interface.
4.6 Passive ConnectionsAlmost all buses on the processor are routed to the carrier board through a high-speed, high-density connection. The exceptions are DDR memory, local bus demultiplexing, local bus memory, and an
Table 4-3. CDS Daughtercard Local Bus Signals
Signal NameMaximum
HSBus Load
Minimum LSBus Load
Notes
LA(27:31) 4 4
LAD(0:31) 3 4
LDP(0:3) 2 4
LALE(0:3) 3 2
LBCTL 4 2 +1 for config connection
LWE(0:3) 2 1
LB_CS0 1 1 Cadmus (for Flash array #1)
LB_CS1 1 1 Cadmus (for Flash array #2)
LB_CS2 4 0 SDRAM
LB_CS3 1 0 Cadmus (for NVRAM/RTC/Cadmus regs)
LB_CS4 1 0
LB_CS5 1 0 Typically TCOM interface
LB_CS6 1 1 Typically TCOM interface
LB_CS7 1 0
LCKE 4 0
LCLK(0:1) 2 0
LCLK(2) 1 1
LGPL 4 2
LSYNC 1 0
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optional second PCI slot. There are two separate connectors to provide easier routing and vacate the area under the processor for mechanical reasons.
The connectors and brief pinout are described in Table 4-4.Table 4-4. CDS Daughtercard Connector Overview
Signal Group SignalsLeft Pin Count
Right Pin Count
Notes
CPM base PA(0:31), PB(4:31), PC(0:31), PD(4:31) 60 60
CPM expansion CX(0:59) 32 Expansion for CE engines
PCI AD[63:0] C_BE[7:0] PAR PAR64 FRAME_B TRDY_B IRDY_B STOP_B DEVSEL_B IDSEL REQ64_B ACK64_B PERR_B SERR_B REQ_B GNT_B LOCK M66EN PCIXCAP PCIRST PCI_DUAL
89 2
Enet MI MDC, MDIO 2
I2C SDA, SCL 2
TSEC1 TSEC1(24:0) 25
TSEC2 TSEC2(24:0) 25
TSEC3 TSEC3(24:0) 25
Local Bus LB_A(0:31) LB_D(0:31) LB_DP(0:3) LB_WE(0:3) LB_CS(0:7) LALE LBCTL LGPL(0:5) LB_CLK LBSIZ(0:1)
91
DMA DMARQ(0:1)DMACK(0:1)DMADN(0:1)
6
Interrupt IRQ(0:11) 12
System Control PWRGD, MCP, UDE, HRESET, SRESET, CFGRST, CFGDRV, HRESETREQ, ASLEEP
6 2
DUART S1_SI, S1_SO, S1_RTS, S1_CTSS2_SI, S2_SO, S2_RTS, S2_CTS
8
I2C SDA, SCK 2
Clock SYSCLK 1
PCICLK 1
GTXCLK 1 125 MHz PHY clock
RTC 1
Misc OVM 1
Power 5.0V VCC_5 0 16 Imax = 7.2 A, Pmax = 36.0 W
Power 3.3V VCC_3.3 17 13 Imax = 13.5 A, Pmax = 44.5 W
Power 2.5V VCC_2.5 22 19 Imax = 18.5 A, Pmax = 46.2 W
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Note: The FCI connector supports 0.45 A/pin.
4.7 Carrier PinoutsFor a detailed pinout, including numbering, refer to Appendix B.1, “Carrier/DaughterCard Connectors Pinout.”
4.8 ClockThere are five pre-defined clock sources available to the CDC, as detailed in Table 4-5.
As discussed in Section 3.8, “Clock,” clocks may or may not be synchronous to any other clock. Also, they may or may not be synchronous to the de-assertion timing of HRESET. Such an environment is determined by the carrier board.
Power +12V VCC_12V 2 0 Imax = 0.9 A, Pmax = 10.8 W
Power –12V VCC_12N 0 1 Imax = 0.5 A, Pmax = 5.4 W
Ground GND 95 86
USB 2.0 U1_TP, U1_TN, U1_OCU2_TP, U2_TN, U2_OC
6
Subtotal 387 344
Spares 13 56 Bring up to next connector size
Total 400 400
Table 4-5. CDC Clocks
Clock Signal Interface Rate Notes
PCICLK LVTTL 33–66 MHz Generally supplied by either the PCI clock of the HIP motherboard, or the local clock of the carrier. Used by processors/bridge logic which operate synchronous to the PCI interface.
PCICLK2 LVTTL 66 MHz Created by the CDC for cards with secondary PCI slots. An on-board oscillator is provided to generate this clock (which is independent of all other clocks).
SYSCLK LVTTL 0–300 MHz Supplied by the HIP motherboard, independent of the PCICLK rate. Used by processors/bridge logic which operate asynchronous to the PCI interface.
RTCCLK 512 MB 16 MHz Timebase clock
GTXCLK 1 GB 125 MHz Clock for GBit Ethernet PHYs and/or interfaces.
Table 4-4. CDS Daughtercard Connector Overview (continued)
Signal Group SignalsLeft Pin Count
Right Pin Count
Notes
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4.9 PCI/PCI-XThe PCI/PCI-X signals from the primary PCI interface of the processor are connected to the edge connector of the CDS carrier board. In addition, some processors have a secondary PCI interface, which may operate independently of the primary PCI bus. If implemented, the optional PCI interface is connected to a PCI connector on the CDC, and is completely independent of the primary PCI interface.
For systems which switch between one 64-bit and two 32-bit PCI interfaces, isolation logic is necessary to isolate the secondary PCI interface from the 64-bit PCI extensions, as shown in Figure 4-7.
Figure 4-7. CDS Dual-PCI Architecture
NOTEThe secondary PCI interface does not detect the bus speed via M66EN/PCIXCAP; instead these settings are specified manually.
The resulting connections and notes are listed in Table 4-6.
4.10 ResetThe daughtercard receives a reset signal (HRESET) from the carrier board and sends it to the processor(s), bridge logic, and memory. This reset signal is merged with the JTAG header JTAG_HRST to allow either source to reset the processor.
Table 4-6. CDC PCI2 IDSEL Mapping
PCI2 IDSEL
Device
20 Processor
21 PCI2 slot
Processor
SecondaryPCI
PrimaryPCI
PCI #2 (32-Bit Part)
PCI #1 (32bit part)
(via CarrierEdge Fingers)
(via Right-Angle Slot)
PCI #1 (64-Bit Part))
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A second reset (CFGRST) is optionally asserted along with HRESET. They have the same period and edge rate, but CFGRST is delayed one clock cycle. This signal is used to drive configuration data onto processor/bridge configuration pins, which in turn are sampled at the rising edge of HRESET.
The daughtercard can also drive a reset to the carrier using the signal HRST_REQ, and possibly to the motherboard (this is motherboard-dependent). Processors may use this to reset themselves, and optionally the entire system as well.
The general reset architecture is shown in Figure 4-8.
Figure 4-8. CDS Daughtercard Reset Architecture
4.11 ExceptionsInterrupts are generally handled transparently on the carrier, with little interference by the CDC. One exception is when special-purpose localized interfaces are present on the CDC (such as a second PCI interface, special PHY or other interrupt-generating device), on dedicated interfaces or the local bus.
The carrier connections and notes were previously described in Table 3-21, but they also apply to local CDC connections. Note that the CDCs are allowed considerable leeway in assigning/sharing localized and global interrupts, as long as sharing is compatible, and documented. Table 4-7 shows the properties of the local CDS exceptions as they apply to the CDC.
Processor
CFGRST
HRESET
SRESET
JTAG_TRST
JTAG_SRST
HRESET
SRESET
TRST
CDS CDC
HRST_REQ
JTAG_HRST
HRST_REQ
JTAG
CFG_PINSW
COP_HRESET
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4.12 I2CThe processor module generally supports one or more I2C ports for storage of initialization and configuration settings. The overall block diagram of the CDC I2C bus is shown in Figure 4-9.
Figure 4-9. CDS Daughtercard I2C Architecture
Table 4-7. CDS Exception Properties
CDS Signal
Carrier Connection
CPUCard Connection
Routing
IRQ0 INTA PCI edge connector INT(A:D)
IRQ1 INTB
IRQ2 INTC
IRQ3 INTD
IRQ4 Reserved Reserved
IRQ5 MDINT On-board QuadPHY
IRQ6 ATMINT ATM PHY interrupt
IRQ7 CMINT CPLD interrupt (typically DMA)
IRQ8 Reserved Reserved
IRQ9 PERINT NVRAM/RTC periodic interval timer
IRQ10 DEBUG Debug event switch (s/w managed)
IRQ11 PCI2_INTA# Second PCI bus slot interrupts
INITEEPROM
DDR SPDEEPROM
#1
CDC IDEEPROM
To CarrierMonitorADCS
VCORE, THERM, etc. To Switches
CONFIG/RemoteControl
I2CProcessor
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The CDC provides the I2C resources listed in Table 4-8.
4.13 ConfigurationAs with the CDS, CDCs include a large number of configuration options. Due to a variance in configuration needs of processors/bridge logic, this section is dependent on the CDC processor.
Some options are designed to be easily changeable, and use the same I2C-overrideable switch configuration logic used on the carrier (see Section 3.13, “Configuration”). Other infrequently used options are implemented with optional resistor installation, requiring removal and/or installation of SMT resistors.
Configuration options fall into two classes: persistent and dynamic. Persistent configuration values are connected to dedicated pins which have no other function. These signals can be connected to resistors or switches, but no other help is needed. Dynamic configuration values are determined by sampling a pin at reset, after which time the pin reverts to some other function.
4.14 PowerPower for the processor core, as well as other logic on the daughtercard, comes from the +2.5- and +3.3-V power supplies. A +12 V power supply is also available for fan-sink power and switching gate drive, but not in sufficient amperage to derive any significant power from it. Table 4-9 summarizes the available power to HIP cards.
Table 4-8. CDS Daughtercard I2C Bus Properties
I2C Device I2C Device I2C Address Data Size Notes
Remote control/configuration port PCA9555 0x18 (0011_000x)0x19 (0011_001x)0x1A (0011_010x)0x1B (0011_011x)
8
System configuration EEPROM AT24C64A 0x50 (1010_000x) 8192 1
DDR SDRAM SPD EEPROM AT24LC02 0x51 (1010_001x) 256 2
CDC ID EEPROM AT24C64A 0x57 (1010_111x) 8192
Voltage monitor ADCs MAX1036 0xC8 (1100_100x) 16
Notes:
1. Only extended address I2C EEPROM devices are supported.2. Device shown is just a compatible example; this device is actually on the DIMM memory module.
Table 4-9. CDC Available Power
Power Pins × Current Current Power
+2.5 V 41 × 0.45 A 18.5 A 46.2 W
+3.3 V 30 × 0.45 A 13.5 A 44.5 W
+5.0 V 16 × 0.45 A 7.2 A 36.0 W
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The power budget must be compared to approximately 170 W available to the carrier, and to the portion of that power required for the carrier itself.
4.14.1 Processor Core Power
Core power (VDD) to the processor is supplied using a switching regulator. It is capable of supplying core voltages in the range 0.925–2.0 V in 25-mV steps over the lower range (0.925 to 1.275 V), and 5-mV steps elsewhere. Up to 15 A (14–30 W) is available, though most processors use much less than that. The core power is trimmed using the standard switch +I2C override method, or using the low-power VRM encoding standards as shown in Table 4-10.
The processor core power flows through a Maxim (MAX4372FEUK) current-measuring device. This analog measurement circuit outputs a voltage corresponding to the current demand of the processor, measured across a low-ohm resistor. The analog signal is conditioned and measured with an I2C-based
+12 V 2 × 0.45 A 0.9 A 10.8 W
Total 137.5 W
Table 4-10. CDC VDD (Vcore) Encoding Table
VIDOutput Voltage
VIDOutput Voltage
4 3 2 1 0 4 3 2 1 0
1 1 1 1 1 OFF1 0 1 1 1 1 OFF1
1 1 1 1 0 0.925 V 0 1 1 1 0 1.300 V
1 1 1 0 1 0.950 V 0 1 1 0 1 1.350 V
1 1 1 0 0 0.975 V 0 1 1 0 0 1.400V
1 1 0 1 1 1.000 V 0 1 0 1 1 1.450 V
1 1 0 1 0 1.025 V 0 1 0 1 0 1.500 V
1 1 0 0 1 1.050 V 0 1 0 0 1 1.550 V
1 1 0 0 0 1.075 V 0 1 0 0 0 1.600 V
1 0 1 1 1 1.100 V 0 0 1 1 1 1.650 V
1 0 1 1 0 1.125 V 0 0 1 1 0 1.700 V
1 0 1 0 1 1.150 V 0 0 1 0 1 1.750 V
1 0 1 0 0 1.175 V 0 0 1 0 0 1.800 V
1 0 0 1 1 1.200 V 0 0 0 1 1 1.850 V
1 0 0 1 0 1.225 V 0 0 0 1 0 1.900 V
1 0 0 0 1 1.250 V 0 0 0 0 1 1.950 V
1 0 0 0 0 1.275 V 0 0 0 0 0 2.000 V
Note:1. The 1.250- and 0.900-V options may be selected by configuring the MAX1813 to 50-mV step mode (remove resistor R___)
and setting the code to 01010 or 10011, respectively. Refer to the MAX1813 datasheet for other codes when in this mode.
Table 4-9. CDC Available Power
Power Pins × Current Current Power
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ADC (Maxim MAX1037EKAT, channel 0). The resulting measurement is compared to a 2.048-V reference, and produces a value from 0 to 2048, corresponding to the current shown in Table 4-11.
Since the ADC uses an external reference derived from the same power plane as the measured VDD power controller, resulting in some inaccuracy. Software can calibrate the ADC periodically to remove the error.
4.14.2 DDR VREF/Vt Power
The DDR memory reference (MVREF) and termination power is supplied (by an LP2995) 1.5-A steady-state, and up to 3.0-A transient.
4.15 Diagnostic FeaturesDue to space limitations, the CDC is generally restricted in how much debugger support can be provided. Where possible, debug support was deferred to external devices, such as JTAG emulation, DDR module adapters, etc. However, a certain minimal amount of debug support is included on the CDC to support initialization, and to avoid routing signals to the carrier for debug purposes.
4.15.1 Logic Analyzer Header
The majority of the debug facilities are located on the carrier board (local bus, etc.), and some are debugged through adapter modules (DDR DIMM adapter). The few signals debugged on the daughtercard are listed in Table 4-12.
Table 4-11. CDC ADC Current Measurement Conversion Table
CPU Current I-to-V OutputConditioned ADC Input
ADC Measurement
0.0 A 0.00 V 0.0 V 0
1.0 A 0.25 V 0.1 V 100
...
10.0 A 2.50 V 1.0 V 1000
...
15.0 A 3.75 V 1.5 V 1500
...
20.0 A 5.00 V 2.0 V 2000
Table 4-12. CDS Daughtercard P6860 Analyzer Header Definition
Pin Signal Description
A1 MSRCID[0]
A3 MSRCID[1]
A4 MSRCID[2]
A6 MSRCID[3]
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4.15.2 JTAG Header
This 2x10-pin Berg header is typically used with JTAG/ICE controllers to download target code and control code execution from a remote computer. The pinout is shown in Table 4-13.
A7 MSRCID[4]
A9 MDVAL
A10 TRIG_OUT
A12 TRIG_IN
A13 CLK_OUT
A15 HRESET
B1 MDBG(0)
B3 MDBG(1)
B4 MDBG(2)
B6 MDBG(3)
B7 MDBG(4)
B9 MDBG(5)
B10 MDBG(6)
B12 MDBG(7)
Table 4-13. CDS JTAG Header
Pin Signal Definition
1 TDO CPU JTAG TDO output
2 n/c Pulled up to OVDD
3 TDI CPU JTAG TDI input
4 TRST CPU JTAG TRST input
5 N/C Pulled up to OVDD
6 VDD +3.3 V power
7 TCK CPU JTAG TCK input
8 CKSTP_I CPU CHKSTP_IN input
9 TMS CPU JTAG TMS input
10 N/C N/C
11 SRST CPU SRESET input
12 GND Ground (non-standard)
Table 4-12. CDS Daughtercard P6860 Analyzer Header Definition (continued)
Pin Signal Description
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The connector is physically arranged as shown in Table 4-14. Other pin numbering schemes are popular, however, the correspondence between each pin and the ‘picture’ in Table 4-14 is correct, whatever the pin number may be.
4.15.3 LEDs
Table 4-15 describes the diagnostic LEDs on the CDC card.
13 HRST CPU HRESET input
14 KEY No pin present
15 CKSTP_O CPU CHKSTP_OUT output
16 GND Ground
Table 4-14. CDS COP Header Definition
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
Table 4-15. CDC Diagnostic LEDs
PCB Label LED Definition Activation Method
VDD3 D4 +3.3-V power active Power applied
OVDD D2 +2.5-V power active Power applied
VCORE D3 VDD (Vcore) power active Power applied
BOOT D10 LCS0* active Boot/read/write to local bus Flash
MEM D9 LCS2* active Read/write/refresh to DDR SDRAM
SLEEP D8 CPU asleep (or PLL not locked) ASLEEP asserted
PCI1 D6 PCI 1 bus activity PCI1_DEVSEL# (resistively sampled near CPU)
PCI2 D5 PCI 2 bus activity PCI2_DEVSEL# (resistively sampled near CPU)
DUAL D1 PCI dual bus modes Switch selected
CLOCK D7 Clock active SYSCLK and/or PCICLK running
RESET D11 Reset active HRESET asserted
Table 4-13. CDS JTAG Header (continued)
Pin Signal Definition
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4.15.4 Test Points
Test points are added to critical signals to aid in bringup and testing. The test point list is shown in Table 4-16.
Table 4-16. CDS Test Point List
Test Point Definition
TP6 CPU Spare01
TP8 CPU Spare02
TP10 CPU Spare10
TP7 CPU Spare13
TP11 WP for I2C EEPROM
U7 Spare analog ADC input
U2 Spare left connector
TP1 Spare left connector
U30 Spare right connector
U31 Spare right connector
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Chapter 5 Arcadia Motherboard ArchitectureThe following sections describe information on the Arcadia Version 3 reference platform, also referred to as Arcadia x3 or Arcadia V3. Arcadia is a flexible evaluation and development platform support, and serves several support purposes:
• As a backplane for evaluation of CDS-based boards (PowerQUICC III network host processors)• As a backplane for high-speed communications protocols (RapidIO, PCI Express, and others)
between hardware interoperability platform (HIP) compliant boards. • Arcadia contains a pair of HIP-compliant slots, four PCI/PCI-X slots, one PrPMC connector, and
sufficient system resources (clock, power, arbitration, IDE disk access, PS/2 ports) to allow the system to boot an operating system (Linux).
5.1 FeaturesThe Arcadia development platform supports many combinations of HIP cards, PrPMC modules (including MPMC cards), and PCI/PCI-X cards (hereafter, PCI-X will be used unless PCI is specifically referred to).
Accordingly, Arcadia includes the following features:• Two RapidIO HIP slots
— 40 differential pairs— Protocol-free— Unlimited speed
• Six PCI slots— Four 3 3-V PCI-X slots and PCI bridge at 66-MHz speeds (all 32- or 64-bit)— Two 5-V, 32-bit PCI slots at 33-MHz speeds
• PrPMC connector— 33-MHz bus speeds— 5-V interfaces— PrPMC/MPMC compatible
• PCI-X/PCI bridge— 66-MHz PCI-X to 33-MHz PCI bridge— Allows fast PCI/PCI-X traffic without being limited by VIA PIPC
• PCI integrated peripheral controller (PIPC)— Dual UDMA100 IDE disk controller— Dual USB interface
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— Floppy disk controller— Dual serial ports
• ATX motherboard form-factor
Figure 5-1 shows a block diagram of the Arcadia motherboard.
5.2 ConfigurationsArcadia’s flexible, non-specific motherboard allows it to be used for several purposes, such as:
• CDS motherboard for CDS development purposes• HIP-compatible parallel/serial RapidIO motherboard
With the on-board VIA PIPC and Ethernet, operating systems such as Linux, QNX, VxWorks, ENEA/OSE, and others can be easily ported. The use of industry-standard components means that porting existing Sandpoint BSP and application code should be relatively easy, though it is not code compatible.
5.2.1 CDS Motherboard
As a CDS motherboard, Arcadia also supports the use of CDS development/evaluation boards, such as the CDS for the MPC8555E, MPC8541E, MPC8548E, the PowerQUICC III family, and others; PMC cards such as the MPC7447-Valis, MPC7410-Altimus, MPC8245-Unity, and other network/control processor cards; and HIP boards such as the Freescale MARS:Elysium, the Freescale MARS:Auxo, and the Tundra TSI500 evaluation boards, as well as any other HIP-compatible boards.
Figure 5-1 shows an example usage in this mode.
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Figure 5-1. CDS-Compatible Arcadia Block Diagram
In general, the CDS view of the system exposes all the hardware resource features.
5.3 ArchitectureThe following sections cover the Arcadia design in more detail. The general features of Arcadia are summarized in Table 5-1.
PCI-X/
Clock
Pw
rH
MZ
D
PrPMC
PCIBridge
IDE/USBSystem
I/O
Slot 7 Slot 6 Slot 5 Slot 4 Slot 3 Slot 2
HIPSlot 2 HIPSlot 1
ARCSystem Control
and PCIBootH
MZ
D
Pw
r PCI4
PCI3
Omni
PCI1
OmniLVDS0–3 GHz40-Bit
PCI/PCIX5 V33 MHz32-Bit
PCI/PCIX3 V33–66 MHz64-Bit
PCI3 V33 MHz32-Bit
RealTekEthernet
PCI4 PCI3 PCI1
ISO
1(+
Shi
ft)
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5.4 Omni BusThe Arcadia platform supports a protocol-independent connection called the Omni bus. The Omni bus is a set of 40 pairs of LVDS signals, grouped into a set of unidirectional transmit and receive sets (20 pair). As long as two cards can transmit all signals on the transmit pairs, and receive correspondingly on the receive pairs, they can communicate using any protocol that will fit.
This is also the case if both the boards agree that certain signals are:• Inputs only• Bidirectional but open-drain driven (for example, interrupts)
Figure 5-2 shows an example of the cross-over connection that allows the two slots to communicate without the requirement of an intermediary interface (which would restrict the connection to only one type of protocol).
Table 5-1. Arcadia Architecture Feature Summary
Bus Connections SizeTheoretical Maximum
SpeedDescription Notes
Omni HIPSlot #1HIPSlot #2
40 differential pairs 3.2 GHz 8-bit parallel RapidIO16-bit parallel RapidIO1x serial RapidIO4x serial RapidIOPCI Express
1
PCI 3/PCI 4
PrPMCSlot #6Slot #7PCI bridge secondaryVIA PIPCEthernet
32-bit 33 MHz PCI/PCI-X data bus
PCI 1 Slot #2Slot #3Slot #4Slot #5PCI bridge primarySystem Control
64-bit 33–66 MHz PCI/PCI-X data bus 2
Clocks PrPMC and PCI 1-bit 33 MHz Reference clock
Interrupts PrPMC and PCI 4-bit N/A Interrupt bus
Reset PrPMC and PCI 1-bit N/A PCI reset signal
Power HIP, PCI, and PrPMC N/A N/A Card power
Notes:1. The maximum speed of the Omni port is limited only by the rates of the HIP cards used, and by skew and
cross-talk issues on the Arcadia connector traces (if any).
2. Non-MPMC cards, such as VITA PrPMC cards, are not supported.
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.
Figure 5-2. Arcadia RapidIO Port Connections
5.4.1 Parallel RapidIO
Table 5-2 describes the pinout of the high-speed port connector, when the parallel RapidIO protocol is in use. This pinout is as defined by the RapidIO Trade Association TWG document, RapidIO Hardware Interoperability Platform (HIP) Specification.
Table 5-2. Arcadia Parallel RapidIO Connector Definition
Pin Definition Pin Definition Pin Definition Pin Definition
A1, B1 RD0, RD0 C1, D1 RD8, RD8 E1, F1 TFRM1, TFRM1 G1, H1 TFRM, TFRM
A2, B2 RD1, RD1 C2, D2 RD9, RD9 E2, F2 TD15, TD15 G2, H2 TD7, TD7
A3, B3 RD2, RD2 C3, D3 RD10, RD10 E3, F3 TD14, TD14 G3, H3 TD6, TD6
A4, B4 RD3, RD3 C4, D4 RD11, RD11 E4, F4 TD13, TD13 G4, H4 TD5, TD5
A5, B5 RCLK0, RCLK0 C5, D5 RCLK1, RCLK1 E5, F5 TD12, TD12 G5, H5 TD4, TD4
A6, B6 RD4, RD4 C6, D6 RD12, RD12 E6, F6 TCK1, TCK1 G6, H6 TCK0, TCK0
A7, B7 RD5, RD5 C7, D7 RD13, RD13 E7, F7 TD11, TD11 G7, H7 TD3, TD3
A8, B8 RD6, RD6 C8, D8 RD14, RD14 E8, F8 TD10, TD10 G8, H8 TD2, TD2
A9, B9 RD7, RD7 C9, D9 RD15, RD15 E9, F9 TD9, TD9 G9, H9 TD1, TD1
A10, B10 RFRM, RFRM C10, D10 RFRM1, RFRM1 E10, F10 TD8, TD8 G10, H10 TD0, TD0
Note:1. BG(1:10), DG(1:10), FG(1:10), and HG(1:10) are all connected to system ground.
Slot 2
Path A
Path B
Transmit
Receive
Slot 1
Transmit
Receive
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5.4.2 Serial RapidIO
Table 5-3 describes the pinout of the high-speed port connector, when the parallel RapidIO protocol is in use. This pinout is as defined by the RapidIO Trade Association TWG document, RapidIO Hardware Interoperability Platform (HIP) Specification.
5.4.3 PCI Express
Table 5-4 describes the pinout of the high-speed port connector when the PCI Express protocol is used.
NOTEThis is not a standard currently supported on HIP platforms and careful interoperability setup is required.
Table 5-3. Arcadia Serial RapidIO Connector Definition
Pin Definition Pin Definition Pin Definition Pin Definition
A1, B1 R1D1, R1D1 C1, D1 R3D1, R3D1 E1, F1 G1, H1
A2, B2 C2, D2 E2, F2 G2, H2
A3, B3 C3, D3 E3, F3 G3, H3
A4, B4 C4, D4 E4, F4 G4, H4
A5, B5 C5, D5 E5, F5 T4D1, T4D1 G5, H5 T2D1, T2D1
A6, B6 R2D1, R2D1 C6, D6 R4D1, R4D1 E6, F6 G6, H6
A7, B7 C7, D7 E7, F7 G7, H7
A8, B8 C8, D8 E8, F8 G8, H8
A9, B9 C9, D9 E9, F9 G9, H9
A10, B10 C10, D10 E10, F10 T3D1, T3D1 G10, H10 T1D1, T1D1
Notes:1. BG(1:10), DG(1:10), FG(1:10), and HG(1:10) are all connected to system ground.2. Blank cells are no connect.
Table 5-4. Arcadia PCIExpress Connector Definition
Pin Definition Pin Definition Pin Definition Pin Definition
A1, B1 rx0 (p,n) C1, D1 rx8 (p,n) E1, F1 G1, H1
A2, B2 rx1 (p,n) C2, D2 rx9 (p,n) E2, F2 tx15 (n,p) G2, H2 tx7 (n,p)
A3, B3 rx2 (p,n) C3, D3 rx10 (p,n) E3, F3 tx14 (n,p) G3, H3 tx6 (n,p)
A4, B4 rx3 (p,n) C4, D4 rx11 (p,n) E4, F4 tx13 (n,p) G4, H4 tx5 (n,p)
A5, B5 CLK125, n/a C5, D5 E5, F5 tx12 (n,p) G5, H5 tx4 (n,p)
A6, B6 rx4 (p,n) C6, D6 rx12 (p,n) E6, F6 G6, H6
A7, B7 rx5 (p,n) C7, D7 rx13 (p,n) E7, F7 tx11 (n,p) G7, H7 tx3 (n,p)
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5.5 PCI/PCI-X BusThe Arcadia platform contains two independent PCI buses: a low-speed legacy PCI bus (the secondary PCI bus) and a high-speed PCI/PCI-X bus (the primary PCI bus). The Tundra TSI310 PCI-to-PCI bridge spans these two buses.
All cards and devices on the secondary PCI bus operates in PCI mode (no PCI-X) and at 33 MHz only (if this is a 5-V bus); 66 MHz can be supplied, but this is not in compliance with the PCI specifications. Slots 6 and 7, the PIPC (PCI I/O), and Ethernet interfaces are present on this bus.
The primary bus supports operation at 33 and 66 MHz, using bus mode and speed detection to select the appropriate speed.
Because of the numerous PCI buses and bus-fragments, the following nomenclature is used when referring to specific portions of the PCI bus:
PCI <Bus> <Fragment> ‘_’ PCI_Signal
where:<Bus> ‘A’ for the high-speed primary bus, or
‘B’ for the slower secondary bus.<Fragment> ‘1’ for primary bus
‘4’ for the PrPMC part of the secondary bus, or‘3’ for the 3-V isolated part of the secondary bus.
Thus, a signal such as PCIA3_FRAME refers to the conventional PCI FRAME signal that is routed between the ISO 3 buffer and slots 4 and 5. This notation is also used on the schematics.
Table 5-5 describes the pinout of the high-speed port connector when the PCI Express protocol is used.
NOTEThis is not currently a standard supported on HIP platforms and so implies that careful interoperability setup is required.
A8, B8 rx6 (p,n) C8, D8 rx14 (p,n) E8, F8 tx10 (n,p) G8, H8 tx2 (n,p)
A9, B9 rx7 (p,n) C9, D9 rx15 (p,n) E9, F9 tx9 (n,p) G9, H9 tx1 (n,p)
A10, B10 RST#, n/a C10, D10 E10, F10 tx8 (n,p) G10, H10 tx0 (n,p)
Notes:1. BG(1:10), DG(1:10), FG(1:10), and HG(1:10) are all connected to system ground.2. The notation (p,n) refers to positive and negative halves of the differential pair, and are assigned to the respective
pin. The notation (n,p) is the same, but reversed.3. Blank cells are no connect.
Table 5-4. Arcadia PCIExpress Connector Definition (continued)
Pin Definition Pin Definition Pin Definition Pin Definition
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5.5.1 PCI Arbitration
The Arcadia contains two separate PCI buses (separated by the PCI bridge). Figure 5-3 shows a block diagram of the PCI arbitration domains.
Table 5-5. Arcadia PCIBus Name Examples
PCI Signal Connects to
PCIA_FRAMEor
PCIA1_FRAME
PCIBridge primary side,HIPSlot 1 (PCI Slot 2),PCI Slot 4,HIPSlot 1 (PCI Slot 5)
PCIB3_FRAME PCIBridge secondary side,ARC PCI interface,PCI B isolation buffer 3
PCIB4 PCI B isolation buffer 4,EthernetVIA PIPCPrPMCPCI Slot 6PCI Slot 7
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Figure 5-3. Arcadia PCI Arbitration Domains
For PCI A, the PCI/PCI-X high-speed bus, the arbitration is handled by the system control logic which provides transparent, high-speed access. For PCI B, the slow-speed bus, arbitration is handled by the Tundra TSI310.
Table 5-6. PCI Arbitration Ports
Component Bus Arbiter Port Notes
PrPMC B4 PCIB4_REQ/GNT*(1:5) 4
Secondary PCI Bridge B3 PCIB3_REQ/GNT*(1:5) N/A Internally port 0
ARC B3 N/A N/A Non-bus-master
RTK8139 Ethernet B4 PCIB4_REQ/GNT*(1:5) 2
VIA 82C686B B4 PCIB4_REQ/GNT*(1:5) 3
Slot 6 B4 PCIB4_REQ/GNT*(1:5) 1
Slot 7 B4 PCIB4_REQ/GNT*(1:5) 5
Clock
Pw
rH
MZ
D
PrPMC
IDE/USBSystem
I/O
Slot 7 Slot 6 Slot 5 Slot 4 Slot 3 Slot 2
HIPSlot 2 HIPSlot 1
ARCSystem Control
and PCIBoot
HM
ZD
P
wr PCI4
PCI3
Omni
PCI1
OmniLVDS0–3 GHz40-Bit
PCI/PCIX5 V33 MHz32-Bit
PCI/PCIX3 V33–66 MHz64-Bit
PCI3 V33 MHz32-Bit
RealTekEthernet
PCI4 PCI3 PCI1
Shi
fter
PCI-X/PCI
Bridge
PCI A
PCI B
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5.5.2 PCI Host Mode
As with all HIP systems, all components on the board are peers. That is, any one (or multiple) HIP and/or PrPMC cards can service interrupt requests. This is essential, as in some configurations, a HIP card or a PrPMC card may not be present.
To accommodate this maximum flexibility, Arcadia does not enforce which slot/device will serve as host. Configuration and design ensure that each device is capable of servicing an interrupt from any location.
NOTEDespite common belief, the concept of host is not inextricably tied to being the arbiter. The arbiter can be, and indeed is, located on a central resource (the system logic) completely independent of whatever card is designated as the host.
Only one device on each PCI domain is allowed to perform configuration cycles. This is enforced by software and/or hardware slot detection.
5.5.3 PCI Bridge
The PCI/PCIX slots are isolated from the PIPC, PrPMC, and Ethernet by the Tundra TSI310 PCI-to-PCI bridge. The primary (PCI-X) interface runs at up to 66 MHz, while the secondary is limited to 33 MHz to match the capabilities of the VIA PIPC.
5.5.4 PCI Interrupts
Arcadia has several interrupt sources, including:• Four PCI slot interrupts (shared among six slots). Four slots on primary bus and two slots on the
secondary bus.• Ethernet interrupt• VIA southbridge interrupt (USB and IDE)• PrPMC interrupts
Figure 5-4 shows a block diagram of the PCI interrupt flow.
Primary PCI Bridge A PCIA_REQ/GNT*(0:4) 0
Slot 2 A 1
Slot 3 A 2
Slot 4 A 3
Slot 5 A 4
Table 5-6. PCI Arbitration Ports (continued)
Component Bus Arbiter Port Notes
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Freescale Semiconductor 5-11
Figure 5-4. Arcadia PCI Interrupts Domains
To allow the PrPMC to service interrupts from PCI1, or HIP cards to service interrupts from the PrPMC, Southbridge, or Ethernet, the system logic contains interrupt steering logic to allow interrupts to be replicated in one direction or the other (depending on where the host is placed).
NOTEAs the PMC slot is typically occupied by a control-plane Freescale PrPMC, the standard software from Freescale and many legacy board support packages reflect this viewpoint in software initialization sequences. For a shared co-processing environment, a more complicated interrupt allocation software will be required.
The slot interrupts are assigned in a conventional rotating pattern, where the INTA output of each card is assigned to successive portions of the common INT(0:3) bus, respectively.
Clock
Pw
rH
MZ
D
PrPMC
Slot 7 Slot 6 Slot 5 Slot 4 Slot 3 Slot 2
HIPSlot 2 HIPSlot 1
ARC
and PCIBootH
MZ
D
Pw
r
PCI4
PCI3
Omni
OmniLVDS0–3 GHz40-Bit
PCI/PCIX5 V33 MHz32-Bit
PCI/PCIX3 V33–66 MHz64-Bit
PCI3 V33 MHz32-Bit
PCI4 PCI3 PCI1
PCI-X/PCI
Bridge
PCI A
Int.Bridge
Shi
fter
IDE/USB
I/OSystem
RealTekEthernet
PCI1
System Control
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Table 5-7. Arcadia 3.1 Interrupt Assignments
DevicePCI INT
PinCDS Interrupt
BusAttached Devices by Connection Notes
Slot #2 INTA# PCIA1_INT0 Slot2 INTA# | Slot3 INTD# | Slot4 INTC# | Slot 5 INTA# 2
INTB# PCIA1_INT1 Slot2 INTB# | Slot3 INTA# | Slot4 INTD# | Slot 5 INTB#
INTC# PCIA1_INT2 Slot2 INTC# | Slot3 INTB# | Slot4 INTA# | Slot 5 INTC#
INTD# PCIA1_INT3 Slot2 INTD# | Slot3 INTC# | Slot4 INTB# | Slot 5 INTD#
Slot #3 INTA# PCIA1_INT1 Slot2 INTB# | Slot3 INTA# | Slot4 INTD# | Slot 5 INTB# 2
INTB# PCIA1_INT2 Slot2 INTC# | Slot3 INTB# | Slot4 INTA# | Slot 5 INTC#
INTC# PCIA1_INT3 Slot2 INTD# | Slot3 INTC# | Slot4 INTB# | Slot 5 INTD#
INTD# PCIA1_INT0 Slot2 INTA# | Slot3 INTD# | Slot4 INTC# | Slot 5 INTA#
Slot #4 INTA# PCIA1_INT2 Slot2 INTC# | Slot3 INTB# | Slot4 INTA# | Slot 5 INTC# 2
INTB# PCIA1_INT3 Slot2 INTD# | Slot3 INTC# | Slot4 INTB# | Slot 5 INTD#
INTC# PCIA1_INT0 Slot2 INTA# | Slot3 INTD# | Slot4 INTC# | Slot 5 INTA#
INTD# PCIA1_INT1 Slot2 INTB# | Slot3 INTA# | Slot4 INTD# | Slot 5 INTB#
Slot #5 INTA# PCIA1_INT3 Slot2 INTD# | Slot3 INTC# | Slot4 INTB# | Slot 5 INTD# 2
INTB# PCIA1_INT0 Slot2 INTA# | Slot3 INTD# | Slot4 INTC# | Slot 5 INTA#
INTC# PCIA1_INT1 Slot2 INTB# | Slot3 INTA# | Slot4 INTD# | Slot 5 INTB#
INTD# PCIA1_INT2 Slot2 INTC# | Slot3 INTB# | Slot4 INTA# | Slot 5 INTC#
PrPMC INTA# PCIB4_INT0 PrPMC_INTA# | VIA_INTA# | ARC_INTA# | Slot6 INTC# | Slot7 INTB#
INTB# PCIB4_INT1 PrPMC_INTB# | VIA_INTB# | ARC_INTB# | Slot6 INTD# | Slot7 INTC#
INTC# PCIB4_INT2 PrPMC_INTC# | VIA_INTC# | | Slot6 INTA# | Slot7 INTD#
INTD# PCIB4_INT3 PrPMC_INTD# | VIA_INTD# | | Slot6 INTB# | Slot7 INTA#
VIAVIA
INTA# PCIB4_INT0 PrPMC_INTA# | VIA_INTA# | ARC_INTA# | Slot6 INTC# | Slot7 INTB#
INTB# PCIB4_INT1 PrPMC_INTB# | VIA_INTB# | ARC_INTB# | Slot6 INTD# | Slot7 INTC#
INTC# PCIB4_INT2 PrPMC_INTC# | VIA_INTC# | | Slot6 INTA# | Slot7 INTD#
INTD# PCIB4_INT3 PrPMC_INTD# | VIA_INTD# | | Slot6 INTB# | Slot7 INTA#
SIOINT PCIB4_INT0PCIB4_INT1
PrPMC_INTA# | VIA_INTA# | ARC_INTA# | Slot6 INTC# | Slot7 INTB# 1
Ethernet INTA# PCIB4_INT1 PrPMC_INTB# | VIA_INTB# | ARC_INTB# | Slot6 INTD# | Slot7 INTC#
Slot #6 INTA# PCIB4_INT2 PrPMC_INTC# | VIA_INTC# | | Slot6 INTA# | Slot7 INTD#
INTB# PCIB4_INT3 PrPMC_INTD# | VIA_INTD# | | Slot6 INTB# | Slot7 INTA#
INTC# PCIB4_INT0 PrPMC_INTA# | VIA_INTA# | ARC_INTA# | Slot6 INTC# | Slot7 INTB#
INTD# PCIB4_INT1 PrPMC_INTB# | VIA_INTB# | ARC_INTB# | Slot6 INTD# | Slot7 INTC#
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NOTEAs the VIA PIPC is located behind a PCI-to-PCI bridge, interrupt acknowledge cycles cannot be used (such cycles are not forwarded across a bridge). Interrupt servicing routines for the VIA must identify interrupting resources (the 8259 core in the VIA) directly.
5.5.5 PCI Interrupt Bridge
Arcadia includes an optional switch to connect/disconnect the PCI domain interrupt pins. Connecting them via the PCI_INT_BRIDGE* switch (see Section 5.11, “Configuration”) allows interrupts to be asserted and handled on either side. Opening the bridge maintains each domain as a separate (independent) entity.
NOTEPer the PCI bridge specification, PCI bridges such as the Tsi310 do not forward interrupt acknowledge cycles. Thus, interrupt handlers attempting to span the bridge will need to poll and/or handle interrupt clearing via software.
5.5.6 PCI Configuration
Each PCI device accessible as a target has an associated bus and device number. PCI device numbers are not globally unique, and must include the bus number. Bus 1 is the main PCI/PCI-X bus (primary), while bus 2 is the secondary, 33-MHz (nominal) PCI bus.
Although the PCI-to-PCI bridge is nominally transparent, allowing data to flow in either direction, PCI configuration cycles are one exception: only the primary PCI bus interface of the bridge converts type1 configuration cycles to type0 configuration cycles. Consequently, the high-speed PCI-X bridge (connected to the HIP/CDS slots) is the PCI bridge primary connection, allowing those cards to configure the
Slot #7 INTA# PCIB4_INT3 PrPMC_INTD# | VIA_INTD# | | Slot6 INTB# | Slot7 INTA#
INTB# PCIB4_INT0 PrPMC_INTA# | VIA_INTA# | ARC_INTA# | Slot6 INTC# | Slot7 INTB#
INTC# PCIB4_INT1 PrPMC_INTB# | VIA_INTB# | ARC_INTB# | Slot6 INTD# | Slot7 INTC#
INTD# PCIB4_INT2 PrPMC_INTC# | VIA_INTC# | | Slot6 INTA# | Slot7 INTD#
ARC INTA# PCIB3_INT0 PrPMC_INTA# | VIA_INTA# | ARC_INTA# | Slot6 INTA# | Slot7 INTB# 1
INTB# PCIB3_INT1 PrPMC_INTB# | VIA_INTB# | ARC_INTB# | Slot6 INTD# | Slot7 INTC#
Notes:1. Note that the SIOINT signal from the VIA is converted to PCI levels and shared with other PCI devices onto PCIB3_INT
bus signal 0 or 1 (software selectable).
2. Note that slots 2, 4, and 5 (the HIP/CDS slots) have paralleling interrupts in order to allow easier peer-interrupt management (i.e., the CDS cards do not need to know what slot it is in to source interrupt assignments).
Table 5-7. Arcadia 3.1 Interrupt Assignments (continued)
DevicePCI INT
PinCDS Interrupt
BusAttached Devices by Connection Notes
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5-14 Freescale Semiconductor
secondary devices if needed. Devices on the secondary interface cannot configure anything on slots 2, 3, 4, and 5.
5.5.7 PrPMC Connector
The Arcadia platform contains connectors for the direct attachment of any of the Freescale PrPMC processor mezzanine cards. These cards are available with a broad spectrum of embedded processors, from the MPC603e-based, to the MPC7448-based.
The PrPMC connectors are compliant with PCI 2.3 standards. Standard 5-V PMC I/O cards such as Ethernet cards, video cards, etc., are, therefore, usable in this slot. The 5-V bus interfacing allows direct installation of existing PrPMC cards.
5.6 System ControlThe Arcadia contains a second FPGA called ARC, which implements the following functions:
• Reset controller• PCI1 bus arbitration
Table 5-8. PCI Configuration Addresses
Component BusSchematic
Device Number
Notes
PrPMC IDSEL #1 B4 16 1
Secondary PCI bridge B3 17 2
ARC B3 18
RTK8139 Ethernet B4 21
VIA 82C686B B4 20
Slot 6 B4 22
Slot 7 B4 23
Primary PCI bridge A 28
Slot 2 A 20
Slot 3 A 21
Slot 4 A 22
Slot 5 A 24
Notes:1. IDSEL for PCI interface provided for PCI test card probing only;
performing PCI configuration cycles to self may or may not be valid.
2. A configuration option; normally IDSEL is disabled on the secondary PCI bridge.
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• VIA SIOINT to PCIB interrupt mapping• PCIA speed detection and control• Optional: PCI boot for PrPMCs
5.7 ClockingArcadia provides clocks to the PCI/PCI-X slots and devices (both buses), the AGP slot, the PrPMC connector, the arbiter/system logic, and the PCI bridge. With multiple PCI domains, each domain may operate at a different frequency than the others, as shown in Figure 5-5.
Figure 5-5. Arcadia PCI Clock Domains
The VIA PIPC is fixed at a 33-MHz frequency, so the ‘standard’ speed of the secondary PCI bus is also 33 MHz and, therefore, is the secondary interface of the PCI bridge. The PCI bridge accepts asynchronous primary and secondary clocks, so the bridge and the PIPC devices are clocked with a simple, fixed 33-MHz clock buffer.
Pw
rH
MZ
D
PMC/PrPMC
IDE/USBSystem
I/O
Ethernet10/100Base
Slot 7 Slot 6 Slot 5 Slot 4 Slot 3 Slot 2
HIPSlot 2 HIPSlot 1
HM
ZD
P
wr
PCI 1
PCI 2
Clock
PCI Boot512–8 MBFlash/CF
ARCSystemControl
ISO+Shift
PCI-X/PCI
Bridge
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The primary PCI clock varies depending on the devices installed in the PCI slots. The M66EN signal is used to select 33 or 66 MHz, while PCIXCAP is used to select between PCI and PCI-X mode, as well as for 66-MHz operation.
Configuration switches select the frequency used for the high-speed PCI clock rate. Since Arcadia lacks intelligent PCI configuration, and is not anticipated to readily support PCI-X at 133 MHz due to the number of PCI slots needed, no automatic high-speed PCI-X clock configuration is supported. Arcadia is only guaranteed to work at 66 MHz PCI/PCI-X rates; all other settings are experimental.
Lastly, the entire clock system can be switched to an external clock source for complete control over the PCICLK signals sent to cards. The overall clock architecture is shown in Figure 5-6.
Table 5-9. PCI Clock Domain Summary
PCI Domain
PCI Group
Device PCI ClockPCI Speed
RangeSpeed Detection Notes
PCI A 1 PCI bridge PCIA_CLK(0) 33–66 PCIA_M66E, PCIA_PCIXCAP, PCIA_SPEED(0:1)
Slot 2/HIP 1 PCIA_CLK(1) 33–66
ARC PCIA_CLK(2) 33–66 2
Slot 3 PCIA_CLK(5) 33–66
Slot 4 PCIA_CLK(3) 33–66
Slot 5/HIP 2 PCIA_CLK(4) 33–66
PCI B 3 PCI bridge PCIB_CLK(0) 33 N/A 1
ARC PCIB_CLK(1)
4 Ethernet PCIB_CLK(2)
VIA PIPC PCIB_CLK(3)
PrPMC PCIB_CLK(4)
Slot 6 PCIB_CLK(5)
Slot 7 PCIB_CLK(6)
Notes:1. PCI B is fixed at 33 MHz.
2. Used to clock the primary arbiter.
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Figure 5-6. Arcadia Clock Architecture
Arcadia uses the MPC9855 clock synthesizer to generate 33/66 MHz primary PCI clock rates; 33 MHz secondary PCI clocks are generated by a buffered version of the clock input.
Note that HIP cards provide their own, locally-generated clocks for the RapidIO bus, and may or may not elect to make any use of the PCI clock signal.
5.8 ResetThe reset architecture of Arcadia is fairly straightforward. PCI cards are reset from the PCIRST signal, generated by the ATX power supply, or chassis/motherboard pushbutton switches. The general reset architecture is shown in Figure 5-7.
MPC9855
33
PCI #4
PCI #5
Bridge
PrPMC
Ethernet
PSIPC
MPC9109
MHz
M66EN
PCIXCAP
33 MHz
Slot 6
Slot 7
ARC FPGA
ARC FPGA
PCI #2
ARC FPGA
Bridge
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Figure 5-7. Arcadia Reset Architecture
In operation, the assertion of any the reset pushbutton switches, the power supply, or a signal from the MPMC card may initiate a system reset and cause the reset controller to drive the global reset signals low.
Note that, as PCI is optional, the HIP cards do not have a reset definition. non-PCI RapidIO cards typically use one of the following resources:
• Local reset controller (based on RapidIO power supply or local switch)• PCIRST (even if PCI not supported, PCIRST signal may be referenced)• RapidIO maintenance packets (software-based reset)
Since PCI is not a required feature of the RapidIO HIP platform, HIP cards should generally not rely on the PCIRST signal being available. To ease the implementation of PCIRST, Arcadia includes strong drivers for the PCIRST signal, to allow HIP cards to place a pullup on the PCIRST signal such that the signal may be used on an HIP card and still operate in the absence of the PCI bus.
5.9 PowerHIP cards are provided with 5 and 3.3 V through the HIP power connectors; additional power may be obtained from the (optional) PCI/PCI-X connector, which also has 5, 3.3, and 12 V as required by the PCI V2.2 specification. Table 5-10 summarizes the available power to HIP cards.
ARC
TSI310
ATX
PSU
Switch
VIA
Port 92H
PrPMC
PCI A
PCI B
Clock
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Note that if a RapidIO HIP card requires +12 or –12 V, it will have to tap into the PCI slot or synthesize its own power using an energy conversion device. As PCI is a non-required feature of the RapidIO HIP platform, the latter is recommended.
All power is provided by the external ATX/ATX-12 V power supply, except for +2.5 V which is locally created.
5.10 Diagnostic FeaturesThe Arcadia motherboard contains few diagnostic and debug features. PCI debug is easily facilitated through the PCI and PMC connectors, and RapidIO debug is handled on the HIP cards using a dedicated logic analyzer tap PCB pattern.
5.10.1 LEDs
Table 5-11 describes the diagnostic LEDs on the Arcadia motherboard.
Table 5-10. Arcadia Slot Power Availability
Power Source Current Power
5 V HIP 2 × 7.8 A 78 W
PCI 5 A 25 W
Total 20.6 A 103 W
3.3 V HIP 2 × 7.8 A 52 W
PCI 7.6 A 25 W
Total 23.2 A 77 W
12 V HIP — —
PCI 0.5 A 6 W
Total 0.5 A 6 W
–12 V HIP — —
PCI 0.1 A 1.2 W
Total 0.1 A 1.2 W
Table 5-11. Arcadia Diagnostic LEDs
LED PCB Label Definition
D13 HOT_3V Standby 3.3 V power working
D16 HOT_5V Standby 5 V power working (from ATX power)
D6 3.3V Power on, 3.3 V working
D1 2.5V 2.5-V regulator for Actel and Tsi310 working
D3 ISO PCIB3 has been isolated from the PCIB4 domain
D14 CLKSTAT Clock is stable
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PCIA speed detect is encoded as shown in Table 5-12.
5.10.2 JTAG
Table 5-13 describes the diagnostic LEDs on the Arcadia motherboard.
D15 PWRGD Power is stable from ATX power supply
D17 IDE IDE disk activity detected
D8 L1_VIA VIA status LED
D9 L2_ISO Bus domains are isolated
D10 L3_ARB Arbitration activity
D11 L4_BOOT Access to PCI Boot space detected
D12 L5_PSPD0 PCIA speed detect or user_defined
D13 L6_PSPD1 PCIA speed detect or user_defined
D14 L7_PCIA PCIA activity detected or user_defined
D15 L8_PCIB PCIB activity detected or user_defined
Table 5-12. Arcadia Diagnostic LEDs: PCI Speed Encoding
PSPD(1:0) Speed
OFF OFF 33-MHz PCI
OFF ON 66-MHz PCI
ON OFF NA
ON ON NA
Table 5-13. Arcadia JTAG Chain
Device TDI Input Name TDO Output Name Notes
FPGA (from header) ARC_TDO
PrPMC ARC_TDO PRPMC_TDO
Tundra PRPMC_TDO TSI310_TDO
Slot 2 TSI310_TDO SLOT2_TDO
Slot 4 SLOT2_TDO SLOT4_TDO
Slot 5 SLOT4_TDO SLOT5_TDO
Slot 6 SLOT5_TDO SLOT6_TDO
Slot 7 SLOT6_TDO SLOT7_TDO Slot 7 TDO test pad near FPGA header
Table 5-11. Arcadia Diagnostic LEDs (continued)
LED PCB Label Definition
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5.11 ConfigurationArcadia contains several slide-switches used to configure the board, processors(s) and chipsets for the options shown in Table 5-14. Underlined entries are the defaults, as shipped. Since the switches operate by connecting a pulled-up signal to ground, setting a switch to ON is indicated as ‘1’ in the table.
All switches are oriented so that ON = 1 = UP, where UP means toward the PCI and I/O connector back panel of the ATX chassis. If the chassis is standing up with the cover off, an alternate interpretation is ON = 1 = LEFT.
Table 5-14. Arcadia Configuration Switches
Switch No. Option DescriptionDefault Setting
Notes
SW1 1 TSI310: BAR_EN Default 1MB BAR enable0/OFF: BAR0 disabled by default1/ON: BAR0 enabled by default
0
2 TSI310: S_INT_ARB_EN Secondary bus internal arbiter enable0/OFF: Use internal arbiter1/ON: Use external arbiter
0
3 TSI310: 64_BIT_DEVICE Physical width of the PCI-X device0/OFF: Bridge is a 64-bit bus1/ON: Bridge is a 32-bit bus
0
4 TSI310: OPAQUE_EN Opaque region enable0/OFF: Opaque memory enable = 01/ON: Opaque memory enable = 1
0
5 TSI310: IDSEL_REROUTE_EN
Secondary PCI IDSEL remap0/OFF: IDSEL remap mask is 0000_00001/ON: IDSEL remap mask is 22F2_0000
0
6 TSI310: S_SEL100 Secondary high-speed rate select0/OFF: PCI-X highest speed is 133 MHz1/ON: PCI-X highest speed is 100 MHz
1
7 TSI310: P_CFG_BUSY Primary configuration busy0/OFF: Primary side responds to configuration
cycles normally.1/ON: Primary side configuration cycles are
retried until bit 2 of the miscellaneous control registers is set to 0 by a secondary configuration cycle write.
0
8 TSI310: P_DRVR_MODE Primary Driver mode control0/OFF:Normal impedance
1/ON:Lower impedance for heavier loads
0
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SW3 1 ISOLATE_3_4 Isolate slow PCI bus segment0/OFF: PCIB3 connected to PCIB41/ON: PCIB3 isolated from PCIB4
1
2 BRIDGE_EN* TSI310 PCI bridge enable0/OFF: PCI bridge responds to config cycles1/ON: PCI bridge ignores all config cycles
1 2
3 PCIA_FRC1 PCI A (Fast) bus speed forceFRC(1:0)0 0 AUTO (33 MHz when M66_EN input is 0 or
66 MHz when M66_EN is a 1. M66_EN pin is three-stated.)
0 1 PCIA forced to 66 MHz PCI mode (M66_EN pin is three-stated)
1 0 PCIA forced to 33 MHz PCI mode (M66_EN pin is driven with logic 0)
1 1 PCIA forced to 33 MHz PCI mode (M66_EN pin is driven with logic 0)
11
4 PCIA_FRC0
5 ENET_DIS* RTK8139 Ethernet enable0/OFF RealTek 8139 may be accessed1/ON: RealTek 8139 cannot be accessed
1
6 PCI_INT_BRIDGE* PCI bus interrupt connection0/OFF: PCIA and PCIB interrupts are directly
connected (wire-OR’d)
1/ON: PCIA and PCIB interrupts are isolated
1
7 PRPMC_IDSELEN* PrPMC IDSEL enabled0/OFF: PrPMC can be target selected1/ON: PrPMC cannot be target selected
1 5
8 MONARCH* 0/OFF: PrPMC is PCIB controller1/ON: PrPMC is not PCIB controller
1 1
Table 5-14. Arcadia Configuration Switches (continued)
Switch No. Option DescriptionDefault Setting
Notes
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5.11.1 Power Supply Force Header
This 2-pin Berg header allows installation of a shorting header. When not installed, as is the default, the chassis power switch is used to turn power ON and OFF. If a header is installed across pins 1 and 2, the ATX power supply will be forced into the ON state at all times. This feature is used with non-ATX power supplies, as well as with systems requiring systems to power-up in the ON state.
5.12 MechanicalThe following sections discuss mechanical issues of the Arcadia board, including board layout, thermal/heatsink issues, and placement. Nothing in this section should be considered a substitute for mechanical drawings.
SW2 1 ARC0 0/OFF: SIOINT -> PCIB3_INT01/ON: SIOINT -> PCIB3_INT1
0
2 ARC1 Reserved 1
3 ARC2 Reserved 1
4 G0 Switch readable on VIA GPI5 1 3
5 G1 Switch readable on VIA GPI6 1 3
6 LPCWP* 0/ON: LPC flash is write-protected1/OFF: LPC flash is write-enabled
1 4
7 rsvd N/A 1
8 rsvd N/A 1
Notes:1. This switch configures the MPMC card into system controller, a mode which is required for normal PCI use. Disabling is
provided for testing purposes only.2. This switch allows software that does not wish to deal with PCI bridges ignore them, at the cost of access to the other PCI
domain.3. Software-defined switches.
4. Optional feature.
5. Some PCI devices do not allow their own IDSEL to be asserted when operating as the PCI host; if so, use this switch to disable IDSEL. Not applicable for PCI agents.
Table 5-15. Arcadia Power Supply Force Header
Pin Definition
1 PSON; open-drain signal pulled up to 5 V
2 Chassis ground
Table 5-14. Arcadia Configuration Switches (continued)
Switch No. Option DescriptionDefault Setting
Notes
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5.13 Motherboard DimensionsArcadia is a standard 12.0 × 9.6 inch (305 × 244 cm (the specification is written in inches)) motherboard, and follows standard ATX 2.01 clearance requirements. Arcadia implements the standard set of mounting holes for chassis attachment, with the addition of ATX 2.01 mounting hole F, located near the communications port adapter as shown in Figure 5-8.
Figure 5-8. Arcadia ATX Chassis Mounting Holes
Hole F is required for ATX 2.01 standards and is needed for mechanical rigidity for Arcadia; most standard chassis punchouts implement the standard support area.
12.0 in.
9.6
in.
4.9 in.3.1 in.
11.1 in.
6.1
in.
8.95
in.
0.9 in.
F
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Freescale Semiconductor 5-25
5.14 PlacementThe general placement of components on the Arcadia motherboard is shown in Figure 5-9.
Figure 5-9. Component Placement
12.0 in.
9.6
in.
4.9 in.3.1 in.
11.1 in.
6.1
in,
8.95
in,
0.9 in.
F
VIA
RTK
PrPMC
TSI310
FPGA
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Chapter 6 CDS IOCard ArchitectureThis chapter describes the IOCard in detail. It elaborates on the physical architecture and device connections, as well as the power management and usage.
6.1 Mechanical PropertiesThe CDS IOCard is essentially a PCB and connector implementing a passive but high-quality, balanced connection between communications devices and the connectors. To maximize the available back-panel I/O space available with a double-width PCI form-factor, CDS uses a small card near the IO escape end of the board. The use of small modules to allow flexibility on the CPM interface is the primary driving factor behind the connector solution. The module must be positioned such that any I/O from a module will be properly aligned with the adjacent PCI slot (recall that HIP cards are twice the PCI card width). The CDS system routes its dedicated I/O to the first slot in the chassis opening. The optical connectors are routed to the adjacent opening.
Figure 6-1 shows a block diagram of a CDS daughtercard, for reference purposes.
Figure 6-1. CDS IOCard Block Diagram
Con
nect
or
RJ45 +MAG
DualUSB
RJ45 +MAG
USBPower
Events
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The approximate placement and component sizes of the CDS IOCard are shown in Figure 6-2.
Figure 6-2. CDS IOCard Physical Dimensions
6.2 IOCard ConnectorThe IOCard uses a high-speed, high-density connector. Table 6-1 lists the pins of the daughtercard connector.
Table 6-1. CDS IOCard Connector Details
Signal Group Signal Pin Count Notes
TSEC3 T3_TXI[P,N][A:D] 8 Differential routing matched-length routing
T3_LED(1:4) 4 —
TSEC4 T4_TXI[P,N][A:D] 8 Differential routing matched-length routing
T4_LED(1:4) 4 —
USB U1_TN, U1_TP 2 Differential routing matched-length routing
U2_TN, U2_TP 2 Differential routing matched-length routing
U1_OC, U2_OC 2 —
Signal EVENT1, EVENT2 2 Reset/IRQ/event signal
Power VCC_3.3 10 —
VCC_5 6 Needed for USB power
GND 46 —
Total Total 94 —
38 [1.5]
107[4.2]
RJ45
RJ45
USB
RIs
er
1 cm2
1 in.2
USB
PWR
Cutout to
PCI slotsallow adjacent
9.5 [0.375]
9.5 [0.375]
CDS IOCard Architecture
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor 6-3
6.3 IOCard Connector PinoutFor a detailed pinout, including numbering, refer to Appendix B.2, “IOCard Connector Pinout.”
6.4 IO PowerIO power is obtained from the carrier, which supplies +2.5- and +3.3-V power. This power is shared with numerous resources, excluding the daughtercard, which derives its power separately.
Spares Spares 6 Bring up to next connector size
Total Total 100 —
Table 6-1. CDS IOCard Connector Details (continued)
Signal Group Signal Pin Count Notes
CDS IOCard Architecture
MPC8555E Configurable Development System Reference Manual, Rev. 1
6-4 Freescale Semiconductor
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor 7-1
Chapter 7 uTCOM ArchitectureThis chapter describes the interface of the uTCOM, as well as its physical properties. The uTCOM is an adaptation of the TCOM expansion board. Essentially, it is the same, just shrunk to fit the CDC. The uTCOM board is a separate adapter, with its own specification document.
7.1 OverviewThe general uTCOM interface architecture is shown in Figure 7-1.
Figure 7-1. CDS uTCOM/TCOM Interface
TCOMConnectors
uTCOM
CPM/CE Signals
-to-60XBus
DIN
128
DIN
128
uTCOM Architecture
MPC8555E Configurable Development System Reference Manual, Rev. 1
7-2 Freescale Semiconductor
7.2 Mechanical Architecture
7.2.1 uTCOM Connector• The uTCOM connector is used to connect the CDS carrier card to one of several special-purpose
test/evaluation boards, most commonly the TCOM board. This card has numerous I/O, debug and communications configurations, and is connected to via two 128-pin DIN connectors. These connectors are too large to be accommodated on the CDS carrier, therefore, CDS uses a 400-pin connector on the back of the board (the same FCI connector is used for the daughtercard connection). This connector mates to a special adapter board, which converts the FCI footprint to the TCOM footprint. The adapter board also contains:
• Interface logic that allows the CDS local bus to communicate with the TCOM• Optional USB 1.1 interface to support certain processors• Additional power supply access points• Mechanical bracing mechanisms for rigidity
7.2.2 uTCOM Connector Signals
Table 7-1 lists the signals of the uTCOM connector.Table 7-1. CDS uTCOM Connector Details
Signal Notes
PA(0:31)
PB(4:31)
PC(0:31)
PD(4:31)
CX(0:60) CE/future expansion
LB_A(0:15) Lower 16 addresses
LB_D(0:15) 16-bit data bus
LB_CS(6:7)
LB_BS/WE(0:3)
LALE
LBCTL
LGP(0:5)
LBCLK
CFGDRV
TCM_RST
IRQ(6:7)
MDIO
uTCOM Architecture
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor 7-3
7.3 uTCOM PinoutFor a detailed pinout, including numbering, refer to Appendix B.3, “uTCOM Connector Pinout.”
The following tables detail the pinout interface between CDS uTCOM board P1 and P2 connector, to TCOM board (Table 7-2 and Table 7-3).
MDC
5V
3.3V
Ground
Total
Spares Bring up to next connector size
Total
Table 7-2. uTCOM Pin Routing to TCOM Board (P1 Connector)
MPC8555E CPM
(Port Name) Male
uTCOM Sweezler
<->Female
TCOM(Port Name)
PA31–PA26 FCC1–FEC A31–PA26
PA21–PA14 FCC1–FEC PA21–PA14
PA21–PA14 FCC1–FEC PA21–PA14
PC21 CLK11 FCC1-FEC RXCLK PC21
PC20 CLK12 FCC1-FEC TXCLK PC20
PB30 FCC2-FEC RxDV FCC3-FEC PB17
PB28 FCC2-FEC RxER FCC3-FEC PB16
PB31 FCC2-FEC TxER FCC3-FEC PB15
PB29 FCC2-FEC TxEN FCC3-FEC PB14
PB27 FCC2-FEC COL FCC3-FEC PB13
PB26 FCC2-FEC CRS FCC3-FEC PB12
PB18 FCC2-FEC RxD3 FCC3-FEC PB11
PB19 FCC2-FEC RxD2 FCC3-FEC PB10
PB20 FCC2-FEC RxD1 FCC3-FEC PB9
PB21 FCC2-FEC RxD0 FCC3-FEC PB8
PB22 FCC2-FEC TxD0 FCC3-FEC PB7
PB23 FCC2-FEC TxD1 FCC3-FEC PB6
Table 7-1. CDS uTCOM Connector Details (continued)
Signal Notes
uTCOM Architecture
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7-4 Freescale Semiconductor
PB24 FCC2-FEC TxD2 FCC3-FEC PB5
PB25 FCC2-FEC TxD3 FCC3-FEC PB4
PC17 CLK15 FCC2-FEC RXCLK PC17
PC16 CLK16 FCC2-FEC TXCLK PC16
PD22 TDMA2 TxD TDMB1 PD13
PD21 TDMA2 RxD TDMB1 PD12
PC9 TDMA2 Tsync TDMB1 PD11
PD20 TDMA2 Rsync TDMB1 PD10
PD30 EN_T1_2 PD5
PC27 CLK5 TDMA2 T1_2_RXCLK PC23
PC26 CLK6 TDMA2 T1_2_TXCLK PC22
PB27 TDMB2 TxD TDMB2 PB31
PB26 TDMB2 RxD TDMB2 PB30
PB25 TDMB2 Tsync TDMB2 PB28
PB24 TDMB2 Rsync TDMB2 PB29
PD31 EN_T1_6 PD9
PC29 CLK3 TDMB2 T1_6_RXCLK PC17
PC28 CLK4 TDMB2 T1_6_TXCLK PC16
PA9 TDMC2 TxD TDMA1 PA9
PA8 TDMC2 RxD TDMA1 PA8
PB28 TDMC2 Tsync TDMA1 PA7
PC1 TDMC2 Rsync TDMA1 PA6
PD29 EN_T1_1 PD4
PC19 CLK13 TDMC2 T1_1_RXCLK PC31
PC18 CLK14 TDMC2 T1_1_TXCLK PC30
— VCC —
— GND —
— VCC VDS3EN1 PD25
— VCC VDS3EN2 PA4
— GND DS3 LB PA5
— GND DS3LB PC13
Table 7-2. uTCOM Pin Routing to TCOM Board (P1 Connector) (continued)
MPC8555E CPM
(Port Name) Male
uTCOM Sweezler
<->Female
TCOM(Port Name)
uTCOM Architecture
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Freescale Semiconductor 7-5
NOTEThe MIIMDIO and MIIMDC signals of the TCOM are connected to both uTCOM expansions, P1 and P2 (for compatibility reasons).
PD23 EN_T1_3 PD6
PD24 EN_T1_4 PD7
PD25 EN_T1_5 PD8
PD14 EN_T1_7 PD18
PD15 EN_T1_8 PD19
All other — NC — All other
PC9 — MIIMDIO — PC9
PC10 — MIIMDC — PC10
Table 7-3. uTCOM Pin Routing to TCOM Board (P2 Connector)
MPC8555E CPM
(Port Name) Male
uTCOM Sweezler
<->Female
TCOM (Port Name)
— MIIMDIO MIIMDIO Connector P1 PC9
— MIIMDC MIIMDC Connector P1 PC10
All other — Pin-to-pin — All other
Table 7-2. uTCOM Pin Routing to TCOM Board (P1 Connector) (continued)
MPC8555E CPM
(Port Name) Male
uTCOM Sweezler
<->Female
TCOM(Port Name)
uTCOM Architecture
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7-6 Freescale Semiconductor
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor A-1
Appendix A Revision HistoryThis appendix provides a list of the major differences between the MPC8555E Configurable Development System Reference Manual, Revision 0 through the MPC8555E Configurable Development System Reference Manual, Revision 1.
A.1 Changes From Revision 0 to Revision 1Major changes to the MPC8555E Configurable Development System Reference Manual, from Revision 0 to Revision 1 are as follows:Section, Page ChangesBook Change 33-66 MHz to 33/66 MHz.About This Book, xiv In the “Organization” section, change the nineth and tenth bullets to read
• Appendix C, “CDS Carrier BOM, Rev. 1.2”• Appendix D, “CDS Carrier Schematics, Rev. 1.2” After the tenth bullet, insert two new bullets and renumber the remaining appendices as follows: • Appendix E, “CDS Carrier BOM, Rev. 1.3”• Appendix F, “CDS Carrier Schematics, Rev. 1.3”
1.1, 1-1 Replace the first sentence with the following:The configurable development system (CDS) was developed to support a wide range of Power Architecture™ processors, such as the MPC8555E and the MPC8541E.
1.2, 1-1 Replace the first paragraph with the following:This reference manual describes the Freescale CDS development platform. It provides details on the MPC8555E CDS hardware configuration and functionality. It is intended primarily as a guide for hardware and software designers.
1.3, 1-1 Replace the entire section with the following:The CDS system is the middle ground between evaluation and test boards. It is more configurable and flexible than an evaluation board, but it is not as configurable as a test board, in which every component can be tested and examined. Where it lacks configurability, its design has options for the most common settings.Two MPC8555E CDS development system configurations are described. The configurations consist of different board revisions which are referenced
Revision History
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A-2 Freescale Semiconductor
throughout this manual as Configuration 1 or Configuration 2. The configurations are:• Configuration 1
— Arcadia, Rev. 3.1— Carrier card, Rev. 1.2— CPU card, Rev. 1.1— I/O card, Rev. 1.1
• Configuration 2— Arcadia, Rev. 3.1— Carrier card, Rev. 1.3— CPU card, Rev. 1.1
Refer to Appendix F, “CDS Carrier Schematics, Rev. 1.3,” Table F-1, for hardware differences between carrier card, Rev. 1.2 and Rev. 1.3.
1.3.1, 1.2 Last bullet, second dash, replace with the following:— Supports two Ethernet ports on the carrier card at MII/GMII, and two
Ethernet ports on the I/O adapter at MII/GMII, 10/100 or 1G rates (Configuration 1).
NOTEIn Configuration 1, Ethernet port #4 on the I/O card is not functional.
— Supports all four Ethernet ports on the carrier card. MII/GMII on ports #1 and #2. Ethernet ports #3 and #4, 10/100 or 1G rates (Configuration 2).
1.3.1, 1-2 Last dash on page, replace with the following:— PCI/PCI-X 32/64 bits, 33/66 MHz
1.3.1, 1-3 Last two bullets, replace with the following:— Includes I/O adapter board (Configuration_1)
1.3.2, 1-3 Replace the first paragraph with the following:Figure 1-1 is a diagram of the CDS system for Configuration 1.
1.3.2, 1-3 Change Figure 1-1 caption to the following:Figure 1-1. Carrier Block Diagram (Configuration 1)
1.3.2, 1-3 After Figure 1-1, add the following paragraph and figure:Figure 1-2 is a diagram of the CDS system for Configuration 2.
Revision History
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Freescale Semiconductor A-3
Figure 1-2. Carrier Block Diagram (Configuration 2)
1.3.2, 1-4 Renumber Figure 1-2 to Figure 1-3.Chapter 2, 2-1 Replace the first paragraph with the following:
This chapter provides a step-by-step guide for bringing up a CDS.2.1, 2-1 Replace the first paragraph, four bullets, and note with the following:
The hardware configurations consist of different board revisions which are referenced throughout this manual as Configuration 1 or Configuration 2. Refer to Appendix F, “CDS Carrier Schematics, Rev. 1.3,” Table F-1, for hardware differences between carrier card, Rev. 1.2 and Rev. 1.3. The configurations are:• Configuration 1
— Arcadia, Rev. 3.1— Carrier card, Rev. 1.2— CPU card, Rev. 1.1— I/O card, Rev. 1.1
• Configuration 2— Arcadia, Rev. 3.1— Carrier card, Rev. 1.3— CPU card, Rev. 1.1
CPUDaughtercard
PCI-X+2.5-VPower
LocalClock
H/SClock
FlashGBit#2
GBit#1
QuadPHY
NVRAM
DEBUG
MUX uTCOM
OC3ATMPHY
OC12ATMPHY
AdTech
BU
F
GBit#3
GBit#4
UART
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A-4 Freescale Semiconductor
2.2,2-1 Replace the first sentence in the note to read:The carrier card and processor card are packaged together.
2.2, 2-1 Delete Step 1 and renumber the rest.2.3, 2-5 Item No. 5, replace the U-boot screen dump with the following:
U-Boot 1.1.3 (FSL Development) (Oct 27 2006 - 10:43:18)
CPU: 8555, Version: 1.1, (0x80790011)Core: E500, Version: 2.0, (0x80200020)
Clock Configuration:
CPU: 833 MHz, CCB: 333 MHz, DDR: 166 MHz, LBC: 83 MHz
L1: D-cache 32 kB enabled
I-cache 32 kB enabled
Board: CDS Version 0x13
CPU Board Revision 0.0 (0x0000) PCI1: 32 bit, 33 MHz, sync
PCI2: 32 bit, 66 MHz, async
I2C: readyDRAM: Initializing
SDRAM: 64 MB
DDR: 256 MBFLASH: 16 MB
L2 cache 256KB: enabled
In: serialOut: serial
Err: serial
Net: TSEC0: PHY is Marvell 88E1145 (1410cd4)TSEC1: PHY is Marvell 88E1145 (1410cd4)
TSEC0, TSEC1
The IP address of the board is currently set to 169.254.113.58The MAC address is 00:04:9F:00:28:C8
If they don't match your network environment, please change them in U-Boot and kernel manually.
Hit any key to stop autoboot: 0
=>
2.5, 2-9 Change the title of Table 2-2 to read: “Default Status of Carrier Board Switches (Configuration 1).”
2.5, 2-9 In Table 2-2, replace the rows for SW 1, Bits 2 and 3 with the following:
1 2 Synchronizer 1 1 Must be 1 at all times (PHY CLK/FPGA CLK)
3 Reserved 1 See Note 1
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Freescale Semiconductor A-5
2.5, 2-9 In Table 2-2, replace the rows for SW 2, Bits 5 and 6 with the following:
2.5, 2-10 In Table 2-2, replace the row for SW 3, Bit 2 with the following:
2.5, 2-10 In Table 2-2, replace the row for SW 3, Bits 6 with the following:
2.5, 2-10 In Table 2-2, add the following notes to the end of the table:Notes:1. SW1(3) for Configuration 2 is PCI CLK SEL and must be set to 1.2. SW2(6) for Configuration 2 is PCI Select PCI = 1 and PCIX = 0.
2.5, 2-11 Change the title of Table 2-3 to read: “Default Status of Arcadia Board Switches (Arcadia C3.n).”
2.5, 2-11 In Table 2-3, replace the rows for SW 2, Bits 4–8 and SW 3, Bits 1 and 2 with the following:
2 5 Reserved 1 1 Reserved
6 Reserved 1 1 Reserved, see Note 2
3 2 DUART output select 1 0 DUART channel #2 to 2x5 (AT) headerDUART channel #1 to DB9 connector
1 DUART channel #2 to DB9 connectorDUART channel #1 to 2x5 (AT) header
3 6 FE select 0 0 FCC3->Cicada MII#4 enabled1 FCC3->Cicada MII#4 disabled
2 4 1 G0 1 User defined
5 1 G1 1 User defined
6 2 LPCWP* 1 User defined
7 Reserved 1 N/A
8 Reserved 1 N/A
3 1 Isolate slow PCI bus segmentISOLATE_3_4
0 0 PCIB3 connected to PCIB41 PCIB3 isolated from PCIB4
2 TSI310 PCI bridge enableBRIDGE_EN*
0 0 PCI bridge responds to config cycles1 PCI bridge ignores all config cycles
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A-6 Freescale Semiconductor
2.5, 2-11 In Table 2-3, replace the rows for SW 3, Bits 6, 7, and 8; and replace the notes with the following:
3.1.1, 3-1 Delete the first 2 paragraphs, 2 bullets, and Figure 3-1.3.1.2, 3-2 Replace the first paragraph with the following:
Figure 3-1 is a diagram of the CDS board for Configuration 1.3.1.2, 3-2 Change Figure 3-2 caption to the following:
Figure 3-1. Carrier Block Diagram (Configuration 1)
3 5 RTK8139 Ethernet enableENET_DIS*
1 0 RealTek 8139 may be accessed1 RealTek 8139 cannot be accessed
6 PCI bus interrupt connectionPCI_INT_BRIDGE*
0 0 PCIA and PCIB interrupts are directly connected (wire-or’d)
1 PCIA and PCIB interrupts are isolated
7 3 PrPMC IDSEL enabledPRPMC_IDSELEN*
1 0 PrPMC can be target selected1 PrPMC cannot be target selected
8 4 MONARCH* 1 0 PrPMC is PCIB controller1 PrPMC is not PCIB controller
Notes:1. Software-defined switches.
2. Optional feature.
3. Some PCI devices do not allow their own IDSEL to be asserted when operating as the PCI host; if so, use this switch to disable IDSEL. Not applicable for PCI agents.
4. This switch configures the MPMC card into the system controller, a mode which is required for normal PCI use. Disabling is provided for testing purposes only.
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Freescale Semiconductor A-7
3.1.2, 3-2 After Figure 3-2, add the following paragraph and figure:Figure 3-2 is a diagram of the CDS system for Configuration 2.
Figure 3-2. Carrier Block Diagram (Configuration 2)
3.3.2, 3-4 In Table 3-2, replace offset rows 0x03 and 0x04 with the following:
3.3.2.3, 3-5 In Table 3-5, replace row for bit 1 with the following:
3.3.2.4, 3-6 Delete Section 3.3.2.4, Figure 3-6, and Table 3-6.3.3.2.5, 3-6 Delete Section 3.3.2.5, Figure 3-7, and Table 3-7. Renumber the remaining
sections, figures, and tables.3.5, 3-12 In Figure 3-12, replace the label HFBR-5805 with HFBR-5208M. Replace the
label HFBR-58208M with HFBR-5805.3.5, 3-12 In Table 3-15, replace feature row for optical transceiver with the following:
0x03 Reserved — —
0x04 Reserved — —
1 PHYRST This bit allows software to issue a reset to the Ethernet PHY.
Optical transceiver Agilent HFBR-5208M Agilent HFBR-5805
CPUDaughtercard
PCI-X+2.5-VPower
LocalClock
H/SClock
FlashGBit#2
GBit#1
QuadPHY
NVRAM
DEBUG
MUX uTCOM
OC3ATMPHY
OC12ATMPHY
AdTech
BU
F
GBit#3
GBit#4
UART
Revision History
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A-8 Freescale Semiconductor
3.6, 3-12 Replace the first paragraph and note with the following:In Configuration 1, the CDS carrier card provides four 10/100 1GB-baseT Ethernet ports. Two are located on the basic carrier board and the other two on the IOCard expansion. The four ports are controlled by a Cicada CS8204 quad-PHY, which in turn receives data from three dedicated MII/GMII daughtercard connections. In Configuration 2, all four Ethernet ports on the carrier card are supported by a Marvell 88E1145. MII/GMII on Ethernet ports #1 and #2. RGMII on Ethernet ports #3 and #4, 10/100 or 1G rates.
NOTEIn Configuration 1, TBI, RTBI, RMII, and RGMII interface modes are not supported.In Configuration 1, Ethernet port #4 on the I/O card is not functional.In Configuration 2, RGMII is supported only on Ethernet ports #3 and #4.
3.6, 3-13 Add the following sentence to the paragraph before Table 3-16:The Ethernet PHY addresses are fixed in Configuration 2.
3.6, 3-13 Change Table 3-16 caption to the following:Table 3-16. Phy Address Options (Configuration 1)
3.6, 3-13 After Table 3-16, replace the paragraph with the following:These connections and the interface logic are shown in Figure 3-11 for Configuration 1 and Figure 3-12. for Configuration 2.
3.6, 3-14 Change Figure 3-13 caption to the following:Figure 3-11. CDS Ethernet Architecture (Configuration 1)
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Freescale Semiconductor A-9
3.6, 3-14 After Figure 3-13, add the following figure:
Figure 3-12. CDS Ethernet Architecture (Configuration 2)
3.6, 3-14 In Table 3-17 change the fifth column heading to read: ‘CS8204 PHY or Marvell 88E1145’. Remove the references to note 3 in the table and note 3 at the end of the table.
3.7, 3-16 Table 3-18, replace the Chip selects rows with the following:
3.8, 3-18 Change the first paragraph to the following:The CDS carrier board contains four independent clock domains:
3.8, 3-18 After the first paragraph delete the fourth item.3.8, 3-19 Table 3-21, change the PCICK row with the following:
Chip selects LB_CS0 8 Connects to Flash device #1 (carrier card)
LB_CS1 Connects to Flash device #2 (carrier card)
LB_CS2 Connects to SRAM/SDRAM port (CPU card)
LB_CS3 Connects to RTC/NVRAM
LB_CS4 Connects to uTCOM port
LB_CS5 Reserved
LB_CS6 Reserved
LB_CS7 Reserved
PCICLK 33/66 MHz 3.3V LVTTL PCI interface of daughtercard
125 MHz
RJ45 +MAG
RJ45 +MAG
RJ45 +MAG
RJ45 +MAG⊗
Dau
ghte
rcar
d
RGMII 10/100
MI
GMII TSEC2
GMI/RGMII
RGMII
TSEC1
Marvell88E1145
0
1
2
3
Port
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A-10 Freescale Semiconductor
3.8, 3-19 Table 3-21, remove the HS_CLK row and note 1 at the end of the table.3.8, 3-19 Replace Figure 3-15 with the following:
3.8, 3-21 In the last paragraph, delete the first sentence.3.8.1, 3-21 Delete Section 3.8.1.3.13, 3-27 Table 3-27, replace the seventh through eleventh rows with the following:
3.13, 3-28 Table 3-27, replace the fourth from the bottom row with the following:
3.13, 3-28 Table 3-27, add the following notes to the end of the table:Notes:1. SW1(3) for Configuration 2 is PCI CLK SEL and must be set to 1.2. SW2(6) for Configuration 2 is PCI Select PCI = 1 and PCIX = 0.
3.14.1, 3-30 Delete Section 3.14.1 and Table 3-29. Renumber remaining sections and tables.
Uart_Sel Switch or I2C 6 SW3(2) 1 = Uart_Sel
Reserved Switch or I2C 7 SW3(1) 1 = Reserved
User-defined USERMODE(0:1) Switch or I2C 0x25 1–0 SW2(8:7) 00 = User defined
Reserved Switch or I2C 2 SW2(6) 1 = Reserved 1
Reserved Switch or I2C 3 SW2(5) 1 = Reserved
Reserved Switch or I2C 5 SW1(3) 1 = Reserved 2
CDC
125 MHzOSC
PCICLK
PCICLK
ICS
525-
02
16 MHzOSC
GTX_CLK
RTC_CLK
I2C/Switch
PCISLOT
SYSCLK
LocalBus
LBCLK
MUX
Revision History
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Freescale Semiconductor A-11
5.5.4, 5-12 In Table 5-7, for Slots #2, #3, #4, and #5, the Slot 5 information has changed in the ‘Attached Devices by Connection’ column. Replace these rows with the following:
5.5.6, 5-15 In Table 5-9, replace the last nine rows with the following:
5.7, 5-18 In the first paragraph after Table 5-9, replace the second sentence with the following:The M66EN signal is used to select 33 or 66 MHz, while PCIXCAP is used to select between PCI and PCI-X mode, as well as for 66-MHz operation.
Appendix C, C-1 Replace title and paragraph as follows:
Slot #2 INTA# PCIA1_INT0 Slot2 INTA# | Slot3 INTD# | Slot4 INTC# | Slot 5 INTA# 2
INTB# PCIA1_INT1 Slot2 INTB# | Slot3 INTA# | Slot4 INTD# | Slot 5 INTB#
INTC# PCIA1_INT2 Slot2 INTC# | Slot3 INTB# | Slot4 INTA# | Slot 5 INTC#
INTD# PCIA1_INT3 Slot2 INTD# | Slot3 INTC# | Slot4 INTB# | Slot 5 INTD#
Slot #3 INTA# PCIA1_INT1 Slot2 INTB# | Slot3 INTA# | Slot4 INTD# | Slot 5 INTB# 2
INTB# PCIA1_INT2 Slot2 INTC# | Slot3 INTB# | Slot4 INTA# | Slot 5 INTC#
INTC# PCIA1_INT3 Slot2 INTD# | Slot3 INTC# | Slot4 INTB# | Slot 5 INTD#
INTD# PCIA1_INT0 Slot2 INTA# | Slot3 INTD# | Slot4 INTC# | Slot 5 INTA#
Slot #4 INTA# PCIA1_INT2 Slot2 INTC# | Slot3 INTB# | Slot4 INTA# | Slot 5 INTC# 2
INTB# PCIA1_INT3 Slot2 INTD# | Slot3 INTC# | Slot4 INTB# | Slot 5 INTD#
INTC# PCIA1_INT0 Slot2 INTA# | Slot3 INTD# | Slot4 INTC# | Slot 5 INTA#
INTD# PCIA1_INT1 Slot2 INTB# | Slot3 INTA# | Slot4 INTD# | Slot 5 INTB#
Slot #5 INTA# PCIA1_INT3 Slot2 INTD# | Slot3 INTC# | Slot4 INTB# | Slot 5 INTD# 2
INTB# PCIA1_INT0 Slot2 INTA# | Slot3 INTD# | Slot4 INTC# | Slot 5 INTA#
INTC# PCIA1_INT1 Slot2 INTB# | Slot3 INTA# | Slot4 INTD# | Slot 5 INTB#
INTD# PCIA1_INT2 Slot2 INTC# | Slot3 INTB# | Slot4 INTA# | Slot 5 INTC#
RTK8139 Ethernet B4 21
VIA 82C686B B4 20
Slot 6 B4 22
Slot 7 B4 23
Primary PCI bridge A 28
Slot 2 A 20
Slot 3 A 21
Slot 4 A 22
Slot 5 A 24
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A-12 Freescale Semiconductor
Appendix CCDS Carrier BOM, Rev. 1.2This appendix provides CDS Carrier BOM for Rev. 1.2.
Appendix D, D-1 Replace title and paragraph as follows:Appendix DCDS Carrier Schematics, Rev. 1.2This appendix provides CDS Carrier board schematics for Rev. 1.2.
Appendix E, E-1 Add new appendices E and F (renumber remaining appendices):Appendix ECDS Carrier BOM, Rev. 1.3This appendix provides CDS Carrier BOM for Rev. 1.3. Appendix FCDS Carrier Schematics, Rev. 1.3This appendix provides CDS Carrier board schematics for Rev. 1.3.
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor B-1
Appendix BPinouts
B.1 Carrier/DaughterCard Connectors Pinout
Table B-1. Daughtercard Connector (Left) Definition and PinoutPin A B C D E F G H J K
1 GND U1_SI GND PA0 PA1 GND PA2 PA3 VCC_2.5
2 U1_TP VCC_2.5 U1_SO U2_SI GND PA4 PA5 GND PA6 PA7
3 U1_TN U1_OC GND U2_SO PA8 GND PA9 PA10 VCC_2.5 PA11
4 VCC_2.5 U2_OC U1_RTS GND PA12 PA13 GND PA14 PA15 GND
5 U2_TP GND U1_CTS U2_RTS GND PA16 PA17 VCC_2.5 PA18 PA19
6 U2_TN VCC_2.5 U2_CTS PA20 GND PA21 PA22 GND PA23
7 GND TS1_0 TS1_1 GND PA24 PA25 GND PA26 PA27 VCC_2.5
8 TS1_2 VCC_2.5 TS1_3 TS1_4 GND PA28 PA29 GND PA30 PA31
9 TS1_5 TS1_6 GND TS1_7 PB4 GND PB5 PB6 VCC_2.5 PB7
10 VCC_2.5 TS1_8 TS1_9 GND PB8 PB9 GND PB10 PB11 GND
11 TS1_10 GND TS1_11 TS1_12 GND PB12 PB13 VCC_2.5 PB14 PB15
12 TS1_13 TS1_14 VCC_2.5 TS1_15 PB16 GND PB17 PB18 GND PB19
13 GND TS1_16 TS1_17 GND TS1_18 PB20 GND PB21 PB22 VCC_2.5
14 TS1_19 VCC_2.5 TS1_20 TS1_21 GND PB23 PB24 GND PB25 PB26
15 TS1_22 TS1_23 GND TS1_24 PB27 GND PB28 PB29 VCC_2.5 PB30
16 VCC_2.5 TS2_0 TS2_1 GND TS2_2 GND PB31 GND
17 TS2_3 GND TS2_4 TS2_5 GND VCC_2.5 SLEEP
18 TS2_6 TS2_7 VCC_2.5 TS2_8 TS2_9 GND MDIO GND PCICLK2
19 GND TS2_10 TS2_11 GND TS2_12 GND MDC UDE VCC_3.3
20 TS2_13 VCC_2.5 TS2_14 TS2_15 GND GTXCLK GND PCICLK2
21 TS2_16 TS2_17 GND TS2_18 TS2_19 GND VCC_3.3 AD57
22 VCC_2.5 TS2_20 TS2_21 GND TS2_22 GND AD43 AD50 GND
23 TS2_23 GND TS2_24 TS3_0 GND VCC_3.3 AD51 AD58
24 TS3_1 TS3_2 GND TS3_3 TS3_4 GND AD44 GND AD59
25 GND TS3_5 TS3_6 GND TS3_7 PERR GND AD45 AD52 VCC_3.3
26 TS3_8 VCC_2.5 TS3_9 TS3_10 GND AD32 PAR64 GND AD53 AD60
27 TS3_11 TS3_12 GND TS3_13 TS3_14 GND AD36 AD46 VCC_3.3 AD61
28 VCC_2.5 TS3_15 TS3_16 GND TS3_17 AD33 GND AD47 AD54 GND
29 TS3_18 GND TS3_19 TS3_20 GND AD34 AD37 VCC_3.3 AD55 AD62
30 TS3_21 TS3_22 VCC_3.3 TS3_23 TS3_24 GND AD38 AD48 GND AD63
Pinouts
MPC8555E Configurable Development System Reference Manual, Rev. 1
B-2 Freescale Semiconductor
NOTES:1) Was PCICLK on V1.0 carriers.
2) Was SYSCLK on V1.0 carriers.
31 GND AD31 GND PAR AD35 GND AD49 AD56 VCC_3.3
32 GNT# VCC_3.3 AD30 C_BE0 GND C_BE3 AD39 GND AD11 AD5
33 REQ# GNT64# GND C_BE1 C_BE2 GND AD40 C_BE6 VCC_3.3 AD4
34 VCC_3.3 REQ64# AD29 GND AD20 IDSEL GND C_BE4 AD10 GND
35 M66EN GND AD28 AD24 GND DEVSEL AD41 VCC_3.3 AD9 AD3
36 PCIXCAP SERR# VCC_3.3 AD23 AD19 GND AD42 AD15 GND AD2
37 GND STOP# AD27 GND AD18 TRDY GND AD14 AD8 VCC_3.3
38 +12V VCC_3.3 AD26 AD22 GND IRDY C_BE7 GND AD7 AD1
39 +12V LOCK# GND AD21 AD17 GND C_BE5 AD13 VCC_3.3 AD0
40 VCC_3.3 SYSCLK1 AD25 GND AD16 FRAME GND AD12 AD6 GND
Table B-2. Daughtercard Connector (Right) Definition and PinoutPin A B C D E F G H J K
1 GND PC0 PC1 GND PC2 PC3 GND CX0 CX1 VCC_2.5
2 PC4 VCC_2.5 PC5 PC6 GND PC7 PC8 GND CX3 CX4
3 PC9 PC10 GND PC11 PC12 GND PC13 CX5 VCC_2.5 CX6
4 VCC_2.5 PC14 PC15 GND PC16 PC17 GND CX7 CX8 GND
5 PC18 GND PC19 PC20 GND PC20 PC21 VCC_2.5 CX9 CX10
6 PC22 PC23 VCC_2.5 PC24 PC25 GND PC26 CX11 GND CX12
7 GND PC27 PC28 GND PC29 PC30 GND CX13 CX14 VCC_2.5
8 PC31 VCC_2.5 GND PD4 GND CX15 CX16
9 PD5 PD6 GND PD7 PD8 GND PD9 CX17 VCC_2.5 CX18
10 VCC_2.5 PD10 PD11 GND PD12 PD13 GND CX19 CX20 GND
11 PD14 GND PD15 PD16 GND PD17 PD18 VCC_2.5 CX21 CX22
12 PD19 PD20 VCC_2.5 PD21 PD22 GND PD23 CX23 GND CX24
13 GND PD24 PD25 GND PD26 PD27 GND CX25 CX26 VCC_2.5
14 PD28 VCC_2.5 PD29 PD30 GND PD31 CX35 GND CX27 CX28
15 CX29 CX30 GND CX31 CX32 GND CX33 CX34 VCC_2.5 CX35
16 VCC_2.5 CX36 CX37 GND CX38 CX39 GND CX40 CX41 GND
17 CX42 GND CX43 CX44 GND CX45 CX46 VCC_2.5 CX47 CX48
18 CX49 CX50 VCC_2.5 CX51 CX52 GND CX53 CX54 GND CX55
19 GND CX56 CX57 GND CX58 GND CX59 VCC_2.5
20 VCC_3.3 LBCTL GND LB_OE LALE3 GND LCLK1
21 OVM GND LB_GP0 LB_CS7 GND LALE2 LALE0 VCC_3.3 LCLK0
22 VCC_3.3 GND LB_CS6 LB_A0 GND LB_W3 LB_W2 GND
23 SRESET GND LB_GP1 GND LB_A1 LALE1 VCC_3.3 LB_W1 LB_W0
24 HRESET VCC_3.3 LB_GP2 LB_CS5 GND LB_A8 LB_A14 GND LB_A26
25 GND HR_REQ DMACK1 GND LB_CS4 LB_A2 GND LB_A15 LB_A20 VCC_3.3
Table B-1. Daughtercard Connector (Left) Definition and Pinout (continued)Pin A B C D E F G H J K
Pinouts
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor B-3
.
26 PCIRST# VCC_3.3 DMACK0 LB_GP3 GND LB_A3 LB_A9 GND LB_A21 LB_A27
27 CFGRST DMADN1 GND LB_GP4 LB_CS3 GND LB_A10 LB_A16 VCC_3.3 LB_A28
28 VCC_3.3 DMADN0 DMARQ1 GND LB_CS2 LB_A4 GND LB_A17 LB_A22 GND
29 MCP GND DMARQ0 LB_GP5 GND LB_A5 LB_A11 VCC_3.3 LB_A23 LB_A29
30 INT13 INT14 VCC_3.3 LB_CS1 GND LB_A12 LB_A18 GND LB_A30
31 GND INT11 INT15 GND LB_CS0 LB_A6 GND LB_A19 LB_A24 VCC_3.3
32 INT10 VCC_3.3 INT12 LB_DP0 GND LB_A7 LB_A13 GND LB_A25 LB_A31
33 INT7 INT8 GND LB_DP1 LB_D0 GND LB_D11 LB_D16 VCC_3.3 LB_D27
34 VCC_3.3 INT5 INT9 GND LB_D1 LB_D6 GND LB_D17 LB_D22 GND
35 INT4 GND INT6 LB_DP2 GND LB_D7 LB_D12 VCC_3.3 LB_D23 LB_D28
36 INT0 INT1 VCC_3.3 LB_DP3 LB_D2 GND LB_D13 LB_D18 GND LB_D29
37 GND INT2 INT3 GND LB_D3 LB_D8 GND LB_D19 LB_D24 VCC_3.3
38 RTC VCC_3.3 PCIRED LB_SIZ0 GND LB_D9 LB_D14 GND LB_D25 LB_D30
39 PWRGD CFGDRV GND LB_SIZ1 LB_D4 GND LB_D15 LB_D20 VCC_3.3 LB_D31
40 VCC_3.3 SDA SCK GND LB_D5 LB_D10 GND LB_D21 LB_D26 GND
Table B-3. Daughtercard High-Speed Connector Definition and PinoutA B C
1 HS_A2p GND HS_A1p
2 HS_B2n GND HS_B1n
3 GND GND GND
4 HS_C2p GND HS_C1p
5 HS_D2n GND HS_D1n
6 GND GND GND
7 HS_A4p GND HS_A3p
8 HS_B4n GND HS_B3n
9 GND GND GND
10 HS_C4p GND HS_C3p
11 HS_D4n GND HS_D3n
12 GND GND GND
13 HS_A6p GND HS_A5p
14 HS_B6n GND HS_B5n
15 GND GND GND
16 HS_C6p GND HS_C5p
17 HS_D6n GND HS_D5n
18 GND GND GND
19 HS_A8p GND HS_A7p
20 HS_B8n GND HS_B7n
21 GND GND GND
22 HS_C8p GND HS_C7p
Table B-2. Daughtercard Connector (Right) Definition and Pinout (continued)Pin A B C D E F G H J K
Pinouts
MPC8555E Configurable Development System Reference Manual, Rev. 1
B-4 Freescale Semiconductor
23 HS_D8n GND HS_D7n
24 GND GND GND
25 HS_A10p GND HS_A9p
26 HS_B10n GND HS_B9n
27 GND GND GND
28 HS_C10p GND HS_C9p
29 HS_D10n GND HS_D9n
30 GND GND GND
31 HS_E2p GND HS_E1p
32 HS_F2n GND HS_F1n
33 GND GND GND
34 HS_G2p GND HS_G1p
35 HS_H2n GND HS_H1n
36 GND GND GND
37 HS_E4p GND HS_E3p
38 HS_F4n GND HS_F3n
39 GND GND GND
40 HS_G4p GND HS_G3p
41 HS_H4n GND HS_H3n
42 GND GND GND
43 HS_E6p GND HS_E5p
44 HS_F6n GND HS_F5n
45 GND GND GND
46 HS_G6p GND HS_G5p
47 HS_H6n GND HS_H5n
48 GND GND GND
49 HS_E8p GND HS_E7p
50 HS_F8n GND HS_F7n
51 GND GND GND
52 HS_G8p GND HS_G7p
53 HS_H8n GND HS_H7n
54 GND GND GND
55 HS_E10p GND HS_E9p
56 HS_F10n GND HS_F9n
57 GND GND GND
58 HS_G10p GND HS_G9p
59 HS_H10n GND HS_H9n
60 GND GND GND
61 GND
62 GND
Table B-3. Daughtercard High-Speed Connector Definition and Pinout (continued)A B C
Pinouts
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor B-5
B.2 IOCard Connector Pinout
63 GND GND GND
64 HS_X2p GND HS_X1p
65 HS_X2n GND HS_X1n
66 GND GND GND
67 HS_X4p GND HS_X3p
68 HS_X4n GND HS_X3n
69 GND GND GND
70 GND
71 GND
72 GND GND GND
73 GND
74 GND
75 GND GND GND
76 GND
77 GND
78 GND GND GND
79 GND
80 GND
81 GND GND GND
82 GND
83 GND
84 GND GND GND
85 GND
86 GND
87 GND GND GND
88 HSCLKp GND
89 HSCLKn GND
90 GND GND GND
Table B-4. IOCard Connector Definition and Pinout
Pin A B C D E
1 T3_TXIP_A GND T3_TXIP_B VCC_3.3 T3_LED1A
2 T3_TXIN_A GND T3_TXIN_B VCC_3.3 T3_LED1C
3 GND GND GND VCC_3.3 T3_LED2A
4 T3_TXIP_C GND T3_TXIP_D VCC_3.3 T3_LED2C
5 T3_TXIN_C GND T3_TXIN_D VCC_3.3 T3_LED3A
6 GND GND GND VCC_3.3 T3_LED3C
Table B-3. Daughtercard High-Speed Connector Definition and Pinout (continued)A B C
Pinouts
MPC8555E Configurable Development System Reference Manual, Rev. 1
B-6 Freescale Semiconductor
B.3 uTCOM Connector Pinout
7 GND EVENT1 VCC_3.3 T3_LED4A
8 GND EVENT2 VCC_3.3 T3_LED4C
9 GND GND GND VCC_3.3 GND
10 T4_TXIP_A GND T4_TXIP_B VCC_3.3 T4_LED1A
11 T4_TXIN_A GND T4_TXIN_B VCC_5 T4_LED1C
12 GND GND GND VCC_5 T4_LED2A
13 T4_TXIN_C GND T4_TXIP_D VCC_5 T4_LED2C
14 T4_TXIN_C GND T4_TXIN_D VCC_5 T4_LED3A
15 GND GND GND VCC_5 T4_LED3C
16 GND VCC_5 T4_LED4A
17 GND GND T4_LED4C
18 GND GND GND GND GND
19 U1_TN GND U2_TN GND U1_OC
20 U1_TP GND U2_TP GND U2_OC
Table B-5. uTCOM Connector (Right) Definition and PinoutPin A B C D E F G H J K
1 PA0 PA16 GND PB16 PC0 VCC_5 PD16 GND CX16
2 PA1 GND PB17 VCC_3.3 PC16 GND CX17
3 GND PA17 VCC_3.3 PC1 PC17 GND PD17 VCC_5
4 PA2 PA18 VCC_3.3 PB18 PC2 GND PD18 VCC_5 CX18
5 PA3 VCC_3.3 PB19 GND PC18 VCC_5 CX19
6 VCC_3.3 PA19 GND PC3 PC19 VCC_5 PD19 GND
7 PA4 PA20 GND PB20 PC4 VCC_5 PD4 PD20 GND CX20
8 PA5 GND PB4 PB21 VCC_3.3 PC20 PD5 GND CX4 CX21
9 GND PA21 PB5 VCC_3.3 PC5 PC21 GND PD21 CX5 VCC_5
10 PA6 PA22 VCC_3.3 PB22 PC6 GND PD6 PD22 VCC_5 CX22
11 PA7 VCC_3.3 PB6 PB23 GND PC22 PD7 VCC_5 CX6 CX23
12 VCC_3.3 PA23 PB7 GND PC7 PC23 VCC_5 PD23 CX7 GND
13 PA8 PA24 GND PB24 PC8 VCC_5 PD8 PD24 GND CX24
14 PA9 GND PB8 PB25 VCC_3.3 PC24 PD9 GND CX8 CX25
15 GND PA25 PB9 VCC_3.3 PC9 PC25 GND PD25 CX9 VCC_5
16 PA10 PA26 VCC_3.3 PB26 PC10 GND PD10 PD26 VCC_5 CX26
17 PA11 VCC_3.3 PB10 PB27 GND PC26 PD11 VCC_5 CX10 CX27
18 VCC_3.3 PA27 PB11 GND PC11 PC27 VCC_5 PD27 CX11 GND
19 PA12 PA28 GND PB28 PC12 VCC_5 PD12 PD28 GND CX28
20 PA13 GND PB12 PB29 VCC_3.3 PC28 PD13 GND CX12 CX29
Table B-4. IOCard Connector Definition and Pinout (continued)
Pin A B C D E
Pinouts
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor B-7
21 GND PA29 PB13 VCC_3.3 PC13 PC29 GND PD29 CX13 VCC_5
22 PA14 PA30 VCC_3.3 PB30 PC14 GND PD14 PD30 VCC_5 CX30
23 PA15 VCC_3.3 PB14 PB31 GND PC30 PD15 VCC_5 CX14 CX31
24 VCC_3.3 PA31 PB15 GND PC15 PC31 VCC_5 PD31 CX15 GND
25 SDA GND VCC_5 GND
26 SCK GND VCC_3.3 GND
27 GND VCC_3.3 GND VCC_5
28 MDIO VCC_3.3 GND VCC_5 LB_A8
29 MDC VCC_3.3 GND LB_D0 VCC_5 LB_A0 LB_A9
30 VCC_3.3 GND VCC_5 LB_D8 LB_A1 GND
31 LB_GP0 GND VCC_5 LB_D1 LB_D9 GND LB_A10
32 LB_GP1 GND INT6 VCC_3.3 LB_D2 GND LB_A2 LB_A11
33 GND INT7 VCC_3.3 GND LB_D10 LB_A3 VCC_5
34 LB_GP2 VCC_3.3 LB_W3 GND LB_D3 LB_D11 VCC_5 LB_A12
35 LB_GP3 VCC_3.3 LB_W2 GND LB_D4 VCC_5 LB_A4 LB_A13
36 VCC_3.3 LB_CS7 GND VCC_5 LB_D12 LB_A5 GND
37 LB_GP4 LB_CS6 GND LB_W1 VCC_5 LB_D5 LB_D13 GND LB_A14
38 LB_GP5 GND LB_W0 VCC_3.3 LB_D6 GND LB_A6 LB_A15
39 GND PWRGD CFGDRV VCC_3.3 GND LB_D14 LB_A7 VCC_5
40 TCMRST CFGRST VCC_3.3 LBCTL LALE0 GND LB_D7 LB_D15 VCC_5 LCLK0
Table B-5. uTCOM Connector (Right) Definition and Pinout (continued)Pin A B C D E F G H J K
Pinouts
MPC8555E Configurable Development System Reference Manual, Rev. 1
B-8 Freescale Semiconductor
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor C-1
Appendix CCDS Carrier BOM, Rev. 1.2This appendix provides CDS Carrier BOM for Rev. 1.2.
Board Station BOM fileDate : NOV 1 2005
Variant : CDS_Carrier rev 1.2 BOM CDS Carrier rev 1.2a updated 12_MAY_05Line item 68, J12, is now a NO POP component BOM CDS Carrier rev 1.2B updated 1_SEP_05
BOM CDS Carrier rev 1.2C updated 1_NOV_05
ITEM_NOCOMPANY PART NO. GEOMETRY COUNT DESCRIPTION REFERENCE
1 pcb_carrier 12 1-1605458-1 conn_rj45_mag_led 2 conn.rj45_cat5_mag_led.ra, TransPower J6 J83 103167-2 header_ra_2x5 1 header.ra.2x5, AMP J14 103309-1 header_2x5_shrouded 1 header.2x5, AMP J25 105-1089-00 3 Latch_Housing_Tektronix6 1210YG106ZAT2A cc1210 9 cap, 10uF, AVX C117 C162 C165
C255 C257 C282C298 C300 C302
7 1469001-1 conn_hmzd40pr_recpt_ra 1 conn.amp.HMZd.40pr.recpt.ra, Tyco P78 218-8LPST sw_som16 4 sw.8spst.cts, CTS SW1 SW2 SW3 SW49 223961-1 conamp_223961-1 2 conn.pwr.3pos.ra, AMP P5 P6
10 223986-1 guide_mod 2 guide_module.keyed.ra, AMP GM1 GM211 293D105X9016A2T cct3216 2 cap_tant, 1uF, SPRAGUE C2 C9612 293D106X9016C2T cct6032 2 cap_tant, 10uF, SPRAGUE C60 C6913 293D226X9016C2T cct6032 5 cap_tant, 22uF, SPRAGUE C1 C15 C83 C196
C28514 293D476X9016D2T cct7343 1 cap_tant, 47uF, SPRAGUE C13215 597-5112-40X led_0603 12 led, Dialight, Red D1 D2 D3 D4 D5 D6
D7 D8 D11 D12 D13D14
16 597-5312-40X led_0603 2 led, Dialight, Green D9 D1017 74390-001 connFCI_recp_10x40_sm 3 conn.megarray.10x40.1of5, FCI J3 J10 J1118 767054-1 conn_mictor38 3 conn.mictor.38, Amp J14 J16 J1719 AM29LV641DH120REI tsop48w 2 am29lv641d.tsop48w, AMD U49 U54
20 APA150-FG256 fbga256 1 apa150.1of2.fbga256, ACTEL U2421 AT24C64AN-10SI-2.7 so8 1 at24c64a.s08, ATMEL U122 CY7B9950AC tqfp32 1 cy7b9950ac.tqfp32, CYPRESS U5023 DEM9PL conn_db9_plg_ra 1 conn.db9.plug.rta, ITT Cannon J1524 DS1553WP-120 pcm34 1 ds1553wp_120.pcm34, DallasSemi U5125 DS1834S so8 2 ds1834s.so8, DALLAS SEMI. U34 U3726 DS9034PCX 1 POWERCAP27 E13W1F2C-77.760M osc_smd_e13j1 1 osc.3_3v.diff.smd, 77.760MHz, ECLIPTEK U2228 EEFUE0G221R cc_7.3x4.3_ue 19 cap_tant, 220uF, PANASONIC C18 C62 C86 C87
C91 C127 C135 C136C146 C192 C193C208 C212 C278C289 C291 C292C297 C306
29 EH2645TS-125.000M osc_smd_5x7mm 1 osc.3_3v.smd, 125.00MHz, ECLIPTEK Y130 EH2645TS-16.000M osc_smd_5x7mm 1 osc.3_3v.smd, 16.000MHz, ECLIPTEK U4431 EH2645TS-19.440M osc_smd_5x7mm 1 osc.3_3v.smd, 19.440MHz, ECLIPTEK U2732 ETQP6F1R1BFA inductor_12.5x12.5 2 inductor, 1.1uH, Panasonic L1 L233 FTR-125-01-S-D header_2x25_05sp_smt 1 header_2x25_05sp, Samtec J1334 FTSH-113-01-L-DV-K conn_2x13_050_sma 1 conn.2x13, Samtec J935 G3B15AH-x-XA sw_sm_spdt_ra 1 sw.1spdt, NKK SW536 HFBR-5208M 1x9mezz 1 hfbr_5xxx.1x9mezz, AGILENT U1237 HFBR-5805 1x9mezz 1 hfbr_5xxx.1x9mezz, AGILENT U1338 HI1206N101R-00 ferrite_1206 7 ferrite_bead_1206, Steward FB1 FB2 FB3 FB4
FB5 FB6 FB739 ICS525R-02I ssop28_pit635mm 1 ics525_02.ssop28, ICS U4240 IDTQS3VH16233PA tssop56 6 idtqs3vh16233pa.tssop56, IDT U7 U8 U17 U18 U20
U2141 IDTQS3VH257PA tssop16 2 idtqs3vh257.tssop16, IDT U19 U4142 IRF6604 irf6604 1 irf66xx.dirfet, IRF Q243 IRF6607 irf6607 1 irf66xx.dirfet, IRF Q144 LMK107F105ZA cc0603 9 cap, 1.0uF, TAIYO_YUDEN C34 C35 C55 C90
C128 C129 C134C304 C305
45 LT1331CG ssop28 2 lt1331cg.ssop28, Linear U16 U4746 LT1587CM-1.5 ddpak3 1 lt1587-1.5v.ddpak3, Linear Technology U3147 LTC4300-1CMS8 ms8 1 ltc4300_1.ms8, Linear Tech U2
48 MAX4372FEUK-T sot23_5p 1 max4372f.sot23_5, Maxim U1449 MBRS140T3 smb_403a 1 mbrs140t3.smb, MOT CR150 MCCA101K0NRT cc0402 1 cap, 100pF, SMEC C5451 MCCA104K0NRT cc0402 240 cap, 0.1uF, SMEC C3 C5 C7 C8 C11
C13 C16 C19 C20C22 C24 C25 C27C29 C32 C36 C37C39 C41 C42 C43C45 C46 C47 C48C50 C51 C53 C57C58 C66 C67 C68C70 C71 C72 C76C77 C78 C79 C82C84 C85 C88 C89C92 C93 C94 C95C97 C100 C102 C105C107 C108 C110C111 C112 C113C114 C115 C116C118 C119 C120C121 C122 C123C124 C125 C130C131 C137 C141C142 C143 C144C145 C147 C148C149 C150 C151C152 C153 C154C155 C156 C157C159 C160 C161C163 C164 C166C167 C168 C169C170 C171 C172C173 C174 C175C176 C177 C178C179 C180 C181C182 C183 C184C185 C186 C187
C188 C189 C190C191 C194 C195C197 C199 C200C201 C202 C203C204 C205 C206C207 C209 C210C213 C214 C215C216 C217 C218C219 C220 C221C222 C223 C224C225 C226 C227C228 C229 C230C231 C232 C233C236 C237 C238C239 C240 C241C242 C243 C244C245 C246 C248C249 C250 C251C252 C253 C256C258 C259 C260C261 C262 C263C264 C265 C266C267 C268 C269C270 C271 C272C273 C274 C275C276 C277 C279C280 C281 C283C284 C287 C288C294 C295 C296C299 C301 C303C309 C311 C312C313 C314 C315C316 C317 C318C319 C320 C321C322 C323 C324C325 C326 C327C328 C329 C330
C331 C333 C334C335 C336 C337C338 C339 C340C341 C342 C343C345
52 MCCA470K0NRT cc0402 3 cap, 47pF, SMEC C211 C235 C30753 MCCE102KONRT cc0402 34 cap, 1000pF, SMEC C4 C6 C9 C10 C12
C14 C17 C21 C23C26 C28 C30 C31C33 C38 C40 C44C49 C56 C59 C63C64 C65 C73 C74C75 C80 C81 C98C99 C101 C103 C104C106
54 MCCE103KONRT cc0402 1 cap, 0.01uF, SMEC C28655 MCR10-EZHM-J-5R0 rc0805 1 res, 5, Rohm R17656 MMSZ6V2T1 sod_123 1 MMSZ6V2T1.sod123, Motorola CR257 MPC9259FA lqfp32 1 mpc9259fa.lqfp32, MOTOROLA U2958 MPC962308DT-1H tssop16 2 mpc962308, Freescale U9 U1159 NOT_A_COMPONENT tp_pth 31 test.pth, None TP14 TP15 TP16
TP17 TP18 TP19TP20 TP21 TP22TP23 TP24 TP25TP26 TP29 TP30TP31 TP32 TP33TP34 TP35 TP36TP37 TP38 TP39TP40 TP41 TP42TP43 TP44 TP45TP46
60 Not_a_component jump_2x1_1mil 1 splice.1, PCB SP161 P6880 conn_banjo 3 conn.banjo, Tektronix P1 P3 P462 PCA9557PW tssop16 4 pca9557pw.tssop16, PHILIPS U48 U52 U53 U5563 PM5357-B1 sbga304_1.27mm 1 pm5357.main.1of3.sbga304, PMC-SIERRA U2364 PM5384NI stpbga196_1mm 1 pm5384.main.1of2.stpbga196, PMC-SIERRA U2565 QSE-020-01-L-D-A qse_2x20_gnd 2 conn.qse.2x20, SAMTEC J4 J5
67 RC5051M sol20 1 rc5051m.so20, Raytheon U1568 RC73L2Z000JT rc0402 29 res, 0, SMEC R56 R63 R67 R68
R69 R70 R74 R77R85 R104 R105 R111R112 R114 R126R127 R133 R134R139 R147 R154R158 R161 R162R169 R205 R207R208 R204
69 RC73L2Z100JT rc0402 5 res, 10, SMEC R150 R177 R201R202 R203
70 RC73L2Z101JT rc0402 17 res, 100, SMEC R36 R37 R41 R49R61 R121 R132 R137R140 R144 R170R171 R175 R178R179 R180 R182
71 RC73L2Z102JT rc0402 3 res, 1K, SMEC R45 R46 R11772 RC73L2Z103JT rc0402 9 res, 10K, SMEC R75 R119 R122 R123
R124 R125 R128R129 R130
73 RC73L2Z104JT rc0402 3 res, 100K, SMEC R135 R153 R16374 RC73L2Z181JT rc0402 4 res, 180, SMEC R53 R54 R59 R6075 RC73L2Z202JT rc0402 1 res, 2K, SMEC R6576 RC73L2Z221JT rc0402 10 res, 220, SMEC R28 R29 R30 R31
R32 R33 R34 R35R78 R80
77 RC73L2Z330JT rc0402 11 res, 33, SMEC R146 R148 R164R165 R166 R167R173 R174 R186R197 R198
78 RC73L2Z331JT rc0402 2 res, 330, SMEC R79 R8179 RC73L2Z470JT rc0402 1 res, 47, SMEC R9180 RC73L2Z472JT rc0402 40 res, 4.7K, SMEC R47 R48 R51 R52
R57 R58 R82 R83R84 R92 R93 R94
R95 R96 R103 R115R118 R136 R141R142 R143 R151R152 R155 R156R157 R168 R183R184 R185 R189R190 R191 R192R193 R194 R195R196 R199 R200
81 RK73H1ETTP1500F rc0402 3 res, 150, KOA R100 R101 R10282 RK73H1ETTP1580F rc0402 4 res, 158, KOA R106 R107 R108
R10983 RK73H1ETTP15R0F rc0402 3 res, 15, KOA R145 R159 R16084 RK73H1ETTP2001F rc0402 1 res, 2.00K, KOA R13185 RK73H1ETTP2R70F rc0402 2 res, 2.7, KOA R116 R13886 RK73H1ETTP3010F rc0402 5 res, 301, KOA R97 R98 R110 R113
R12087 RK73H1ETTP47R5F rc0402 35 res, 47.5, KOA R1 R2 R3 R4 R5 R6
R7 R8 R9 R10 R11R12 R13 R14 R15R16 R17 R18 R19R20 R21 R22 R23R24 R25 R26 R27R38 R39 R40 R42R43 R50 R55 R62
88 RK73H1ETTP49R9F rc0402 4 res, 49.9, KOA R86 R87 R88 R8989 RK73H1ETTP4R70F rc0402 2 res, 4.7, KOA R99 R14990 RNA4A8E102JT rna4a 4 rnet8.bussed.rna4a, 1K, AVX RN1 RN5 RN6 RN791 RNA4A8E472JT rna4a 4 rnet8.bussed.rna4a, 4.7K, AVX RN2 RN3 RN4 RN892 SN74CBTLV1G125DBVR sop5 2 74cbtlv1g125dbv.so5, TI U56 U5793 SN74LVC16244ADGG tssop48 2 74lvc16244adgg.tssop48, TI U40 U4694 SN74LVC1G125DCKR sc70 13 74lvc1g125.sc70, TI U3 U4 U26 U28 U30
U32 U33 U35 U36U38 U39 U43 U45
95 SN74LVTH273PW tssop20 2 74lvth273, TI U5 U1096 T510X337M010AS cct_casee 14 cap_tant, 330uF, Kemet C52 C61 C126 C133
C138 C139 C140
C198 C254 C290C308 C332 C344C346
97 T510X477M006AS cct_casee 1 cap_tant, 470uF, Kemet C31098 TPSE227K010R0100 cct_casee 3 cap_tant, 220uF, AVX C234 C247 C29399 VSC8204VX pbga388_35x35 1 cis8204.ports.1of3.pbga388, CICADA U6100 WSL2512R010F rc2512 1 res, 0.010, DALE R44101 YFS-20-03-H-05-SB-K header_array_5x20 1 header.5x20.1of3, Samtec J7102 pcix_econ_64b_3.3v econ_pcix64b_3.3v_Signal8_ 1 pcix_edgeconn_64bit, MOT P8103 screw 2 screw
NO POP ComponentsQTH-090-02-F-D-A qth_2x90_gnd 0 conn.qsh.2x90.1of3, SAMTEC J12 RC73L2Z000JT rc0402 0 res, 0, SMEC R205,R206RC73L2Z330JT rc0402 0 res, 33, SMEC R198
CDS Carrier BOM, Rev. 1.2
MPC8555E Configurable Development System Reference Manual, Rev. 1
C-10 Freescale Semiconductor
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor D-1
Appendix DCDS Carrier Schematics, Rev. 1.2This appendix provides CDS carrier board schematics for Rev. 1.2.
87653
7700 W. Parmer LnAustin, Texas 78729
Carrier
C
A
B
CDS_CarrierCover Story
11/8/2005
10:25:20 am
D
1
1 2 3
freescaleFreescale Semiconductor
semiconductor
TM
4 5 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
_4
C
2
Gary Milliorn 011.2
Revision:Page:Title:
accuracy of the information contained herein. Contact
Project:
_
03Nov03V1.0
7700 W. Parmer Ln
this product.
All fuses are self-resetting polyswitch (PTC) devices.
Integrated circuits have default connections to powerand ground unless explicitly shown otherwise. Global powerconnections are:
09
23
1
All inductances are in microhenries (uH).
29
4.
null1
freescaleFreescale Semiconductor
semiconductor
TM
V1.1 04Apr08 Errata fix; see errata.
12
CPM Routing: ATM2 and FE25uTCOM Header, part I
22
0403
2 3 4 5 6 7
A
V1.2 04Oct04 Errata fix; see errata.
uTCOM Header, part II
Serial Port
36
AdTech Adapter Connector
of IBM. Other trademarks are the respective property of their
Engineer:
REV
The sheet-to-sheet cross reference format is:
Configuration05
apply (i.e. PCI). Little-endian numbering is noted at thesource component.
Board impedance is 55 +/- 5 ohms.
19Quad Enet PHY Power/System Interface
D
Date Changed:
8
trademarks of Freescale Semiconductor. PowerPC is a trademark
All ferrites are Z=50 ohms at 100 MHz.
20Ethernet Ports #1 and #221
CPM Routing: ATM124
Cover Page
Time Changed:
FCC1/ATM1: PHY Power
Initial version
FCC2/ATM2: PHY Power31
--reserved--34
1.
2.
VCC_3.3VCC_5
3.
Local High-Speed Clock10
All buses follow big-endian bit numbering order (bit 0 is
Placement and PCB Stackup
02
Page ContentsSchematic Notes
respective copyright holders. For Kristi, with love.
Components with the label "No_Stuff" are not to be installed bydefault; they are for test or manufacturing purposes only.
C123
33pF
null
5432
FCC2/ATM2: (155Mbps) Interface
1
Carrier
C
Freescale Sale/FAEs to obtain the latest information on
B
D
C
System Logic (part I)System Logic (part II)
This schematic is provided for reference purposes only.All information is subject to change without notice.No warranty, expressed or applied, is made as to the
06
CHANGES
VCC_1.2
Sheet VertZoneLetter HorizZoneNumber
DaughterCard High-Speed Connector16
Part numbers used are for reference only; compatibleparts may be used; refer to the bill of materials.
Freescale and the Freescale logo are registered
LocalBus NVRAM/Debug33
Bypass Capacitors35
IOCard Connector
27
All rights reserved. No warranty is made, express or implied.
No_Stuff
GNDVCORE
DaughterCard Connector (Left, Part II)13DaughterCard Connector (Right, Part I)14DaughterCard Connector (Right, Part II)
Unless otherwise specified:
All resistors are SMD0402, in ohms, 0.08W, +/-5%All capacitors are SMD0402, in microfarads (uF), +/-20%.
26
30
LocalBus Flash
5.
6.
7.
CDS_CarrierInformation, please
11/8/2005
10:25:33 am
8
FCC1/ATM1 (622Mbps) Interface28
32
Austin, Texas 78729
11DaughterCard Connector (Left, Part I)Misc: LEDs, Debug Port, I2C
the most-significant bit), except where industry standards
VCC_2.5
Block Diagram
01General Information
07Local Power Supply08Local (non-PCI) Resources: Clock, Reset
76
15
PCI Bus #1 Edge Connector18HMZD Connector + Banjo Headers17
Quad Ethernet PHY MAC Interface
A
B
DATE
Gary Milliorn 021.2
Supplies08
Connector
Mezzanine
freescaleFreescale Semiconductor
semiconductor
TM
Local Bus
_
Revision:Engineer:7700 W. Parmer Ln
Austin, Texas 78729
HmZd
5432
PHY
High-Speed
19-20
10/100/1000baseTConnectors
21
CPM Select
24-25
uTCOM
26-27
Connector
B
D
ATM PHYs
29-32
Date Changed:
Time Changed:
22
IOCard
Page:Title:Project:
11, 34
C
A
876
Connector
B
D
C
34
Debug
17
Interface
Configuration
05
Logic
System
06-07
Logic
Clocks
CDS_CarrierBlock Diagram
11/8/2005
10:25:43 am
Power
09-10
12-14
Connectors
LocalBus
I2C Devices
11
Test Access
33-34
Flash + NVRAM
PCI/PCI-X
18
Connector
Quad Ethernet
15-16
1
1 2 3 4 5 6 7 8
A
Gary Milliorn 031.2
8
0.5oz
PLANE: VCC_2.5
QS
QS
QS
LAYER 1
SWITCH
SWITCH
MISC POWER
CPLD
P6880
freescaleFreescale Semiconductor
semiconductor
TM
Mictor
0.5oz
0.5oz
PLANE: VCC_3.3
SIGNAL: 9
D
Date Changed:
Time Changed:Engineer:
Revision:
PLANE: VCC_3.3
Title:Project:
_
HMZDPOWER
7700 W. Parmer Ln
1
1 2 3 4
765
D
C
0.5oz
SIGNAL: 1
LEDs
6 7
LAYER 2
LAYER 3
LAYER 4
LAYER 10
LAYER 11
.062
335mm [13.25]
SIGNAL: 7
SIGNAL: 8
PLANE: GND
PLANE
BURIED CAPACITANCE LAYER
LAYER 18
LAYER 17
SIGNAL
SIGNAL
0.5oz
LAYER 14
LAYER 15
LAYER 5
LAYER 6
LAYER 7
QS
QS
AdTech
SWITCH
SWITCH
PLANE
PLANE
SIGNAL
SIGNAL
KEY
QPHY
QS
CLK
COMP 0.5oz
Mictor
Mictor
SIGNAL
SIGNALPLANE
SIGNAL
SIGNAL
SOLDER
SIGNAL
0.5oz
32
SIGNAL: 5
SIGNAL: 6
Opto
PHY 1 PHY 2
5
0.5oz
0.5oz0.5oz
0.5oz
ATM
FCI
SIGNAL: 10
PLANE: GND
SIGNAL: 2
8
A
B
Page:
PLANE: GND
FLASH
NVRAM
FLASHPromJet
Austin, Texas 78729
C
A
B
FCI
0.5oz
LAYER 13
LAYER 16
Placement (approximate) and PCB Stackup11/8/2005
10:25:53 am
ATM
LAYER 8
LAYER 9
LAYER 12
SIGNAL
PLANEBURIED CAPACITANCE LAYER
KEY
RJ45
RJ45
P6880
4
0.5oz
0.5oz
0.5oz
0.5oz
0.5oz
0.5oz
UART
130mm
[5.2]
FCI
Samtec
Opto
PLANE: GND
SIGNAL: 3
SIGNAL: 4
PLANE: VCC_2.5
Gary Milliorn1.2
04Carrier
4321
1 2 3 4 5 6
Time Changed:Engineer:
7
freescaleFreescale Semiconductor
semiconductor
TM
8
Date Changed:
Revision:Page:
A
B
D
REMOTE CONTROL 3+4
Gary Milliorn 051.2
CDS_CarrierCarrier Configuration
11/8/2005
10:26:07 am7700 W. Parmer Ln Title:
Project:
ADDR=0x1A+0x1B
Austin, Texas 78729
C
A
B
D
C
REMOTE CONTROL 1+2
ADDR=0x18+0x19
8765
11C1
11C1
25D1
7C1
4
2
7B8
6B10
23B1
1
24C1
25C1
0
1
10D1
1
2
10D1
3
2
3
4
6
5
7C1,9B1
6C1
22
23
1OE1
48OE2
25OE3
OE424
10A1
1
16
17
30
29
27
26
19
20
11
12
36
35
33
32
13
14
5
6
41
40
38
37
8
9
74lvc16244adgg.tssop48
Y1
Y2
Y3
Y4
47
46
44
43
2
3
23
OE11
OE248
OE325
24OE4
tssop48
A4
A3
A2
A1
U46
17
30
29
27
26
19
20
22
12
36
35
33
32
13
14
16
6
41
40
38
37
8
9
11A2
A3
A4
tssop48
47
46
44
43
2
3
5
1 2 3 4
9
Y4
Y3
Y2
Y1
74lvc16244adgg.tssop48U40
A1
9
RN7
1K
5
10
6 7 8
10
2 3 4 5 6 7 8
TP40
RN6
1K
1
8C
98_ON
10D1
7C1,31C8
7D80
1
TP39
33C
14
3_ON
44C
13
4_ON
55C
12
5_ON
66C
11
6_ON
77C
10
7_ON
8
5 6
9
sw.8spst.cts
SW2
11C
16
1_ON
22C
15
2_ON
4
10
3 2 1 7 8
3 4 5 6 7 8
9
4.7K
RN8
7 8
9
1K
RN5
1
10
2
4.7K
4
10
3 2 1 5 6
8 4 3 2 1
9
RN2
7_ON
88C
98_ON
1K
RN1
5
10
6 7
15
2_ON
33C
14
3_ON
44C
13
4_ON
55C
12
5_ON
66C
11
6_ON
77C
10
6 7 8
9
sw.8spst.cts
SW4
11C
16
1_ON
22C
1
10
2 3 4 5
4C
44_ON
13
5C
55_ON
12
6C
66_ON
11
7C
77_ON
10
8C
88_ON
9
4.7K
RN3
7B8,11A8,26C1
SW3
sw.8spst.cts
1C
11_ON
16
2C
22_ON
15
3C
33_ON
14
11IO4
IO512
13IO6
IO714
RESET15
SCL1
2SDA
VDD16
7B8,11A8,26C1
3A0
4A1
5A2
8GND
6IO0
IO17
9IO2
IO310
IO613
14IO7
15RESET
1SCL
SDA2
16VDD
pca9557pw.tssop16
U55
4
A25
GND8
IO06
7IO1
IO29
10IO3
IO411
12IO5
1SCL
SDA2
16VDD
7A1,10A1,14C1,26D1
VCC_3.3
U52
pca9557pw.tssop16
A03
A1
7IO1
IO29
10IO3
IO411
12IO5
IO613
14IO7
15RESET
VCC_3.3
U53
pca9557pw.tssop16
A03
A14
A25
GND8
IO06
10
11IO4
IO512
13IO6
IO714
RESET15
SCL1
2SDA
VDD16
U48
3A0
4A1
5A2
8GND
6IO0
IO17
9IO2
IO3
2 1 8 7 6 5
9
pca9557pw.tssop16
7_ON
10
8C
88_ON
9
RN4
4.7K
4
10
3
22_ON
15
3C
33_ON
14
4C
44_ON
13
5C
55_ON
12
6C
66_ON
11
7C
7
SW1
sw.8spst.cts
1C
11_ON
16
2C
FE_SELFENET DEMUX SELECT
ATM2 DEMUX SELECT ATM2_SELATM1_SELATM1 DEMUX SELECT
UART_SELUART SELECT
REMOTE UDE CFG_UDE*
CFG_RST*REMOTE HRESET
NC
NC
29B1
TP31
ROMMODE FLASHSEL(0:1)
EVENT SELECT EVE_SEL
NC
NVRAM DISABLE NVRAM_DIS*
ATM1 ADTECH SELECT ADT_SEL
ATM1_16BIT*ATM1 WIDTH
USERMODE(0:1)USERMODE
ATM2 ENABLE ATM2_EN*
SYNCHRO*SYNCHONIZED CLOCKS
SW_21
SW_22
SW_23
SW_27
LCLK_V(6:1)CLOCK V
PCI ENABLE PCIEN*
CLOCK S LCLK_S(2:0)
CLOCK R LCLK_R(4:1)
SW_9
SW_10
SW_11
SW_12
SW_13
SW_14
SW_15
SW_1
SW_2
SW_3
SW_4
SW_5
SW_6
SW_7
SCL
CFGRST*
SDA
SW_24
SW_25
SW_26
SW_28
SW_31
SW_16
SW_17
SW_18
SW_19
SW_20
65
1
1 2 3 4 7 8
A
B
D
Date Changed:
Time Changed:Engineer:freescaleTM
Revision:Page:Gary Milliorn
1.206
CDS_CarrierSystem Control Logic (part I)
11/8/2005
10:29:52 am
Freescale Semiconductor
semiconductor
4 5
7700 W. Parmer Ln Title:Project:
Austin, Texas 78729
C
A
B
87632
D
C
ACTEL PROGRAMMING HEADER
Locate within 3" of device.
C2710.1uF
TP19
TP21
10
0.1uFC275
7
R122
10K
TP22
C1780.1uF
TP25
TP26
TP24
7A1,14A8,26C1,34C1
C2380.1uF
13D1
TP17
10K
R123
C2290.1uF
No_Stuff
0
37B1,28B1,29D8,31D8,33B1,34B1
14
0.1uF
1
27pFC158
VDD_9
R15VPN
VPPP14
4
14B1
0
C273
VDD_14L9
VDD_15L10
VDD_16J11
VDD_2F8
F9VDD_3
VDD_4F10
G6VDD_5
VDD_6G11
VDD_7H6
VDD_8H11
J6
VDDP_4F5
VDDP_5
VDDP_6F12
VDDP_7G5
G12VDDP_8
K5VDDP_9
F7VDD_1
VDD_10K6
K11VDD_11
L7VDD_12
VDD_13L8
TRST
VDDP_1E6
VDDP_10K12
L5VDDP_11
VDDP_12L12
M6VDDP_13
M7VDDP_14
M10VDDP_15
M11VDDP_16
E7VDDP_2
VDDP_3E10
E11
IO_F15F15
F16IO_F16
IO_F2F2
F3IO_F3
IO_F4F4
N14RCK
P13TCK
TDIR14
TDOR16
TMST15
P15
IO_E15
IO_E16E16
IO_E2E2
E3IO_E3
IO_E4E4
E5IO_E5
IO_E8E8
E9IO_E9
F1IO_F1
F13IO_F13
IO_F14F14
D3
D4IO_D4
IO_D5D5
D6IO_D6
IO_D7D7
D8IO_D8
IO_D9D9
E1IO_E1
IO_E12E12
E13IO_E13
IO_E14E14
E15
C9IO_C9
IO_D1D1
D10IO_D10
IO_D11D11
D12IO_D12
IO_D13D13
D14IO_D14
D15IO_D15
IO_D16D16
D2IO_D2
IO_D3
IO_C13
IO_C14C14
C15IO_C15
IO_C16C16
IO_C2C2
C3IO_C3
IO_C4C4
C5IO_C5
IO_C6C6
C7IO_C7
IO_C8C8
B3
B4IO_B4
IO_B5B5
B6IO_B6
IO_B7B7
B8IO_B8
IO_B9B9
C1IO_C1
IO_C10C10
C11IO_C11
IO_C12C12
C13
IO_A9A9
IO_B1B1
B10IO_B10
IO_B11B11
B12IO_B12
IO_B13B13
B14IO_B14
IO_B15B15
B16IO_B16
B2IO_B2
IO_B3
IO_A12
IO_A13A13
A14IO_A14
IO_A15A15
IO_A2A2
A3IO_A3
IO_A4A4
A5IO_A5
A6IO_A6
IO_A7A7
A8IO_A8
VCC_3.3$V
apa150.1of2.fbga256
U24
AGND_1H4
H15AGND_2
AVDD_1J3
J15AVDD_2
A10IO_A10
IO_A11A11
A12
VCC_2.5
5B8
C2090.1uF
2
6
$V0R154
6
33B1
0.1uFC157 C230
0.1uF 0.1uFC272
0.1uFC210
VCC_3.3
$V0R162
C252 C2530.1uF
TP23
16
15
0.1uF
VCC_3.3
12
27
26
25
8
33B1
11
24
23
22
18
17
21
20
19
0.1uFC239C237
0.1uFC199
9D1,11D1
26
3 4
5 6
7 8
9
VCC_2.5
0.1uF
17 18
19
2
20
21 22
23 24
25$V
conn.2x13J9
1
10
11 12
13 14
15 16
5
13
VCC_2.5
C2740.1uF
7A1,14C8,15D8,27D1
0.1uFC214
1
10B8
0.1uFC179
C2130.1uF
20A1
5B8
22C1
10A1
10A1
10A1
C1560.1uF
21
22
12B8
20A1,21D1
4
3
2
7A1,14D1,18A8,20A1,26D1,28C1,29C8,31C8,34B87
9
17
18
19
20
SRESET*
UDE*
LB_GPL(0:5)
EVE_SEL
EVENT1*
HSCLK_CLK
HSCLK_DATA
HSCLK_LD*
FLASH0_CS*
IRQ*(11:0)
LB_A(0:31)
NC
NC
NC
NC
NC
CLA(23:0)
COP_HRST*
ENET_RST*
EPHY_ADR(4:2)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
FLASH1_CS*
NC
NC
NC
NC
NC
NC
NC
POR_RST*
FLASHSEL(0:1)
CTLCLK
4 5 6 7 8
Date Changed:
Time Changed:
B
D
Engineer:
A
Revision:Page:Title:
Project:
D
B
7700 W. Parmer LnAustin, Texas 78729
C
A
freescaleFreescale Semiconductor
semiconductor
TM
C
8
Gary Milliorn 071.2
CDC_CarrierSystem Logic (part II)
11/8/2005
10:30:06 am
7654321
1 2 3
3
18A8
12C1,18B1
6B1,14C8,15D8,27D1
7
0
6B8,14D1,18A8,20A1,26D1,28C1,29C8,31C8,34B8
18A110
18A1
0
5B1,10A1,14C1,26D1
8B1,26D1
9C1
9C1
14D1
30
26C1
12B8,34C1
12B8,34C1
R129
10K
TP18
TP20
0
34A1
10K
R124
33B1
14C1
3
11C1
2
1
014D8,15D8,27D1,28D1,29C8,31C8,33D1,34A8
15D8,26D1,34C1
4
3
1
4
6
11C1
14D8,26D1,34D1
1
23
1
0
7
6
5
VCC_3.3
31
34B8
14D1
14D1
14C1,18A1
18A1
5A1,11A8,26C1
16
VCC_3.3
8
9
28
29
5B8
13B8
14
13
5A8
29C8
R125
10K
1
28C1,29C8
9B1
22C1
5B8,31C8
15
0
2
14C1
14D1,26D1
28C1,29C8,31C8,33B1,34B1
15B8
28D1,29C8,31C8,33B1,34B1
7
11D1
0
5
6C1,14A8,26C1,34C1
4
3
0
1
14C1
33B1
2
14D1
12C1,18B1
10K
R119
T3
T4IO_T4
T5IO_T5
IO_T6T6
IO_T7T7
T8IO_T8
IO_T9T9
NPECL1H2
NPECL2H14
J2PPECL1
PPECL2J13
R6IO_R6
R7IO_R7
IO_R8R8
R9IO_R9
T10IO_T10
IO_T11T11
T12IO_T12
IO_T13T13
T14IO_T14
T2IO_T2
IO_T3
IO_P8
IO_P9P9
R1IO_R1
IO_R10R10
R11IO_R11
IO_R12R12
R13IO_R13
IO_R2R2
R3IO_R3
IO_R4R4
IO_R5R5
IO_P1
P10IO_P10
IO_P11P11
IO_P12P12
IO_P16P16
IO_P2P2
P3IO_P3
P4IO_P4
IO_P5P5
P6IO_P6
IO_P7P7
P8
IO_N15N15
N16IO_N16
N2IO_N2
IO_N3N3
N4IO_N4
N5IO_N5
IO_N6N6
IO_N7N7
N8IO_N8
IO_N9N9
P1
IO_M2M3
IO_M3M4
IO_M4M5
IO_M5M8
IO_M8M9
IO_M9
IO_N1N1
N10IO_N10
IO_N11N11
N12IO_N12
IO_N13N13
IO_L15
IO_L16L16
L2IO_L2
L3IO_L3
IO_L4L4
M1IO_M1
M12IO_M12
M13IO_M13
M14IO_M14
M15IO_M15
M16IO_M16
M2
K13IO_K13
IO_K14K14
K15IO_K15
IO_K16K16
IO_K2K2
K3IO_K3
IO_K4K4
IO_L1L1
L13IO_L13
IO_L14L14
L15
G3
G4IO_G4
IO_H12H12
H13IO_H13_GLMX2
IO_H3_GLMX1H3
IO_H5H5
J12IO_J12
IO_J14J14
J4IO_J4
IO_J5J5
K1IO_K1
GL1H1
GL2J1
GL3J16
H16GL4
IO_G1G1
IO_G13G13
IO_G14G14
IO_G15G15
IO_G16G16
G2IO_G2
IO_G3
1
5A1,11A8,26C1
31C8
5
5D8,9B1
9D8,34B1
$V
apa150.2of2.fbga256
U24
1
2
10
11
12
0
14D8
31C8
10K
R128
6B1,28B1,29D8,31D8,33B1,34B10
LB_GPL(0:5)
LB_SIZ(0:1)
ROBO_BANDEN*
28C1
R130
10K
DMARQ*(0:1)
DMADN*(0:1)
LB_A(0:31)
LB_CS*(0:7)
LB_D(0:31)
LB_WE*(0:3)
NVRAM_CS*
NVRAM_DIS*
PJET_CS*
RMT_FLASH*
NC
NC
NC
NC
ADT_SEL
ATM1_CS*
ATM1X_CS*
ATM2_CS*
CLA(23:0)
EVENT2*
RMT_UDE*
PCIEN
PCIEN*
ASLEEP
IRQ*(11:0)
LB_RD*
LB_WR*
CDC_SPR1
CDC_SPR2
DMACK*(0:1)
NC
NC
NC
NC
NC
ROBO_BAND
SDA
UTCOM_RST*
MEM_RST*
HRESET*
SYSRST*
ATM2_RST*
ATM1_RST*
CFGRST*
CFGDRV*
NVWD_RST*
PCIRST*
PWRGD_OVDD
PWRGD_CDC
MCP*
LEDS(0:7)
USERMODE(0:1)
PCI_PCIXCAP
PCI_M66EN
SENSE_TRDY*
SENSE_STOP*
SENSE_IRDY*
PCI_DUAL
ATM2_EN*
SCL
LCL_RST*
32
6 7 8
A
1 2 3 4 5
Date Changed:
Time Changed:Engineer:
Revision: 10:28:43 am
1. All components in the power path (large/red bus)
B
D
POWER SUPPLY LAYOUT RULES
Project:Page:Title:
should be on the same layer, with area filled connections.
freescaleFreescale Semiconductor
semiconductor
TM
C
2. No vias or thermal reliefs allowed on power path components.
3. Ground plane connections should be made with two vias closeto the component.
C
A
THERMAL HEATSINK PLANE FILL
B
D
10 cm^2 on top layer
7700 W. Parmer LnAustin, Texas 78729
1 87654
Gary Milliorn 081.2
CDS_CarrierSystem +2.5V Power Supply
11/8/2005
C3051.0uF
14C1
VCC_12
C293220uF
+
VCC_3.3
1.0uFC304
+220uFC234
+
ddpak3
U31
LT1587CM-1.5
GND1
3VIN
2VOUT
VOUT_TAB4
C247220uF
C208220uF
+220uFC127+
220uF+
220uFC212+
1 2 3 4
7
5 6
C18
irf6607
1 2 3 4
7
5 6
irf6604
IRF6604
Q2
C292220uF
+
Q1
IRF6607
+
100pFC54
CR2
MMSZ6V2T1
sod_123
10V220uFC62+
10V220uFC91
1.0uFC134
C136220uF10V
+
L1
1.1uH
C1281.0uF
6
VCCA VCCP
7 13
VCCQP
VFB5
20VID0
19VID1
VID218
17VID3
VID48
16VREF
CEXT1
ENABLE2
15
GNDA GNDD
14
GNDP1
10
11
GNDP2
12HIDRV
4IFB
9LODRV
PWRGD3
R69
0
rc5051m.so20
U15
smb_403aMBRS140T3CR1
1W
1%
R44
0.010
C551.0uF
0.1uFC147
VCC_5
No_Stuff
C1090.1uF
1.1uH
L2
+
VCC_2.5
R91
47
0
R70
220uFC291
No_Stuff
0
R900.1uFC72
0
R76
0
R77
+
No_Stuff
0
R71
No_Stuff
220uFC87+ C297
220uF220uFC306+ C289
220uF+C278+ C86
220uF+
10V
+ C146220uF10V
+
220uF
No_Stuff
22K
R64
C192220uF
U14
sot23_5p
MAX4372FEUK-T
1GND
2OUT
RSn
54
RSp
VCC3
VCC_3.3
1.0uFC90
VCC_5
0.1uFC145
C135220uF10V
+
VCC_1.5
7B8,26D1
10V220uFC193+
1.0uFC129
SHORT
VID2
SHORT
VID4 SHORT
VID3
SHORT
VID1
R75
10K
SHORT
VCCQPPOWER_TRACE
FILT_VCCAREA_FILL
PWRGD_OVDD
SWCOM AREA_FILL
PWR_KELVIN
AREA_FILL
IFB
POWER_TRACE
SHORT
VID0
SHORTVREF
OVM
POWER_TRACE
AREA_FILL
NC
SHORTCEXT
PWR_KELVIN
AREA_FILL
HIDRV SHORT
LODRV
43
A
B
D
21
1 2 3
Revision:Page:Title:
Project: Date Changed:
Time Changed:09
CDS_CarrierLocal (non-PCI) Resources: System Clock, System Reset
11/8/2005
10:30:22 amEngineer:
8
SPECIAL LAYOUT0402 as a 2x5 array of pads.
8
A
B
D
76
7
freescaleFreescale Semiconductor
semiconductor
TM 7700 W. Parmer Ln
6
LOCAL RESET
Non-re-config reset.
Austin, Texas 78729
CC
4 5
5
Gary Milliorn1.2
0
No_Stuff
33R186
U43
74lvc1g125.sc70
2
1
4
R206
74lvc1g125.sc70
U382
1
4R167 33
R173 33
7B8,34B1
12C1
VCC_3.3
VCC_5
34B1
27D1
15B8
U37
4GND
PBRST5
7RST3V
2RST5V
6TOL3V
3TOL5V
8VCC_3.3
1VCC_5
VCC_3.3
33R198
ds1834s.so8
A4
B
3GND
1OE
5VCC
100K
R163
U39
74lvc1g125.sc70
2
1
4
sop5
U56
SN74CBTLV1G125DBVR
2
U57
sop5
A2 4
B
3GNDOE
1
5VCC
11C1
14D1
7C1
34B133R197
6D8,11D1
SN74CBTLV1G125DBVR
VCC_3.3VCC_3.3
7B8
4.7K
R168
VCC_3.3
R180
100
No_StuffR182
100
No_Stuff
No_Stuff
100
R181
R188
R187
100
No_Stuff
29REF
22SOE
TEST27
14
VCC1
VCC2
30
VDDQ1221
12VDDQ3
5VDDQ4
No_Stuff
100
4F13
74Q0
64Q1
13FB
FS31
GND1
8 9GND2
17
GND3
GND4
18
28
GND5
4PE_HD
1Q0
191Q1
2F025
2F126
162Q0
152Q1
3F032
13F1
113Q0
103Q1
4F02
18A1
5D8,7C1
U50
CY7B9950AC
tqfp32231F0
241F1
20
74lvc1g125.sc70
U352
1
4
10C8
0R207
U45
74lvc1g125.sc70
2
1
4
0
13B8R164 33
7B8
13B8
0R205
R208
ROBO_BANDEN*
UT_CDCPCICLK
SYSCLK
1CM_MAX
330R204
SHORT
1CM_MAX
PCICLK
1CM_MAX
PCIENPCIEN*
PCICLK_COPY
UT_CDCSYSCLK
1CM_MAX
CDC_PCICLK
CDC_PCICLK2
ROBO_BAND SHORT
NC
NC
NC
NC
NC
NC
NC
NC
NC
LB_LACLK
UTCOM_LBCLK
CDC_LBCLKOUT SHORT
SHORT
LCL_RST*NC
HRESET_REQ*
RMT_RST*
CDC_SYSCLK
1CM_MAX
LA_PCICLK1CM_MAX
POR_RST*
PHASEFIX_PCICLK
NC
NC
NC
D
TM
Date Changed:
Time Changed:Engineer:
Project:
7
Revision:Page:Title:
8
7700 W. Parmer LnAustin, Texas 78729
C
A
B
D
C
HIGH-SPEED EXTERNAL CLOCKOptional high-speed/flexible
clock source.
65
Gary Milliorn1.2
10CDS_Carrier
High-Speed Clock Generation11/8/2005
10:30:37 am
4321
8
A
DEFAULT=124MHz
1 2 3 4 7
semiconductor
5 6
B
freescaleFreescale Semiconductor
LOCAL SYSTEM CLOCKUsed on non-PCI HIP boards or stand-alone.
R150
0
R127
Y1
125.00MHz
GND2 1
OE
OUT 34 V3.3V
10
VCC_3.3
33R148
6
5
4 33R166
15V5
16V6
17V7
18V8
6
VDD1 VDD2
23
7X1_ICLK
X28
3S0
S14
S25 10
V0
11V1
12V2
13V3
14V4
PDTS
24R0
R125
26R2
27R3
R428
1R5
R62
22REF
U42ics525_02.ssop28
CLK21
9
GND1 GND2
20
19
C311
0.1uF
5D8
R174 33
C312
0.1uF 0.1uF
C309
2
1
4
100
R178
74lvc1g125.sc70
U302
1
4
U26
74lvc1g125.sc70
No_Stuff
conn.smaP2
5D8
3
14C1
R172
100No_Stuff
2
1
4
100
R175R179
100
3
2
1
4
0.1uFC249
0.1uF
C317
VCC_3.3
74lvc1g125.sc70
U36
U44
16.000MHz
GND2 1
OE
OUT 34 V3.3V
1
0
5C8
5C8
33R165
5B1,7A1,14C1,26D1
6D1
VCC_3.3
C2680.1uF
100
R171
0.01uFC286
2
1
R170
100
10R177
9B1
R140
100
6C1
6B1
470uFC310+
2
1
4
VCC_3.3
100K
R135
9
20XTAL_SEL
22uFC285
+
U28
74lvc1g125.sc702
SDATA
S_LOAD3
TEST26
VCC127
28VCC2
VCC332
VCC_PLL14
5VCC_PLL2
XTAL_IN8
XTAL_OUT
M6
N022
23N1
16NC1
NC221
24NC3
10OE
PWR_DOWN6
P_LOAD11
SCLK1
30
FREF_EXT7
25GND1
GND229
12M0
M113
14M2
M315
17M4
M518
19
16D1
16D1
mpc9259fa.lqfp32
U29
FOUT31
FOUTn
2
1
4
VCC_3.3
20B1
6C1R146 33
U32
74lvc1g125.sc70
2
1
4
74lvc1g125.sc70
U33
2CM_MAXREF_CLK
RTC_CLKSHORT
SHORT
2
VCC_3.3
NC
NC
LCLK_V(6:1)
LCLK_R(4:1)
1CM_MAXUTRTCCLKOMCLK_DIS*
PHY_CLK0
SHORT
1CM_MAXSYSCLK SYSCLKUTSYSCLKO 1CM_MAX
POWER_TRACE
REF16 1CM_MAX
NC
LCLK_S(2:0)
NC
NC
HS_TXCLKnHSCLKDP_HSCLK
NC
NC
NC
NC
NC
CFGRST*
NC
NC
NC
HSCLK_DATA
HSCLK_CLK
HSCLK_LD*
SYNC_CLK
SYNCHRO*
SHORT
NC
SHORT
SHORT
CTLCLK
HS_TXCLKpHSCLKDP_HSCLK
SHORT_POWER
NC
NC
NC
Addr=0x56
REMOTE CONTROL ACCESS HEADER
Time Changed:
3 4 5 6 7 8
A
B
D
Date Changed:Engineer:
Revision:Page:Title:
Project:
A
7700 W. Parmer LnAustin, Texas 78729
C
freescaleFreescale Semiconductor
semiconductor
TM
B
D
C
87
Gary Milliorn1.2
11CDS_Carrier
Miscellaneous: LEDs, Debug Port and I2C Devices11/8/2005
10:30:52 am
65432
POWER-ON RESET
Re-config reset.
1
1 2
CARRIER CONFIG
2
1
4
5B8
VCC_3.3
74lvc1g125.sc70
U42
1
4
74lvc1g125.sc70
U3
1A0
A1
23A2
CLK6
5DATA
WC7
VCC_3.3VCC_3.3
14C1
14D1
4.7K
R47
at24c64a.s08
U1
220
7C1
4.7K
R58
220
220R33
R28VCC_3.3
R34220
R35
D4
Red L3_Sleep
4
7A8
D1
1
2
1K
R45
R30
0
L0_VddRed
9D1
6D8,9D1
220R31
220
100
D7
Red L6_Mem
VCC_3.3
D5
100R36
R37
D9
Green Vdd3VCC_3.3
L4_ResetRed
L2_PCIRed
D3
VCC_2.5
L7_I2CRed
D8
Red L1_PCIEn
OVddGreen
D10
7A8
R48
4.7K
VCC_3.3
D2
4.7K
R52 R51
4.7K
VCC_5
100K
R153
ds1834s.so8
U34
4GND
PBRST5
7RST3V
2RST5V
6TOL3V
3TOL5V
8VCC_3.3
1VCC_5
VCC_3.3
L5_Clk
5B8
SW5
sw.1spdt1
23
220R29
D6
Red
7
6
5
R32220
1
10
2
3 4
5 6
7 8
9
1ENABLE
GND
4
READY5
SCL_I3
SCL_O2
6SDA_I
7SDA_O
8
VCC
J1header.ra.2x5
R57
4.7K
U2
ltc4300_1.ms8
5A1,7B8,26C1
5A1,7B8,26C1
VCC_3.3
R46
1K
3
NC
RMT_RST*
CFG_RST*
RMT_FLASH*
NC
POR_RST*
CFG_UDE*
NC
NC
NC
CDC_SCL
CDC_SDA
LEDS(0:7)
RMT_UDE*
SDA
SCL
freescaleFreescale Semiconductor
semiconductor
TM
1
1 2 3 4 5 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer: Gary Milliorn
1.212
CDS_CarrierCDC DaughterCard Connector (Left, Part I)
11/8/2005
10:26:51 amRevision:Page:Title:
Project:
C
Austin, Texas 787297700 W. Parmer Ln
A
B
D
C
8765432
10
17
6
9
16
19
0
1
4
7B8,18B1
0
1
5
10
13
10
20
23
18B1
0
1
18B1
23
8
14
16
23
07B8,34C1
7B8,34C1
28
9
19
22
13
20
22C1
19D1
VCC_2.5
4
7
24
14
12
20
12
24
4
2
3
3
0
23
0
1
32
33
4
7
34
35
15
11
17
20
18A1
9A8
11
14
VCC_3.3
2
1
2
5
3
26
25
24
23
22
2
3
20
VCC_2.5
7C8,18B1
23C1
29
28
22
18A1
17
16
19A8
1
19
18
18A1
18B1
1
VCC_3.3
13
16
25
18A1
8
15
3
7
13
16
22C1
8
16
6
24
5
B7
B8
B9
VCC_2.5
17
18A1
13D1,18D8
13D1,18B8
B34
B35
B36
B37
B38
B39
B4
B40
B5
B6
B26
B27
B28
B29
B3
B30
B31
B32
B33
B18
B19
B2
B20
B21
B22
B23
B24
B25
B1
B10
B11
B12
B13
B14
B15
B16
B17
A38
A39
A4
A40
A5
A6
A7
A8
A9
A30
A31
A32
A33
A34
A35
A36
A37
A22
A23
A24
A25
A26
A27
A28
A29
A3
A15
A16
A17
A18
A19
A2
A20
A21
VCC_3.3
FCI 74390-001
conn.megarray.10x40.1of5J10
A1
A10
A11
A12
A13
A14
21
24
8
11
30
18
21
1
0
9
12
12
20
19
22
2
23A1
31
21
0
18
27
2
2
2
27
0
8
19A1
12
15
21
6C8
4
D4
D40
D5
D6
D7
D8
D9
6
D32
D33
D34
D35
D36
D37
D38
D39
D24
D25
D26
D27
D28
D29
D3
D30
D31
D17
D18
D19
D2
D20
D21
D22
D23
C9
D1
D10
D11
D12
D13
D14
D15
D16
C37
C38
C39
C4
C40
C5
C6
C7
C8
C29
C3
C30
C31
C32
C33
C34
C35
C36
C20
C21
C22
C23
C24
C25
C26
C27
C28
C12
C13
C14
C15
C16
C17
C18
C19
C2
F7
F8
F9
FCI 74390-001
conn.megarray.10x40.2of5J10
C1
C10
C11
F35
F36
F37
F38
F39
F4
F40
F5
F6
F28
F29
F3
F30
F31
F32
F33
F34
F19
F2
F20
F21
F22
F23
F24
F25
F26
F27
F1
F10
F11
F12
F13
F14
F15
F16
F17
F18
E39
E4
E40
E5
E6
E7
E8
E9
E31
E32
E33
E34
E35
E36
E37
E38
E23
E24
E25
E26
E27
E28
E29
E3
E30
E15
E16
E17
E18
E19
E2
E20
E21
E22
FCI 74390-001
conn.megarray.10x40.3of5
J10
E1
E10
E11
E12
E13
E14
TP35
TP32
18
13A1,24A1,26A1
1
18A1
3
VCC_12
9
18A1
18B1
18B1
18B8
13A1,25A1,26A1
TSEC3(0:24)
PB(4:31)
UART2(0:3)
UART1(0:3)
USB2(0:2)
USB1(0:2)
CDC_SPR1
CDC_SPR2
NC
DEFAULT_NET_TYPE
PCI_FRAME*
COP_HRST*
CPM_CLASS
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPEDEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
PA(0:31)
DEFAULT_NET_TYPE
CPM_CLASS
CDC_SYSCLK
PCI_CBE*(7:0)
PCI_PERR*
PCI_IRDY*
PCI_TRDY*
PCI_DEVSEL*
PCI_IDSEL
PCI_GNT*
PCI_PCIXCAP
PCI_M66EN
PCI_REQ64*
PCI_SERR*
TSEC1(0:24)
NC
NC
TSEC2(0:24)
PCI_AD(63:0)
PCI_STOP*
NC
NC
PCI_PAR
PCI_REQ*
pwr
PCI_ACK64*
C
76
A
B
D
C
432
2 3 4 5 6 7 8
A
B
Gary Milliorn1.2
13CDS_Carrier
CPU DaughterCard Connector (Left, part II)11/8/2005
10:27:06 am
D
Date Changed:
Time Changed:freescale
Freescale Semiconductor
semiconductor
TM Engineer:Revision:
Page:Title:Project:
1
1
7700 W. Parmer LnAustin, Texas 78729
85
62
63
1
0
3
2
5
4
21
29
52
53
50
51
6C8
29
3
6
15
18
27
14
22
26
6
10
18
21
19
23
31
37
9B8
10
30
26
19
15
7
7
11
39
38
49
2
59
57
VCC_3.3
5
12D1,18D8
12D1,18B8
7
42
41
40
61
5
13
17
24
28
20B1
6
10
9
56
11
60
22
25
31
VCC_2.5
VCC_3.3
8
7
12A1,24A1,26A1
5
9
17
9A8
11
14
K7
K8
K9
VCC_3.3
VCC_2.5
20A1,26C1
20A1,26C1
12A1,25A1,26A1
K35
K36
K37
K38
K39
K4
K40
K5
K6
K28
K29
K3
K30
K31
K32
K33
K34
K2
K20
K21
K22
K23
K24
K25
K26
K27
K11
K12
K13
K14
K15
K16
K17
K18
K19
J4
J40
J5
J6
J7
J8
J9
K1
K10
J32
J33
J34
J35
J36
J37
J38
J39
J23
J24
J25
J26
J27
J28
J29
J3
J30
J31
J15
J16
J17
J18
J19
J2
J20
J21
J22
J10
conn.megarray.10x40.5of5
74390-001FCI
J1
J10
J11
J12
J13
J14
H39
H4
H40
H5
H6
H7
H8
H9
H3
H30
H31
H32
H33
H34
H35
H36
H37
H38
H22
H23
H24
H25
H26
H27
H28
H29
H14
H15
H16
H17
H18
H19
H2
H20
H21
G6
G7
G8
G9
H1
H10
H11
H12
H13
G34
G35
G36
G37
G38
G39
G4
G40
G5
G27
G28
G29
G3
G30
G31
G32
G33
G17
G18
G19
G2
G20
G21
G22
G23
G24
G25
G26
G1
G10
G11
G12
G13
G14
G15
G16
46
47
48
VCC_2.5
7C1
30
J10
conn.megarray.10x40.4of5
74390-001FCI
6
13
14
15
43
44
45
55
58
3618B8
12
4
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
CDC_PCICLK2
54
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPEDEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
CPM_CLASS
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPEDEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPEDEFAULT_NET_TYPE
DEFAULT_NET_TYPEDEFAULT_NET_TYPE
PCI_CBE*(7:0)
PCI_AD(63:0)
MDC
NC
MDIO
UDE*
NC
NC
CDC_PCICLK
ASLEEP
NC
NC
PB(4:31)
PA(0:31)
DEFAULT_NET_TYPE
CPM_CLASS
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
PCI_PAR64
NC
NC
GTXCLK125
NC NC
Project:
7 8
7700 W. Parmer LnAustin, Texas 78729
C
A
B
D
C
6543
freescaleFreescale Semiconductor
semiconductor
TM
2
1 2 3
1
5 6 7 8
Gary Milliorn 141.2
CDS_CarrierCDC DaughterCard Connector (Right, Part I)
11/8/2005
10:27:20 am
4
B
D
Date Changed:
A
Time Changed:Engineer:
Revision:Page:Title:
24
20
30
1310
5
15
25
10
20
31
10
14
23
27
VCC_3.3
6
3
TP34
TP33
8C8
26D1,34B1
2
19
28
7C1
7D1
0
D38
D39
D4
D40
D5
D6
D7
D8
D9
D29
D3
D30
D31
D32
D33
D34
D35
D36
D37
D21
D22
D23
D24
D25
D26
D27
D28
D13
D14
D15
D16
D17
D18
D19
D2
D20
C5
C6
C7
C8
C9
D1
D10
D11
D12
C33
C34
C35
C36
C37
C38
C39
C4
C40
C24
C25
C26
C27
C28
C29
C3
C30
C31
C32
C16
C17
C18
C19
C2
C20
C21
C22
C23
74390-001
conn.megarray.10x40.2of5J11
C1
C10
C11
C12
C13
C14
C15
0
1
2
27
VCC_5
1
FCI
F9
0
1
7
16
21
30
F37
F38
F39
F4
F40
F5
F6
F7
F8
F3
F30
F31
F32
F33
F34
F35
F36
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F12
F13
F14
F15
F16
F17
F18
F19
F2
E5
E6
E7
E8
E9
F1
F10
F11
E34
E35
E36
E37
E38
E39
E4
E40
E25
E26
E27
E28
E29
E3
E30
E31
E32
E33
E18
E19
E2
E20
E21
E22
E23
E24
E1
E10
E11
E12
E13
E14
E15
E16
E17
B40
B5
B6
B7
B8
B9
FCI 74390-001
conn.megarray.10x40.3of5
J11
B33
B34
B35
B36
B37
B38
B39
B4
B24
B25
B26
B27
B28
B29
B3
B30
B31
B32
B16
B17
B18
B19
B2
B20
B21
B22
B23
A8
A9
B1
B10
B11
B12
B13
B14
B15
A36
A37
A38
A39
A4
A40
A5
A6
A7
A27
A28
A29
A3
A30
A31
A32
A33
A34
A35
A19
A2
A20
A21
A22
A23
A24
A25
A26
A11
A12
A13
A14
A15
A16
A17
A18
3
20
24
FCI 74390-001
conn.megarray.10x40.1of5J11
A1
A10
4
7
6
7
6
5
4
29
7A1
0
3
2
VCC_5
10D8
7A8
10
26
5
17
2
0
VCC_5
9
8
0
1
11A1
7B8
7C8
8
12
22
6B1,7A1,15D8,27D1
7C8,26D1,34D1
6
3
5B1,7A1,10A1,26D1
1
2
25
16
12
29
3
1
7D1
11A1
19
15A1,24A1,25A1,26A1
15A1,27A1
9
3
2
2
VCC_12N
7
4
4
0
0
7
6
5
4
15A1,24A1,25A1,27A1
7C8,15D8,27D1,28D1,29C8,31C8,33D1,34A8
1
31
VCC_5
7B8,18A1
34C1
7B1,26D1
11
1
29
9D1
15
6
11
7
17
1
5
9
18
22
28
0
11
6C1,7A1,26C1,34C1
0 3 2
1
6B8,7A1,18A8,20A1,26D1,28C1,29C8,31C8,34B8
4
30
1
VCC_2.5 VCC_2.5 VCC_2.5
5
31
5
NC
NC
NC
NC
NC
CX(0:31)
8
6D8
0
14
7D1
NCNC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
LB_CS*(0:7)
LB_A(0:31)
NC
NC
DMADN*(0:1)
NC
DMACK*(0:1)
DMARQ*(0:1)
NC
LB_GPL(0:5)
LB_DP(0:3)
NC
NC
LB_D(0:31)
OVM
SRESET*
HRESET*
MCP*
NC
HRESET_REQ*
LB_LBCTL
LB_SIZ(0:1)
IRQ*(11:0)
PCIRST*
CFGRST*
NC
PWRGD_CDC
CFGDRV*
CDC_SDA
NC
CDC_SCL
NC
PC(0:31)
PD(4:31)
RTC_CLK
PCI_DUAL
freescaleFreescale Semiconductor
semiconductor
TM Title:Project:
5 6
7700 W. Parmer LnAustin, Texas 78729
C
A
B
D
C
874321
1 2 3 4
Gary Milliorn 151.2
CDS_CarrierCDC DaughterCard Connector (Right, Part II)
11/8/2005
10:27:33 am
5 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:
19
20
28
VCC_3.3
12
15
14
21
20
27
17
26
17
18
6
4
VCC_2.5
10
31
0
25
23
19
16
16
15
26D1,34C1
30
29
12
31
30
27
VCC_3.3
12
11
7
VCC_2.5
H6
H7
H8
H9
0
29
28
H35
H36
H37
H38
H39
H4
H40
H5
H27
H28
H29
H3
H30
H31
H32
H33
H34
H19
H2
H20
H21
H22
H23
H24
H25
H26
H10
H11
H12
H13
H14
H15
H16
H17
H18
G39
G4
G40
G5
G6
G7
G8
G9
H1
G31
G32
G33
G34
G35
G36
G37
G38
G23
G24
G25
G26
G27
G28
G29
G3
G30
G15
G16
G17
G18
G19
G2
G20
G21
G22
1
FCI 74390-001
conn.megarray.10x40.4of5
J11
G1
G10
G11
G12
G13
G14
19
24
22
8
28
9
18
13
11
1
5
18
16
K8
K9
14A1,27A1
2
17
K36
K37
K38
K39
K4
K40
K5
K6
K7
K28
K29
K3
K30
K31
K32
K33
K34
K35
K2
K20
K21
K22
K23
K24
K25
K26
K27
K11
K12
K13
K14
K15
K16
K17
K18
K19
J40
J5
J6
J7
J8
J9
K1
K10
J32
J33
J34
J35
J36
J37
J38
J39
J4
J24
J25
J26
J27
J28
J29
J3
J30
J31
J16
J17
J18
J19
J2
J20
J21
J22
J23
FCI 74390-001
conn.megarray.10x40.5of5
J11
J1
J10
J11
J12
J13
J14
J15
25
24
TP36
14
22
9
18
VCC_2.5
9C1
14A1,24A1,25A1,26A1
26
VCC_3.3
24
14A1,24A1,25A1,27A1
8
13
21
26
4
23
22
21
20
26
25
23
11
10
9
8
21
14
13
3
7C1,26D1,34C1
27
2
13
CX(0:31)
23
3
15
7C8,14D8,27D1,28D1,29C8,31C8,33D1,34A8
6B1,7A1,14C8,27D1
CDC_LBCLKOUT
NC
LB_D(0:31)
LB_A(0:31)
LB_WE*(0:3)
NC
PC(0:31)
PD(4:31)
LB_LALE
NC
NC
TM
Time Changed:Engineer:
Expansion Ports
Revision:Page:Title:
Project:
5
11/8/2005
10:27:47 am
4
7700 W. Parmer LnAustin, Texas 78729
C
A
B
7
D
C
8654321
1 2 3 6 7 8
A
B
D
Date Changed:freescale
Freescale Semiconductor
semiconductor
Gary Milliorn 161.2
CDS_CarrierHigh-Speed IO Daughtercard Connector
13
14
15
16
17
18
TP38
4
5
10A8
10A8
2
37
38
0
1
TP37
30
6
5
33
34
1
22
25
26
10
9
29
B86
B87
B88
B89
B90
21
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
A85
A86
A87
A88
A89
A90
B61
B62
B63
B64
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
B57
B58
B59
B60
J12conn.qsh.2x90.3of3
QTH-090-02-F-D-A
A61
A62
A63
B48
B49
B50
B51
B52
B53
B54
B55
B56
B39
B40
B41
B42
B43
B44
B45
B46
B47
B31
B32
B33
B34
B35
B36
B37
B38
A53
A54
A55
A56
A57
A58
A59
A60
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A35
A36
A37
A38
A39
A40
A41
A42
B9
GND1
J12conn.qsh.2x90.2of3
QTH-090-02-F-D-A
A31
A32
A33
A34
B28
B29
B3
B30
B4
B5
B6
B7
B8
B2
B20
B21
B22
B23
B24
B25
B26
B27
B12
B13
B14
B15
B16
B17
B18
B19
A4
A5
A6
A7
A8
A9
B1
B10
B11
A23
A24
A25
A26
A27
A28
A29
A3
A30
A15
A16
A17
A18
A19
A2
A20
A21
A22
QTH-090-02-F-D-A
conn.qsh.2x90.1of3
J12
A1
A10
A11
A12
A13
A14
9
10TP41
TP42
35
36
37
38
39
17A1
28
29
30
31
32
33
34
22
23
24
25
26
27
15
16
17
18
19
20
21
11
12
6
7
13
14
3
4
39
8
2
3
7
31
32
17A1
0
35
36
23
24
12
11
27
28
8
HS_TD(0:39)
HS_TXCLKp
19
20
HS_RD(0:39)
NC
NC
NC
NC
NC
NC
HS_TXCLKn
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
From processor to motherboard/target.Receive PathTo processor from motherboard/target.
freescaleFreescale Semiconductor
semiconductor
TM
1 2 3 4 5 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
B
disassembler.
7700 W. Parmer LnAustin, Texas 78729
C
Gary Milliorn 171.2
CDS_CarrierHigh-Speed Differential IO, HMZD/HIP Interface and P6880 "Banjo" Receive probes
11/8/2005
10:28:00 am
A
connectors, despite appearances!
differences are handled in the
8765432
D
C
The high-speed protocol signals are
routed THROUGH the Tek P6880
Yes, the connector connections areconnected correctly! Polarity
1
Transmit Path
35
22
A10D6+
A12D6-
D7+B12
D7-B10
8
37
36
A4D2+
A6D2-
D3+B6
D3-B4
A7D4+
A9D4-
D5+B9
D5-B7
P1conn.banjo
CLK_QUAL+A13
A15CLK_QUAL-
A1D0+
A3D0-
D1+B3
D1-B1
guide_module.keyed.ra223986-1
GM1
GM2
223986-1guide_module.keyed.ra
32
33
0
19
18
2
3
17
14
1
2
38
39
12
13
23
36
37
5
6
36
35
34
33
25
11
13
4
5
6
7
9
26
27
20
7
10
34
35
21
22
0
24
6
7
H9
3
4
31
31
24
H10
H2
H3
H4
H5
H6
H7
H8
GHG2
GHG3
GHG4
GHG5
GHG6
GHG7
GHG8
GHG9
H1
G5
G6
G7
G8
G9
GHG1
GHG10
F6
F7
F8
F9
G1
G10
G2
G3
G4
EFG8
EFG9
F1
F10
F2
F3
F4
F5
EFG1
EFG10
EFG2
EFG3
EFG4
EFG5
EFG6
EFG7
E2
E3
E4
E5
E6
E7
E8
E9
D4
D5
D6
D7
D8
D9
E1
E10
CDG6
CDG7
CDG8
CDG9
D1
D10
D2
D3
C8
C9
CDG1
CDG10
CDG2
CDG3
CDG4
CDG5
C1
C10
C2
C3
C4
C5
C6
C7
B3
B4
B5
B6
B7
B8
B9
ABG4
ABG5
ABG6
ABG7
ABG8
ABG9
B1
B10
B2
A7
A8
A9
ABG1
ABG10
ABG2
ABG3
P7conn.amp.HMZd.40pr.recpt.ra
A1
A10
A2
A3
A4
A5
A6
11
12
25
23
16
17
A9
B9D5+
B7D5-
D6+A10
D6-A12
B12D7+
B10D7-
VCC_5
B3D1+
B1D1-
D2+A4
D2-A6
B6D3+
B4D3-
D4+A7
D4-
20
conn.banjoP3
A13CLK_QUAL+
CLK_QUAL-A15
D0+A1
D0-A3
2
3
38
14
23
22
21
13
14
15
8
9
1
B1
B2
B3
B4
C1
C2
C3
C4
28
C2
C3
C4
223961-1
P5
conn.pwr.3pos.ra
A1
A2
A3
A4
A1
A2
A3
A4
B1
B2
B3
B4
C1
D5-B7
A10D6+
A12D6-
D7+B12
D7-B10
29
223961-1
P6
conn.pwr.3pos.ra
B1
A4D2+
A6D2-
D3+B6
D3-B4
A7D4+
A9D4-
D5+B9
P4conn.banjo
A13CLK_QUAL+
CLK_QUAL-A15
A1D0+
A3D0-
D1+B3
D1-
8
9
16
29
28
38
39
17
30
16D1
27
26
32
18
19
12
15
16
30
29
28
37
1
0
2118
15
20
10
11
39
34
26
27
30
VCC_3.3
19
16C1
4
5
10
31
32
33
RFRM
25
24
NC
NC
NC
NC
NC
NC
NC
HS_RD(0:39)
NC
NC
NC
NC
NC
NC
NC
RFRMHSDIFF_R
HSDIFF_T TD14
TD15HSDIFF_T
TD15HSDIFF_T
HSDIFF_T TCLK1TCLK1
TCLK1HSDIFF_T TCLK1
HS_TD(0:39)
TD11HSDIFF_T
TD11HSDIFF_T
TD12HSDIFF_T
TD12HSDIFF_T
HSDIFF_T TD13
HSDIFF_T TD13
HSDIFF_T TD14
TD8HSDIFF_T
TD8HSDIFF_T
HSDIFF_T TD9
HSDIFF_T TD9
HSDIFF_T TD10
HSDIFF_T TD10
HSDIFF_R RAUX
HSDIFF_R RAUX
TCLK0HSDIFF_T TCLK0
TFRMTFRMHSDIFF_T
HSDIFF_T TAUXTAUX
HSDIFF_T TAUXTAUX
RD13HSDIFF_R
RD13HSDIFF_R
RD14HSDIFF_R
RD14HSDIFF_R
HSDIFF_R RD15
HSDIFF_R RD15
RD9HSDIFF_R
RD10HSDIFF_R
RD10HSDIFF_R
HSDIFF_R RD11
HSDIFF_R RD11
HSDIFF_R RD12
HSDIFF_R RD12
HSDIFF_R
RFRMHSDIFF_R
HSDIFF_R RCLK1
HSDIFF_R RCLK1
HSDIFF_R RD8
HSDIFF_R RD8
RD9HSDIFF_R
TD6HSDIFF_T
TD6HSDIFF_T
HSDIFF_T TD7
HSDIFF_T TD7
RCLK0
TD2HSDIFF_T
TD2HSDIFF_T
HSDIFF_T TD3
HSDIFF_T TD3
HSDIFF_T TD4
HSDIFF_T TD4
TD5HSDIFF_T
TD5HSDIFF_T
RD6
RD7HSDIFF_R
RD7HSDIFF_R
TCLK0TCLK0HSDIFF_T
HSDIFF_T TD0
HSDIFF_T TD0
TD1HSDIFF_T
TD1HSDIFF_T
RD2
RD3HSDIFF_R
RD3HSDIFF_R
RD4HSDIFF_R
RD4HSDIFF_R
HSDIFF_R RD5
HSDIFF_R RD5
HSDIFF_R RD6
HSDIFF_R
TFRMTFRMHSDIFF_T
RCLK0HSDIFF_R
RD0HSDIFF_R
RD0HSDIFF_R
HSDIFF_R RD1
HSDIFF_R RD1
HSDIFF_R RD2
HSDIFF_R
1 2
freescaleFreescale Semiconductor
semiconductor
TM
3 4 5 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
8
7700 W. Parmer LnAustin, Texas 78729
C
(motherboard-dependant option also).
754
A
B
D
Place sense Rs within 1cm of edge connector
C
NON-STANDARDAllow PCI/HIP card to reset motherboard
6321
Gary Milliorn 181.2
CDS_CarrierPrimary PCI/PCI-X Edge Connector
11/8/2005
10:28:15 am
22
21
9B1
38
34
54
7B8,14C1
B19
B59
B70
26
25
24
23
TRDYA36
TRSTA1
A10
B79
B88
A16
A59
A66
A75
A84
RSTA15
SBOA41
SDONEA40
SERRB42
STOPA38
TCKB2
TDIA4
TDOB4
TMSA3
B49
PARA43
A67PAR64
B38PCIXCAP
PERRB40
PRSNT1B9
PRSNT2B11
REQB18
A60REQ64
A17
IDSELA26
INTAA6
INTBB7
INTCA7
INTDB8
IRDYB35
LOCKB39
M66EN
B33C_BE3
B26
B66C_BE4
A65C_BE5
B65C_BE6
A64C_BE7
B37DEVSEL
FRAMEA34
GNT
AD62
B68AD63
AD7B53
B52AD8
AD9A49
CLKB16
C_BE0A52
C_BE1B44
C_BE2
AD55
A73AD56
B72AD57
A71AD58
B71AD59
AD6A54
A70AD60
B69AD61
A68
AD48
B78AD49
AD5B55
A77AD50
B77AD51
A76AD52
B75AD53
A74AD54
B74
AD40
B84AD41
A83AD42
B83AD43
A82AD44
B81AD45
AD46A80
B80AD47
A79
AD33
A89AD34
B89AD35
AD36A88
B87AD37
A86AD38
B86AD39
AD4A55
A85
A23AD27
B23AD28
A22
AD29B21
AD3B56
AD30A20
AD31B20
A91AD32
B90
B30
AD2A57
AD20A29
AD21B29
AD22A28
AD23B27
AD24A25
AD25B24
AD26
A47AD12
B47AD13
A46AD14
B45AD15
A44
AD16A32
B32AD17
AD18A31
AD19
12D1
12D1
pcix_edgeconn_64bit
P8
B60ACK64
AD0A58
AD1B58
AD10B48
AD11
2
1
56
12C1
53
12D1,13D1
31
12C8
4
13C1
12D1
12D1
12C8
12C8
0
3
13
12
0
52
12D1
49
48
19
18
17
16
15
14
7C8PCI_EDGE10R203
57
50
11
PCI_EDGER202 107A1
63
62
42
41
40
39
12C8
28
27
36
35
10
51
8
30
29
43
61
60
59
58
37
1
2
47
46
45
44
PCI_EDGE10R201
7C8,12C1
9
12C1
7
33
32
7
6
VCC_3.3
7C8
0
7B8,12C1
R161 07B1
4
3
2
1
12C8
12C8
55
5
3
6B8,7A1,14D1,20A1,26D1,28C1,29C8,31C8,34B8
12D1,13D1
20
6
5
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI_PCIXCAP PCI
SYSRST*
SENSE_TRDY*
SENSE_STOP*
SENSE_IRDY*
PCICLK
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCIPCI_ACK64*
NC
PCI
PCI PCI_PAR64
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI_IRDY* PCI
PCI_TRDY* PCI
PCI_STOP* PCI
NCPCI_PERR* PCI
PCI_SERR* PCI
NC
NCPCIPCI_M66EN
PCIPCI_GNT*
PCIPCI_REQ*PCI_REQ64* PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI_CBE*(7:0)
PCI
PCI
PCI
PCI
IRQ*(11:0)
PCIPCIRST*
PCI_FRAME* PCI
PCI_DEVSEL* PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI_AD(63:0)
PCI
PCI_IDSEL PCI PCI PCI_PAR
NC
NC
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
semiconductor
TM
4 5 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
_
C
Austin, Texas 787297700 W. Parmer Ln
8
Gary Milliorn 191.2
CDS_CarrierQuad 10/100/GB PHY MAC Interfaces
11/8/2005
10:31:05 am
765
A
B
D
C
4321
1 2 3
freescaleFreescale Semiconductor
15
14
24
11
10
8
9
17
16
0
12
1
13
0
21
24
22
23
2
0
1
12A1
88
18
10
13
12
14
4
15
13
5
1
4
2
3
21
2
5
7
24
22
21
20
1919
4
6
17
5
16
15
14
T25TX_EN_0
TX_EN_1AD22
AE12TX_EN_2
TX_EN_3AF1
U25TX_ER_0
AE23TX_ER_1
AE11TX_ER_2
AE1TX_ER_3
16
AF13
SAE2TXD6_3
TXD7_0T26
AD24TXD7_1
TXD7_2AF12
SAF2TXD7_3
TX_CLK_0AC26
AE17TX_CLK_1
TX_CLK_2AE5
V2TX_CLK_3
TXD4_1
TXD4_2AE14
SAD4TXD4_3
TXD5_0R25
AF24TXD5_1
TXD5_2AE13
SAD3TXD5_3
TXD6_0R26
AD23TXD6_1
TXD6_2
TXD1_3
TXD2_0N26
AE25TXD2_1
TXD2_2AF15
AF3TXD2_3
TXD3_0P26
AF25TXD3_1
TXD3_2AF14
AE3TXD3_3
TXD4_0P25
AE24
RX_ER_2AE6
W1RX_ER_3
TXD0_0M25
AF26TXD0_1
TXD0_2AE16
AE4TXD0_3
TXD1_0N25
AE26TXD1_1
TXD1_2AE15
AD5
RX_CLK_0AC25
AF18RX_CLK_1
RX_CLK_2AD6
W2RX_CLK_3
AB26RX_DV_0
RX_DV_1AE19
AF6RX_DV_2
RX_DV_3Y2
RX_ER_0AB25
AE18RX_ER_1
SRXD5_3AA2
AA25RXD6_0
RXD6_1AF20
AF7RXD6_2
SRXD6_3AA1
AA26RXD7_0
RXD7_1AF19
AE7RXD7_2
SRXD7_3Y1
AE21
AE9RXD3_2
RXD3_3AB2
Y26RXD4_0
RXD4_1AF21
AF8RXD4_2
SRXD4_3AB1
Y25RXD5_0
RXD5_1AE20
AE8RXD5_2
AD1
V25RXD1_0
RXD1_1AE22
AE10RXD1_2
RXD1_3AC2
W26RXD2_0
RXD2_1AF22
AF9RXD2_2
RXD2_3AC1
W25RXD3_0
RXD3_1
AF4CRS_2
CRS_3U1
GTX_CLK_0U26
GTX_CLK_1AF23
GTX_CLK_2AF11
SGTX_CLK_3AD2
V26RXD0_0
RXD0_1AD21
AF10RXD0_2
RXD0_3
6
U6
cis8204.macs.2of3.pbga388
COL_0AD26
AF17COL_1
COL_2AF5
V1COL_3
AD25CRS_0
CRS_1AF16
23
9
14
11
7
20
9
9
10
13
12
22
3
17
3
0
5
19
18
7
20
6
18
1
11
16
15
23
2
6
4
12A1
10
8
12
19
18
17
20
24
22
23
25D8
7
11 TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC2
12A1
21
3
TSEC2
TSEC2
TSEC2
TSEC2
TSEC2
TSEC2
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
TSEC4
TSEC4
TSEC2
TSEC2
TSEC2
TSEC2
TSEC2
TSEC2
TSEC1
TSEC1
TSEC1
TSEC1
TSEC1
TSEC1
TSEC1
TSEC1
TSEC1
TSEC1
TSEC1
TSEC2
TSEC2
TSEC2
TSEC2
TSEC1
TSEC1
TSEC1
TSEC1
TSEC1
TSEC1
TSEC1
TSEC1
TSEC1
TSEC1
TSEC1
TSEC1
TSEC2
TSEC2
TSEC2
TSEC2
TSEC2
TSEC2
TSEC2
TSEC2
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC1
TSEC1
TSEC2(0:24)
TSEC1(0:24) TSEC3(0:24)
TSEC4(0:24)
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
TSEC3
Revision:Page:Title:
Project:
_7 8
7700 W. Parmer LnAustin, Texas 78729
C
A
B
D
C
65
Gary Milliorn 201.2
CDS_CarrierQuad 10/100/Gb PHY Power/System Interface
11/8/2005
10:31:19 am
4321
1
freescaleFreescale Semiconductor
semiconductor
TM
3 42 65 8
A
7
B
D
Date Changed:
Time Changed:Engineer:
C220.1uF
No_Stuff
R72 0
C70.1uF
C91000pF
VCC_3.3
1000pFC10
6B1
2
VCC_L
22uFC1
+
0.1uFC24
0.1uFC5
VCC_A
VCC_1.5
FB2
HI1206N101R-00
ferrite_1206
0.1uFC82C76
0.1uF
0.1uFC16
1000pFC17
0.1uFC331000pF
0.1uFC631000pF
C8
1000pF
C301000pF
C57
0.1uFC105 C102
0.1uFC103
1000pFC104
TP7
6B8,7A1,14D1,18A8,26D1,28C1,29C8,31C8,34B8C351.0uF
$V
R50
47.5
1%
100R61
HI1206N101R-00
FB3
C8322uF
+
0.1uFC50
1000pFC81
ferrite_1206
1000pFC770.1uF
C261000pF
VCC_L
C12
1000pFC28C25
0.1uF
0.1uFC41
0.1uFC19
FB1
C970.1uF
C981000pF
0.1uFC27
ferrite_1206
HI1206N101R-00
1000pFC73
C381000pF
C1061000pF
C991000pF
0.1uFC32C43
0.1uF
VCC_3.3
22uFC196
+
1000pFC31
C30.1uF
6B1,21D1
C41000pF 1000pF
C6
C21uF
+
3
13B1
R41 100
0.1uFC78
1000pFC64
C110.1uF
13A8,26C1
13A8,26C1
VCC_L
0.1uFC13
1000pFC14
0.1uFC36
1000pFC74
1000pFC21C37
0.1uFC231000pF0.1uF
C20
C96
+
0.1uFC100
VCC_3.3
C1522uF
+
1uF
5
1000pFC44C107
0.1uF
1000pFC80
1000pFC65C56
1000pF0.1uFC79
1000pFC101
1.0uFC34
C481000pFC49
4
VCC_3.3
C391000pFC40
0.1uF
C12VSSREC_2
VSSREC_3C14
H24VSSREF
0.1uF
G23VDDREC_3
H26VREFN
VREFPH23
J24VSS15_0
VSS15_1K24
G3VSS15_2
VSS15_3F3
VSSPLL15C13
E3VSSPLL33
VSSREC_1D3
D8VDDLD_4
VDDLD_5D9
D10VDDLD_6
VDDLD_7D11
D15VDDLD_8
VDDLD_9D16
D13VDDPLL15
VDDPLL33E4
VDDREC_0D4
D12VDDREC_1
VDDREC_2D14
AC6VDDIO_9
C4VDDLD_0
VDDLD_1D5
D17VDDLD_10
VDDLD_11D18
D19VDDLD_12
VDDLD_13D20
D21VDDLD_14
VDDLD_15D22
D6VDDLD_2
VDDLD_3D7
AC20VDDIO_21
VDDIO_22AC22
AC23VDDIO_23
VDDIO_24AB23
U4VDDIO_3
VDDIO_4W4
AA4VDDIO_5
VDDIO_6AB4
AC4VDDIO_7
VDDIO_8AC5
AC10VDDIO_11
VDDIO_12AC12
L23VDDIO_13
VDDIO_14N23
U23VDDIO_15
VDDIO_16W23
AA23VDDIO_17
VDDIO_18AC14
AC16VDDIO_19
VDDIO_2N4
VDDIO_20AC18
AC21VDDDIG_22
VDDDIG_3P4
R4VDDDIG_4
VDDDIG_5T4
V4VDDDIG_6
VDDDIG_7Y4
AC7VDDDIG_8
VDDDIG_9AC9
VDDIO_0J4
L4VDDIO_1
VDDIO_10AC8
VDDDIG_12
VDDDIG_13M23
P23VDDDIG_14
VDDDIG_15R23
T23VDDDIG_16
VDDDIG_17V23
Y23VDDDIG_18
VDDDIG_19AC15
M4VDDDIG_2
AC17VDDDIG_20
VDDDIG_21AC19
K25TMS
J25TRST
VDD15_0J23
K23VDD15_1
VDD15_2G4
F4VDD15_3
H4VDDDIG_0
VDDDIG_1K4
AC11VDDDIG_10
VDDDIG_11AC13
F23
T2PWDN
REFCLKF2
REF_FILTG25
G26REF_REXT
REG_OUTH25
RESETT1
L25TCK
TDIJ26
K26TDO
U6
cis8204.sys_pwr.3of3.pbga388
CLK125U2
R1MDC
R2MDINT
MDIOP2
PHYADDR2P1
N2PHYADDR3
PHYADDR4N1
PLLMODEF1
R49 100
10B8
VCC_3.3
R65
2K
C751000pF
VCC_L
C290.1uF
0.1uFC591000pF
PWR
PHY_CLK0
GTXCLK125
EPHY_ADR(4:2)
VCC_1.5
C58
NC
NC
NC
MDIO
MDC
IRQ*(11:0)
ENET_RST*
1CM_MAX
1CM_MAX
Revision:
100baseT
Activity
100baseT
Activity
_
freescaleFreescale Semiconductor
semiconductor
TM
ETHERNET PORT #1
7700 W. Parmer LnAustin, Texas 78729
A
B
D
C C
876543
Gary Milliorn1.2
21CDS_Carrier
Ethernet Ports #1 and #211/8/2005
10:26:36 am
2
ETHERNET PORT #2
1 2 3 4 5 6 7
1
A
B
D
Date Changed:
Time Changed:Engineer:
8
Page:Title:Project:
16
8
10b_1
D13
Red
14
15
47pF
10
11
R53
180
22A1
5
6
7
12
C307
Q12
Q25
Q36
Q49
Q512
Q615
Q716
Q819
RST1
20VCCCLK
11
D13
D24
D37
D48
D513
D614
D717
D818
GND10
6B1,20A1
22B1
22A1
22A1
22D1
tssop20
74lvth273
U10
47.5
$VTP9
$VTP12
1%R38 47.5
1%R1
22D1
22D1
$VTP11
$VTP10
16
4
$V TP5
$V TP3
47.5R14 1%
12
13
22D1
22B1
1%R15 47.5
R43 1%
47.5R39 1%
157
1
2
3
4
47.5
4
5
6
7
8
9
S1 S2
L1AD1
D2 L1K
D3 L2A
L2KD4
1
10
2
3
TP13
22A1
22A1
11
12 SHIELD
conn.rj45_cat5_mag_led.ra
J8
R24 47.5
$VTP8
$V
1%R27 47.5
1%
180
1
$V TP6
$V TP4
TP2
$V TP1
R60
47.5R8 1%
$V
1%R10 47.5
47.5R9 1%
47.5R11 1%
1%R13 47.5
1%R12 47.5
14
180
R5947.5R17 1%
47.5R16 1%
13
14
VCC_3.3 VCC_3.3
9
10
R5 1%
47.5R4 1%
R18 47.5
8
9
47.5
47.5R19 1%
1%
15Q6
16Q7
19Q8
1RST
VCC20
0
R169
D413
D514
D617
D718
D8
10GND
2Q1
5Q2
6Q3
9Q4
12Q5
U5
74lvth273
tssop20
11CLK
3D1
4D2
7D3
8
47.5R23 1%
47.5R22 1%
47.5
47.5R55 1%
47.5R26 1%
1%R62
5
6
1%R40 47.5
A24TXVP_D_0
TXVP_D_1A16
TXVP_D_2A8
C2TXVP_D_3
1%R42 47.5
C26TXVP_B_0
TXVP_B_1A20
TXVP_B_2A12
A4TXVP_B_3
TXVP_C_0A26
A18TXVP_C_1
A10TXVP_C_2
TXVP_C_3A2
A23TXVN_D_0
TXVN_D_1A15
TXVN_D_2A7
C1TXVN_D_3
TXVP_A_0E26
A22TXVP_A_1
A14TXVP_A_2
TXVP_A_3A6
C25TXVN_B_0
TXVN_B_1A19
TXVN_B_2A11
A3TXVN_B_3
TXVN_C_0A25
A17TXVN_C_1
A9TXVN_C_2
TXVN_C_3A1
B24TXIP_D_0
TXIP_D_1B16
TXIP_D_2B8
D2TXIP_D_3
TXVN_A_0E25
A21TXVN_A_1
A13TXVN_A_2
TXVN_A_3A5
D26TXIP_B_0
TXIP_B_1B20
TXIP_B_2B12
B4TXIP_B_3
TXIP_C_0B26
B18TXIP_C_1
B10TXIP_C_2
TXIP_C_3B2
B23TXIN_D_0
TXIN_D_1B15
TXIN_D_2B7
D1TXIN_D_3
TXIP_A_0F26
B22TXIP_A_1
B14TXIP_A_2
TXIP_A_3B6
D25TXIN_B_0
TXIN_B_1B19
TXIN_B_2B11
B3TXIN_B_3
TXIN_C_0B25
B17TXIN_C_1
B9TXIN_C_2
TXIN_C_3B1
L2
G1MODE1_0
J1MODE1_1
MODE1_2K1
MODE1_3M2
TXIN_A_0F25
B21TXIN_A_1
B13TXIN_A_2
TXIN_A_3B5
U6
cis8204.ports.1of3.pbga388
DUPLEX_0H2
J2DUPLEX_1
DUPLEX_2L1
M1DUPLEX_3
L26
LED_CLK
M26
LED_DATA
G2MODE0_0
H1MODE0_1
MODE0_2K2
MODE0_3
47.5R2 1%
22B1
47.5R25 1%
2
3
Gb_0
D12
Red
22B1
Red
D11
180
R54
1%R3 47.5
11
Gb_1
R139
0
47pF
C235
47.5
1%R6 47.5
1%R20 47.5
22B1
22B1
1%R7
15
13
1%R21 47.5
8
9
S1 S2
9
10
22B1
22B1
1
10
2
3
4
5
6
7
Red
D14
J6
conn.rj45_cat5_mag_led.ra
SHIELD
D1 L1A
L1KD2
L2AD3
D4 L2K
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
DIFF_PHY DP-1CT1_TXIP_C
10b_0
ENET_LEDS(1:16)
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
T3_TXIN_D
T4_TXIP_A
T4_TXIN_A
T4_TXIP_B
T4_TXIN_B
T4_TXIP_C
T4_TXIN_CT4_TXIP_D
T4_TXIN_D
ENET_RST*
DIFF_PHY DP-1AT1_TXIP_A
T1_TXIN_A DIFF_PHY DP-1A
T3_TXIP_A
T3_TXIN_A
T3_TXIP_B
T3_TXIN_B
T3_TXIP_C
T3_TXIN_C
T3_TXIP_D
1CM_MAX
1CM_MAX
T1_TXIN_B DP-1BDIFF_PHY
T1_TXIN_D DIFF_PHY DP-1D
DIFF_PHY DP-1DT1_TXIP_D
T1_TXIN_C DP-1CDIFF_PHY
DIFF_PHY DP-1BT1_TXIP_B
1CM_MAX
1CM_MAX
DIFF_PHY DP-2BT2_TXIP_B
1CM_MAX
1CM_MAX
DIFF_PHY DP-2CT2_TXIP_C
1CM_MAX
1CM_MAX
DIFF_PHY DP-2DT2_TXIP_D
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
DIFF_PHY DP-2AT2_TXIP_A
T2_TXIN_A DP-2ADIFF_PHY
T2_TXIN_C DIFF_PHY DP-2C
T2_TXIN_D DP-2DDIFF_PHY
T2_TXIN_B DIFF_PHY DP-2B
TM
2 3 5 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
_6 8
7700 W. Parmer LnAustin, Texas 78729
C
A
B
7
D
C
54
freescaleFreescale Semiconductor
32
semiconductor
Gary Milliorn 221.2
CDS_CarrierCarrier-to-IOCard Connector
11/8/2005
10:26:22 am
1
1 4
21C1
VCC_3.3
VCC_5
21B1
21B1
21B1
21B1
21B1
7
21C1
5
21C1
6
21C1
8
0 2
21C1
21C1
2
12A1
B8
B9B9
3
21D1
1
4
2
1
B17B17
B18B18
B19B19
B2B2
B20B20
B3B3
B4B4
B5B5
B6B6
B7B7
B8
A7
A8A8
A9A9
B1B1
B10B10
B11B11
B12B12
B13B13
B14B14
B15B15
B16B16
A16
A17A17
A18A18
A19A19
A2A2
A20A20
A3A3
A4A4
A5A5
A6A6
A7
A1A1
A10A10
A11A11
A12A12
A13A13
A14A14
A15A15
A16
D2
D20D20
D3D3
D4D4
D5D5
D6D6
D7D7
D8D8
D9D9
J7header.5x20.1of3
YFS-20-03-H-05-SB-K
D1
D10D10
D11D11
D12D12
D13D13
D14D14
D15D15
D16D16
D17D17
D18D18
D19D19
D2C2
C2
C20C20
C3C3
C4C4
C5C5
C6C6
C7C7
C8C8
C9C9
D1
C10
C11C11
C12C12
C13C13
C14C14
C15C15
C16C16
C17C17
C18C18
C19C19
E4
E5E5
E6E6
E7E7
E8E8
E9E9
YFS-20-03-H-05-SB-K
header.5x20.2of3
J7
C1C1
C10
E12
E13E13
E14E14
E15E15
E16E16
E17E17
E18E18
E19E19
E2E2
E20E20
E3E3
E4
7B1
6C8
YFS-20-03-H-05-SB-K
header.5x20.3of3
J7
E1E1
E10E10
E11E11
E12
1
0
TP28
TP27
DP_USB1
USB2(0:2)
DIFF_USB
DP_USB2DIFF_USB
DP_USB2
USB1(0:2)
21B1
21B1
21B1
21B1
21B1
12A1
DP-4C
DIFF_PHYT4_TXIP_C
T4_TXIN_CDP-4C
DIFF_PHY
ENET_LEDS(1:16)
DIFF_USB DP_USB1
DIFF_USB
DIFF_PHYT3_TXIP_A
T3_TXIN_A DP-3ADIFF_PHY
DP-3C
DIFF_PHYT3_TXIP_C
T3_TXIN_CDP-3C
DIFF_PHY
DP-4A
DIFF_PHYT4_TXIP_AT4_TXIN_A
DP-4A
DIFF_PHY
DIFF_PHY
DP-3BDIFF_PHYT3_TXIN_B
T4_TXIN_BDP-4B
DIFF_PHY
T4_TXIN_D DP-4DDIFF_PHY
DP-4DDIFF_PHYT4_TXIP_D
DP-3A
NC
NC
EVENT1*
EVENT2*
T3_TXIP_B DP-3B
DP-4B
DIFF_PHYT4_TXIP_B
DP-3D
DIFF_PHYT3_TXIP_D
T3_TXIN_DDP-3D
DIFF_PHY
NC
NC
7700 W. Parmer LnAustin, Texas 78729
C
A
87
Primary Serial Port
SERIAL PORT #2
Secondary Serial Port
1
1
65432
freescale Gary Milliorn 231.2
CDS_CarrierSerial Ports
11/8/2005
10:28:29 am
2 3 4 5 6 7 8
Freescale Semiconductor
semiconductor
TM
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
B
D
SERIAL PORT #1
C
2
13D1
15EN
8GND
SEL1
VCC16
4YA
7YB
9YC
12YD
0
U41
idtqs3vh257.tssop16
A02
A13
5B0
6B1
11C0
10C1
14D0
R4IN10
R4OUT20
12R5IN
18R5OUT
1V+
V-28
VCC2
14VL
VCC_5
$V
16DRVDIS
17
GND NC
15
ON13
6R1IN
24R1OUT
R2IN8
R2OUT22
9R3INR3OUT
21
3C1+
4C1-
C2+26
C2-27
D1IN25
D1OUT5
D2IN23
D2OUT7
D3IN19 11
D3OUT
VCC_5
C1210.1uF
U16
lt1331cg.ssop28
C3160.1uF
VCC_5
YB7
YC9
YD12
1
2
0
3
VCC_3.3
B05
B16
C011
C110
D014
D113
EN15
GND8
1SEL
16VCC
YA4
7 8
9
12A1
$V
idtqs3vh257.tssop16
U19
2A0
3A1
1
10
2
3 4
5 6
21R3OUT
10R4IN
20R4OUT
R5IN12
R5OUT18
V+1
28V-
2VCC
VL14
header.2x5J2
11
DRVDIS16
GND
17 15
NC
13ON
R1IN6
R1OUT24
8R2IN
22R2OUT
R3IN9
lt1331cg.ssop28
C1+3
C1-4
26C2+
27C2-
25D1IN
5D1OUT
23D2IN
7D2OUT
19D3IN D3OUT
0.1uFC329
U47
1
2
3
45
6
7
89
C3270.1uF
12A1
J15conn.db9.plug.rta
0.1uF
VCC_3.3VCC_5
C3140.1uF
C315
C3280.1uF
C1110.1uFC112
VCC_3.3
0.1uF
0.1uFC130
0.1uFC94
3
0
5B8
C1220.1uF
0
1
2
2
1
3
SOUT0
SIN0
CTS0
RTS0
UART2(0:3)
UART1(0:3)
UART_SEL
3
1
VCC_3.3
NC
NC
NC
NC
NC
NC
NC
NC
SHORT_SERIAL
SHORT_SERIAL
SHORT_SERIAL
SHORT_SERIAL
SHORT_SERIAL
SHORT_SERIAL
SHORT_SERIAL
SHORT_SERIAL
NC
NC
NC
NC
NC NC
CTS1 SHORT_SERIAL
SIN1 SHORT_SERIAL
SHORT_SERIALRTS1
SHORT_SERIALSOUT1
NC
NC
A
B
E2
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
_
7700 W. Parmer LnAustin, Texas 78729
8
Gary Milliorn1.2
24CDS_Carrier
CPM Routing for ATM111/8/2005
10:31:33 am
7654
C
A
B
D
C
321
freescaleFreescale Semiconductor
semiconductor
TM
1 2 3 4 5 6 7 8
15
26
27
24
25
13
17
16
15
13
6
0
1
2
9
8
16
15
16
31
12
14
15
15
26
21
2
23
7
4
5
30
13
0
23
21
20
21
22
19
6
12
12
28A1,29A1
25C8,27A1
5A8
1
14
2
0
9
18
21
6
12
11
1010
20
26A1
17
11
10
28
14
12
SEL1
29SEL2
27TEST1
TEST228
VCC114
VCC243
17
14
28
51A4
7A5
A648
10A7
45A8
15A9
13GND1
44GND2
30
18A11
A1237
A1321
34A14
A1524
A1631
54A2
A34
2B46
2B549
2B69
462B7
2B812
412B9
1A1
A1040
382B11
2B1220
352B13
232B14
2B1532
262B16
2B23
2B352
1B45
501B5
81B6
1B747
111B8
421B9
2B155
172B10
1B1139
191B12
1B1336
1B1422
331B15
1B1625
21B2
531B3
TEST127
28TEST2
14VCC1
43VCC2
U21
idtqs3vh16233pa.tssop56
561B1
1B1016
A57
48A6
A710
A845
15A9
GND113
GND244
SEL130
SEL229
37A12
21A13
A1434
24A15
31A16
A254
4A3
A451
492B5
92B6
2B746
122B8
2B941
A11
40A10
A1118
202B12
2B1335
2B1423
322B15
2B1626
32B2
522B3
2B46
1B550
1B68
471B7
1B811
421B9
552B1
2B1017
2B1138
1B1219
361B13
221B14
1B1533
251B16
1B22
1B353
51B4
13
12
idtqs3vh16233pa.tssop56
U18
1B156
161B10
391B11
28B1,29C1
14
6
5
10
12A1,13A1,26A1
25C8,26A1
14
9
24
7
13
28D1,29B1
28B1,29C1
28A1,29C1
21
19
30
17
1
0
15
6
22
19
24
23
30
SEL229
TEST127
28TEST2
14VCC1
43VCC2
29
3
5
A451
A57
48A6
A710
A845
A915
GND113
GND244
SEL1
A1118
37A12
21A13
A1434
24A15
31A16
A254
4A3
62B4
492B5
92B6
2B746
122B8
2B941
A11
40A10
2B1138
202B12
2B1335
2B1423
322B15
2B1626
32B2
522B3
51B4
1B550
1B68
471B7
1B811
1B942
552B1
2B1017
391B11
1B1219
361B13
221B14
1B1533
251B16
1B22
1B353
28D1,29A1
15
14
idtqs3vh16233pa.tssop56
U8
1B156
161B10
15
14
7
6
20
14A1,15A1,25A1,26A1
14A1,15A1,25A1,27A1
24
23
11
28
25
22
8
28
25
13
C460.1uF
8
31
16
28A1,29B1
28D1,29B1
28A1,29B1
28A1
27
1
11
10
27
26
10
0.1uFC131
21
20
19
28C1,29C1
28C1,29C1
28A1
28B1,29D1
VCC_3.3
C1550.1uF
4
3
2
9
8
18
22
29
25
7
5
C850.1uF
0R112
0.1uFC67
VCC_3.3
0.1uFC124
XPA(10:31)
UTCOM
UTCOM
UTCOM
XPC(1,4,6:17,19,21:22)
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
XPD(5:6,14:17,20:28,30:31)
27
26
VCC_3.3
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
ATM1
ATM1
ATM1
ATM1_RXADD(2:0)
ATM1_SEL
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
ATM1_TXSOCATM1
ATM1_TXCLKATM1
ATM1_RXCLAVATM1
ATM1_RXCLKATM1
ATM1
ATM1
ATM1_TXADD(2:0)
ATM1
PC(0:31)
PA(0:31)
PD(4:31)
ATM1
ATM1
ATM1_RXDATA(15:0)
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1_TXENB*ATM1
ATM1_TXPRTYATM1
ATM1_TXCLAVATM1
ATM1_RXSOCATM1
ATM1_RXPRTYATM1
ATM1_RXENB*ATM1
ATM1_TXDATA(15:0)
ATM1
ATM1
ATM1
ATM1
ATM1
ATM1
76
E8
51
1 52
freescaleFreescale Semiconductor
C
semiconductor
TM
3 4 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
_2
E3
3
7700 W. Parmer LnAustin, Texas 78729
8
Gary Milliorn1.2
25CDS_Carrier
CPM Routing for ATM2 and FastEthernet11/8/2005
10:32:02 am
4
C
A
B
D
C1230.1uF
14A1,15A1,24A1,27A1
7
6
0.1uFC84
13
GND244
SEL130
SEL229
TEST127
28TEST2
14VCC1
43VCC2
C450.1uF
A254
4A3
A451
A57
A648
A710
A845
A915
GND1
A11
40A10
A1118
37A12
21A13
A1434
24A15
31A16
32B2
522B3
62B4
492B5
92B6
2B746
122B8
2B941
552B1
2B1017
2B1138
202B12
2B1335
2B1423
322B15
2B1626
1B22
1B353
51B4
1B550
1B68
471B7
1B811
1B942
1B156
161B10
391B11
1B1219
361B13
221B14
1B1533
251B16
31C1
31C1
31D1
19D8
idtqs3vh16233pa.tssop56
U20
15
14
22
6
7
C1540.1uF
10
13
0
1
2
TEST127
28TEST2
14VCC1
43VCC2
5A8
19
4
9
A57
48A6
A710
A845
15A9
GND113
GND244
SEL130
SEL229
37A12
21A13
A1434
24A15
31A16
A254
4A3
A451
492B5
92B6
2B746
122B8
2B941
A11
40A10
A1118
202B12
2B1335
2B1423
322B15
2B1626
32B2
522B3
2B46
1B4
1B550
1B68
471B7
1B811
421B9
552B1
2B1017
2B1138
1B11
1B1219
361B13
221B14
1B1533
251B16
1B22
1B353
5
21
VCC_3.3
idtqs3vh16233pa.tssop56
U17
1B156
161B10
39
VCC_3.3
16
17
4
1
30
24
12
11
10
0.1uFC66
814
0.1uFC137
23
26A1
5A8
25
4
5
0
17
12A1,13A1,26A1
10
5
4
3
17
23
16
2
8
0
16
20
6
4.7K
R103 L
10
31B1
31B1
31B1
R95
4.7K
L L
21
R96
4.7K
L
44GND2
30SEL1
29SEL2
27TEST1
TEST228
VCC114
VCC243
R82
4.7K
A2
A34
51A4
7A5
A648
10A7
45A8
15A9
13GND1
A1
A1040
18A11
A1237
A1321
34A14
A1524
A1631
54
2B352
2B46
2B549
2B69
462B7
2B812
412B9
1
172B10
382B11
2B1220
352B13
232B14
2B1532
262B16
2B23
1B2
531B3
1B45
501B5
81B6
1B747
111B8
421B9
2B155
1B1
1B1016
1B1139
191B12
1B1336
1B1422
331B15
1B1625
2
L
27
30
U7
idtqs3vh16233pa.tssop56
56 2
23
VCC_3.3
18
R84
4.7K
20
24D8,27A1
19
29
19
1
1
R111
13
24D8,26A1
11
19
5
6
7
31
1
0
22
9
8
17
21
20
9
21
15
16
13
24
23
30
2
3
2
1
11
31C1
17
31
25
20
22
14
31A1
31A1
31B1
18
14
7
31B1
29
30
24
25
26
0
15
17
14
15
16
15
4
9
11
18
27
26
1
0
31
24
31
12
23
10
3
7
R94
4.7K
L
11
L
5
5
4
20
31D1
16
14A1,15A1,24A1,26A1
4
4.7K
R92
VCC_3.3
31C1
19
4.7K
R83 L
16
25
22
4.7K
R93 L
21
9
24
21
12
17
PC(0:31)
UTCOMUTCOM
UTCOM
22
31C1
21
6
TSEC4
PD(4:31)
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
FE_SEL TSEC4(0:24)
TSEC4
TSEC4
TSEC4
TSEC4
TSEC4
PB(4:31)
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOMUTCOM
XPD(5:6,14:17,20:28,30:31)
XPB(4:27,29:31)
XPC(1,4,6:17,19,21:22)
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
UTCOM
ATM2_RXSOCATM2 ATM2_RXENB*ATM2 ATM2_RXPRTYATM2 ATM2_RXCLAVATM2 ATM2_RXCLK
UTCOM
UTCOM
UTCOM
ATM2_SEL
ATM2
ATM2_TXSOC
ATM2
ATM2_TXENB*
ATM2
ATM2_TXPRTY
ATM2
ATM2_TXCLAV
ATM2
ATM2_TXCLK
ATM2
ATM2
ATM2
ATM2
ATM2
ATM2
ATM2
ATM2
ATM2
ATM2_RXADD(2:0)
ATM2_TXADD(2:0)
ATM2_RXDATA(7:0)ATM2_TXDATA(7:0)
ATM2
ATM2
ATM2
ATM2
ATM2
ATM2
ATM2
ATM2
ATM2
ATM2
ATM2
ATM2
ATM2
ATM2
1
1 2 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:freescale
Freescale Semiconductor
semiconductor
TM
4
7700 W. Parmer LnAustin, Texas 78729
C
A
B
D
C
876532
Gary Milliorn 261.2
CDS_CarrieruTCOM Connector (part I)
11/8/2005
10:32:45 am
3 4 5
25
26
15
14A1,15A1,24A1,25A1
19
18
17
16
3
1
16
21
D5
D6
D7
D8
D9
VCC_3.3
4
D35
D36
D37
D38
D39
D4
D40
D28
D29
D3
D30
D31
D32
D33
D34
D20
D21
D22
D23
D24
D25
D26
D27
D12
D13
D14
D15
D16
D17
D18
D19
D2
C6
C7
C8
C9
D1
D10
D11
C34
C35
C36
C37
C38
C39
C4
C40
C5
C27
C28
C29
C3
C30
C31
C32
C33
C2
C20
C21
C22
C23
C24
C25
C26
C13
C14
C15
C16
C17
C18
C19
18
2
J3conn.megarray.10x40.2of5
74390-001FCI
C1
C10
C11
C12
14
15
3
6
31 30
31
7C8,14D8,34D1
0
14
6C1,7A1,14A8,34C1
12A1,13A1,24A1
17
29
30
11
25
7
5B1,7A1,10A1,14C1
1
7
6
4
4
5
13
24D8
5A1,7B8,11A8
9
8
26
24
13
21
12
6
7
6B8,7A1,14D1,18A8,20A1,28C1,29C8,31C8,34B8
7B1,14D1
3
22
2929
10
0
F40
F5
F6
F7
F8
F9
28
F34
F35
F36
F37
F38
F39
F4
F27
F28
F29
F3
F30
F31
F32
F33
F19
F2
F20
F21
F22
F23
F24
F25
F26
F11
F12
F13
F14
F15
F16
F17
F18
E5
E6
E7
E8
E9
F1
F10
E33
E34
E35
E36
E37
E38
E39
E4
E40
E26
E27
E28
E29
E3
E30
E31
E32
E2
E20
E21
E22
E23
E24
E25
E12
E13
E14
E15
E16
E17
E18
E19
11
24
J3
conn.megarray.10x40.3of5
74390-001FCI
E1
E10
E11
20
21
22
12
10
12A1,13A1,25A1
25
25C8
18
19
28
27
7C1,15D8,34C1
14A8,34B1
27
28
3
4
VCC_3.3 VCC_3.3
4
5
15
1
14
13
11
12
5A1,7B8,11A8
30
VCC_3.3
15D8,34C1
0
1
2
22
23
16
20
5
7B1
17
5
23
26
27
VCC_5
8
7
8
9
10
VCC_3.3
9
24D8,25C8
6
7
19
23
0
7B8,8B1
31
24
5
6
13A8,20A1
13A8,20A1
20
B4
B40
B5
B6
B7
B8
B9
2
B32
B33
B34
B35
B36
B37
B38
B39
B25
B26
B27
B28
B29
B3
B30
B31
B19
B2
B20
B21
B22
B23
B24
B10
B11
B12
B13
B14
B15
B16
B17
B18
A40
A5
A6
A7
A8
A9
B1
A33
A34
A35
A36
A37
A38
A39
A4
A26
A27
A28
A29
A3
A30
A31
A32
A19
A2
A20
A21
A22
A23
A24
A25
A11
A12
A13
A14
A15
A16
A17
A18
XPB(4:27,29:31)
PA(0:31)PB(4:31)
PC(0:31)
XPC(1,4,6:17,19,21:22)
2
J3conn.megarray.10x40.1of5
74390-001FCI
A1
A10
LB_LALE
MDIOMDC
XPA(10:31)
NC
NC
NC
NC
DEFAULT_NET_TYPE
IRQ*(11:0)
CFGDRV*
LB_WE*(0:3)
LB_LBCTL
NC
NC
NC
NC
NC
NC
NC
NC
NC NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SDA
LB_GPL(0:5)
uTCOM_RST*
CFGRST*
LB_CS*(0:7)
NC
NC
DEFAULT_NET_TYPEDEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
DEFAULT_NET_TYPE
NC
NC
NC
NC
NC
NC NC
NC
NC
NC
SCL
PWRGD_OVDD
NC
NC
NC
NC
NC
NC
NC
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:freescale
Freescale Semiconductor
semiconductor
TM
2 3
7700 W. Parmer LnAustin, Texas 78729
Gary Milliorn 271.2
CDS_CarrieruTCOM Connector (part II)
11/8/2005
10:32:59 am
8765
C
A
B
D
C
4321
1 4 5 6 7 8
A
16
26
2
21
14
15
8
11
12
31
24D8,25C8
VCC_5 VCC_5
7
8
9
13
4
31
6B1,7A1,14C8,15D8
3
16
17
18
29
9
6
5
30
12
9C8
19
20
23
22
K38
K39
K4
K40
K5
K6
K7
K8
K9
K31
K32
K33
K34
K35
K36
K37
K23
K24
K25
K26
K27
K28
K29
K3
K30
K17
K18
K19
K2
K20
K21
K22
J9
K1
K10
K11
K12
K13
K14
K15
K16
J39
J4
J40
J5
J6
J7
J8
J30
J31
J32
J33
J34
J35
J36
J37
J38
J24
J25
J26
J27
J28
J29
J3
J16
J17
J18
J19
J2
J20
J21
J22
J23
J3
J1
J10
J11
J12
J13
J14
J15
10
5
6
17
FCI 74390-001
conn.megarray.10x40.5of5
28
7
8
9
27
28
29
30
27
4
14A1,15A1
25
26
21
22
23
21
17
18
18
19
20
14A1,15A1,24A1,25A1
15
22
23
24
27
28
29
30
13
24
14
15
7C8,14D8,15D8,28D1,29C8,31C8,33D1,34A8
16
0
1
VCC_5 VCC_5
25
14
6
7
10
31
12
13
0
1
2
11
24
25
26
H40
H5
H6
H7
H8
H9
5
H33
H34
H35
H36
H37
H38
H39
H4
H26
H27
H28
H29
H3
H30
H31
H32
H19
H2
H20
H21
H22
H23
H24
H25
H11
H12
H13
H14
H15
H16
H17
H18
G40
G5
G6
G7
G8
G9
H1
H10
G33
G34
G35
G36
G37
G38
G39
G4
G26
G27
G28
G29
G3
G30
G31
G32
G19
G2
G20
G21
G22
G23
G24
G25
G11
G12
G13
G14
G15
G16
G17
G18
3
4
FCI 74390-001
conn.megarray.10x40.4of5
J3
G1
G10
PD(4:31)
19
20
11
10
CX(0:31)
XPD(5:6,14:17,20:28,30:31)
LB_D(0:31)
LB_A(0:31)
NC
NC
NC
NC
NC
NC
UTCOM_LBCLK
NC
NC
NC NC
NC
NC NC
NC
TM
7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
C
Austin, Texas 787297700 W. Parmer Ln
A
B
D
C
8765
Gary Milliorn 281.2
CDS_CarrierFCC1/ATM1: AdTech Adapter Connector
11/8/2005
10:33:28 am
31
1
42
ADTECH RX
Place and Group Connectors per spec
2
ADTECH TX
3 4 5 6
freescaleFreescale Semiconductor
semiconductor
1
0
6B1,7B1,29D8,31D8,33B1,34B17
6
5
10
13
15
9
7C1
7B8,29C8,31C8,33B1,34B1
14
0
VCC_3.3
0
1
2
1
0
7C8,14D8,15D8,27D1,29C8,31C8,33D1,34A8
3
4
6
VCC_3.3
7
2
5
7
8
3
24C8,29C1
24A8,29C1
24C8,29C1
24C8,29C1
10
12
14
24C8
24C8,29A1
24A8,29A1
6
5
4
24C8,29B1
24C8,29B1
3
4
6
9
24C8,29C1
24C8,29D1
11
12
2
5
7
8
24C8,29B1
24C8,29B1
3
2
1
11
7C8,29C8,31C8,33B1,34B1
6B8,7A1,14D1,18A8,20A1,26D1,29C8,31C8,34B8
6
2
10
13
15
1
4
39
4
40
5 6
7 8
9
30
31 32
33 34
35 36
37 38
23 24
25 26
27 28
29
3
16
17 18
19
2
20
21 22G4
1
10
11 12
13 14
15
6
7 8
9
QSE-020-01-L-D-A
J5
G1
G2
G3
35 36
37 38
39
4
40
5
28
29
3
30
31 32
33 34
20
21 22
23 24
25 26
27
13 14
15 16
17 18
19
2
QSE-020-01-L-D-A
G1
G2
G3
G4
1
10
11 12
LB_D(0:31)
ATM1_RST*ATM1X_CS*
LB_RD*LB_WR*
ATM1_RXADD(2:0)ATM1_TXADD(2:0)
ATM1_RXCLK
2
7C1,29C8
0
24C8
J4
NC
NC
NC
ATM1_RXENB*
NC
NC
ATM1_TXPRTY
NC NC
ATM1_TXCLAV
ATM1_TXENB*
ATM1_TXDATA(15:0)
ATM1_TXSOC
ATM1_RXPRTY
ATM1_RXCLAV
ATM1_RXDATA(15:0)
CLA(23:0)
IRQ*(11:0)
ATM1_RXSOC
ATM1_TXCLK
6
7700 W. Parmer LnAustin, Texas 78729
C
A
B
421
1 2
CDS_CarrierFCC1/ATM1: 622 Mbps Interface
11/8/2005
10:31:48 am
D
3
freescaleFreescale Semiconductor
semiconductor
TM
3 4 5 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
_5
C
87
Gary Milliorn 291.2
9
10
4
2
3
1
0
1
2
24C8,28D1
16V
C6910uF
+
1%
R120
301
2
4.7KR143
1%
R98
301
2
1
49.9
R86
1%
VCC_3.3
C211 47pF
3
7
R115 4.7K
4.7KR141
24C8,28C1
24C8,28A1
15
R142 4.7K
14
24C8,28A1
24C8,28D1
6B1,7B1,28B1,31D8,33B1,34B1
1
0
3
24C8,28B1
C217
0.1uFC227
R155 4.7K
0.1uF
4
7TXDn
8TXDp
VCCR
5 6
VCCT
1
VEER
VEET
9
7B8,28C1,31C8,33B1,34B1
VCC_3.3
4
24A8,28A1
HFBR-5208MU12
EGND1
10 11
EGND2
RXDn3
2RXDp
SD
5
8
TP14
TP15
6
4.7KR157
6
0
VCC_3.3
0
14
8
7
6
7
TP29
R156 4.7K
0
13
0R158
301
R113
1%
6B8,7A1,14D1,18A8,20A1,26D1,28C1,31C8,34B8
R114
15
1%
R87
49.9
FB4
HI1206N101R-00
1
3OUTp4 V3.3V
0.1uFC153
6
R66
No_Stuff
4
U22
E13W1F2C-77.760M
77.760MHz
GND2
OUTn
5B8
R67 0
0
R68 0
R63 0
VCC_3.3
0R56
GND1
GND212
1REF
S19
8S2
VDD14
13VDD2
C530.1uF
MPC962308DT-1H
8.435 4.476 1 0 IN 21424900 11369040
CLKA12
3CLKA2CLKA3
14
15CLKA4
6CLKB1
CLKB27
10CLKB3
CLKB411
FBK16
5
R97
1%
9
10$V
U9
L2TXDp
A11WR
330R79
301
TLD
TLDCLKC19
K23TMOD
D10TMS
L20TPRTY
B9TRST
C20TSD
TSDCLKB20
L21TSOC
TXDnL1
C10
C9TDO
K1TDREF0
TDREF1K2
TENBL22
TEOPE22
TERRD23
TFCLKM22
TFPIA21
TFPOA20
D19
TDAT2
TDAT3J23
J22TDAT4
TDAT5J21
H22TDAT6
TDAT7H21
H20TDAT8
TDAT9G23
TDI
TDAT0
TDAT1K21
G22TDAT10
TDAT11G21
G20TDAT12
TDAT13F22
F21TDAT14
TDAT15E23
K20
B10
N21RVAL
V2RXDn
RXDpW1
R2SD
SYSSELAA23
TCAL23
TCKA9
B19TCLK
K22
AB19
AA20RLD
RLDCLKY19
RMODY23
RPRTYP21
U2RRCLKn
RRCLKpU1
AC21RSD
RSDCLKAB20
RSOCP23
RSTU23
RDAT8
RDAT9T20
REFCLKnAA1
Y2REFCLKp
N23RENB
P22REOP
N22RERR
M21RFCLK
RFPO
R23RDAT14
RDAT15P20
W23RDAT2
RDAT3V21
V22RDAT4
RDAT5U20
U21RDAT6
RDAT7U22
AC20RCLK
RDB11
W21RDAT0
RDAT1W22
T21RDAT10
RDAT11T22
R21RDAT12
RDAT13R22
POUT1
POUT2
AC13
AB13
POUT3
POUT4
AA13
Y13
POUT5
AB12
POUT6
POUT7
AA12
Y14PTCLK
RALRMAA19
RBYPE21
RCAN20
AC19
AB18
PIN0
PIN1
AA17
AB16
PIN2
PIN3
AA16
Y16
PIN4
PIN5
AC15
PIN6
AB15
AA15
PIN7
POS_ATMBY21
POUT0
AA14
AB14
B15
A15D6
D7D14
AB17
FPIN
AC14
FPOUT
C14INT
C23LIFSEL
OOFAA18
D22PECLV
PICLK
F3
C0P3
P2C1
C11CS
B17D0
D1A17
C16D2
D3B16
C15D4
D5
A7B12
D11A8
ALEA10
A19APS0
APS1C18
B18APS2
APS3D17
C17APS4
E2ATP0
ATP1 PM5357-B1
B14A0
A1A14
D13A2
A3C13
B13A4
A5A13
C12A6
1%R107 158
U23
pm5357.main.1of3.sbga304
2.00K
7C8,14D8,15D8,27D1,28D1,31C8,33D1,34A8
158R106 1%
11
1%
R110
301
1%R131
C700.1uF
220R78
24C8,28B1
24A8,28A1
11
12
13
VCC_3.3
24C8,28B1
6
R118
7
8
12
24C8,28D1
7C1
7C1,28C1
5B8
5
4.7K
0.1uFC115
7C8,28D1,31C8,33B1,34B1
HI1206N101R-00
FB5
3
4
5
VCC_3.3
TP30
5
0.1uFC113 C114
0.1uF
ATM_RTCLK
ATM_RTCLK
ATM1_RXCLK
ATM1_TXCLK
1CM_MAX ATM_RTCLK
ATM1_RST*
DIFF_FIB
FIB1RDIFF_FIB
ATM1CLK ATM1CLK
SHORT
SHORT
SHORT
SHORT
ATM1CLK ATM1CLK
NC
ATM1_TXDATA(15:0)
ATM1_RXDATA(15:0)
ATM1_RXCLAV
NC
NC
NC
NC
NC
NC
NC
ATM1_16BIT*
DIFF_SERIES
FIB1T2
DIFF_SERIES
FIB1T2
SHORT_POWER
IRQ*(11:0)
NC
NC
LB_RD*
LB_WR*
LB_D(0:31)
CLA(23:0)
NC
NC
NC
NC
DIFF_SERIESFIB1T1
FIB1T3DIFF_SERIES
FIB1T3DIFF_SERIES
DIFF_SERIES
FIB1T1
AREA_FILL
AREA_FILL
ATM1_TXSOC
ATM1_TXENB*
ATM1_TXPRTY
ATM1_TXCLAV
ATM1_RXSOC
ATM1_RXPRTY
ATM1_RXENB*
ATM1_CS*
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
FIB1R
NC
B
C
7700 W. Parmer LnAustin, Texas 78729
C
A
7654321
1
CDS_CarrierFCC1/ATM1:PHY Power
11/8/2005
10:33:14 am
2 3 4 5 6 7 8
A
B
D
Revision:Page:Title:
Date Changed:
Time Changed:Engineer:
Project:
_8
freescaleFreescale Semiconductor
semiconductor
SENSITIVE POWER FILTERS’Capacitors without VCC_3.3V resistors
MUST be placed near corresponding power pad.
TM
D
Gary Milliorn1.2
30
C256
15R145 1%
VCC_3.3
10uFC255
0.1uF
C2020.1uF
C2240.1uF 0.1uF
C2150.1uFC223
C1870.1uF
C2410.1uF 0.1uF
C240
0.1uFC185C183
0.1uFC1840.1uF 0.1uF
C186
VSS6
VSS7AA2
AA22VSS8
VSS9AB1
0.1uFC182
H1
VSS3A12
H23VSS30
VSS31M1
M23VSS32
VSS33T1
T23VSS34
VSS35V1
V23VSS36
A16VSS4
VSS5A18
A22
A8VSS2
B1VSS20
VSS21B3
B21VSS22
VSS23B23
C2VSS24
VSS25C22
D21VSS26
VSS27F1
F23VSS28
VSS29
A6
AB3VSS10
VSS11AB21
AB23VSS12
VSS13AC2
AC6VSS14
VSS15AC8
AC12VSS16
VSS17AC16
AC18VSS18
VSS19AC22
B4
D5AVS39
G2AVS4
AVS5G1
H2AVS6
AVS7J3
J1AVS8
AVS9L4
QAVS0D1
P4QAVS1
A2VSS0
VSS1
AB9AVS29
AVS3H4
AVS30AA10
AC10AVS31
AVS32A7
B7AVS33
AVS34A5
D7AVS35
AVS36C6
C5AVS37
AVS38
AVS19
G3AVS2
AVS20Y5
AB4AVS21
AVS22AC4
AA6AVS23
AVS24Y7
AB6AVS25
AVS26Y8
AC7AVS27
AVS28AB8
AVS0
AVS1C1
M3AVS10
AVS11N1
N2AVS12
AVS13N3
N4AVS14
AVS15T2
T3AVS16
U4AVS17
AVS18W4
Y3
C2420.1uF
PM5357-B1pm5357.vss.3of3.sbga304
U23
E4
1K
R117
C225
VCC_3.3
VCC_3.3
0.1uFC188
16V
C132
47uF
+
0.1uF
4.7
C2260.1uF
0.1uFC203
C1160.1uF
1%R99
C11710uF
0.1uFC216
15R160 1%
10uFC302 C283
0.1uFC28210uF
C2990.1uF
0.1uFC276
1%R159 15
C1500.1uF
C151
0.1uFC301C300
C29810uF
0.1uF
4.7
C1520.1uF
10uF
VDD33Y15
Y18VDD34
VDD35Y20
AB2VDD4
VDD5AB22
AC1VDD6
VDD7AC23
B2VDD8
VDD9B22
1%R149
M4
M20VDD24
VDD25R4
R20VDD26
VDD27V4
V20VDD28
VDD29Y4
VDD3AA21
Y6VDD30
VDD31Y9
Y12VDD32
D6
D9VDD14
VDD15D12
D15VDD16
VDD17D18
D20VDD18
VDD19F4
AA3VDD2
F20VDD20
VDD21J4
J20VDD22
VDD23
PBIAS3
E3QAVD0
QAVD1R1
VBIAS0W20
E20VBIAS1
A1VDD0
VDD1A23
C3VDD10
VDD11C21
D4VDD12
VDD13
AVD31C4
AVD4J2
K4AVD5
AVD6K3
L3AVD7
AVD8P1
T4AVD9
W2PBIAS0
PBIAS1V3
PBIAS2R3
M2
AVD21
AVD22Y10
AC9AVD23
AVD24AB10
D8AVD25
AVD26C7
B6AVD27
AVD28B5
AVD29A4
H3AVD3
A3AVD30
AVD11
AVD12W3
AA4AVD13
AVD14AC3
AA5AVD15
AVD16AB5
AC5AVD17
AVD18AA7
AB7AVD19
AVD2F2
AVD20AA8
AA9
PM5357-B1
pm5357.vdd.2of3.sbga304
U23
AVD0D3
D2AVD1
AVD10U3
Y1
SHORT_POWER
C2430.1uF
R144 100
SHORT_POWER
SHORT_POWER
SHORT_POWER
SHORT_POWER
SHORT_POWER
SHORT_POWER
65
1 2 3 4 5 6 7 8
A
freescaleFreescale Semiconductor
semiconductor
TM
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
_7 8
7700 W. Parmer LnAustin, Texas 78729
C
A
B
D
C
Gary Milliorn 311.2
CDS_CarrierATM2: 155Mbps Interface
11/8/2005
10:32:17 am
4321
0.1uFC231
VCC_3.3
R74
No_Stuff
R73 0
0R85
0
R105 0
0R104
9S1
S28
4VDD1
VDD213
0.1uFC68
VCC_3.3
3
14CLKA3
CLKA415
CLKB16
7CLKB2
CLKB310
11CLKB4
16FBK
GND15
12GND2
REF1
VCC_3.3
$V
8.989 4.301 2 270 IN 22832060 10924540
MPC962308DT-1H
U11
2CLKA1
CLKA2
100R132
R137 100
R102
150
7C1
7B8,28C1,29C8,33B1,34B1
7C8,28D1,29C8,33B1,34B1
TP16
150
R100
1%1%
3
4
5
6
1%
R101
150
1
0R134
6B8,7A1,14D1,18A8,20A1,26D1,28C1,29C8,34B8
5
25C8
25C8
25C8
25A80
0
1
4
5
6
7
7C8,14D8,15D8,27D1,28D1,29C8,33D1,34A87
6
0
1
2
3
4
7
0
0
1
2
R126
+0.1uFC125
5
6
8
9
0
VCC_3.3
16V
C6010uF
C710.1uF
7
49.9
R88
1%1%
R89
49.9
FB6
HI1206N101R-00
0.1uFC219 1%R109 158
330R81
VCC_3.3
158R108 1%
6
VCCT
1
VEER
VEET
9
220R80
EGND1
10 11
EGND2
RXDn3
2RXDp
SD4
7TXDn
8TXDp
VCCR
5
L8
TTOHCLK
K7
K8
TTOHEN
L7
TTOHFP
TXDnF2
F1TXDp
B2WR
G9XOFF
HFBR-5805U13
TMOD
L2TMS
L5
TPOH
TPOHCLK
L6
TPOHEN
M5
K6
TPOHFP
E9TPRTY
L4TRST
F7TSEN
E14TSOC
TTOH
TDCC
TDCLKN1
TDIL3
M2TDO
TENBC13
TEOPD14
TERRC12
TFCLKF14
TFPIP7
TFPOM9
D11
B13TDAT2
TDAT3A14
A13TDAT4
TDAT5A12
B12TDAT6
TDAT7A11
B11TDAT8
TDAT9C11
M1
TCKM3
P8TCLK
C14TDAT0
TDAT1B14
A10TDAT10
TDAT11D10
A9TDAT12
TDAT13B9
C9TDAT14
TDAT15D9
E4SDTTL
SPECLVJ6
E11STPA
E13TADR0
TADR1E12
TADR2F11
F10TADR3
TADR4F9
TCAE10
RSOCJ10
RSTB3
P6
RTOH
N5
RTOHCLK
RTOHFP
P5
L14RVAL
H2RXDn
RXDpH1
H3SD
J14RENB
J12REOP
J13RERR
G14RFCLK
RFPON9
RMODK14
RPOH
P4
RPOHCLK
P3
P2
RPOHFP
RPRTYJ11
L10RDAT4
RDAT5K10
P11RDAT6
RDAT7N11
M11RDAT8
RDAT9L11
N2RDCC
RDCLKP1
K1REFCLK
RDAT0
RDAT1K9
P12RDAT10
RDAT11P13
M14RDAT12
RDAT13M13
L13RDAT14
RDAT15L12
J9RDAT2
RDAT3P10
G11
G10RADR1
RADR2H14
H11RADR3
RADR4H10
RALRML1
RCAK11
P9RCLK
RDA3
L9
D2
D3A7
B7D4
D5C7
D7D6
D7E7
C3INT
POS_ATMBJ8
RADR0
ALEA4
J5APECLV
J2APSIn
APSIpJ1
D2APSOn
APSOpD1
A2CS
A8D0
D1D8
E8
D6A2
A3A6
E5A4
A5D5
C5A6
A7B5
A5A8
A9D4
25A8
25A8
U25
pm5384.main.1of2.stpbga196
PM5384NI
F6A0
A1E6
3
2
1
0.1uFC218
R147 0
4
5B8,7C1
7C1
2
6
0R133
2
25A8
25A8
25A8
25A8
25C8
25A8
25C8
25C8
HI1206N101R-00
FB7
VCC_3.3
0
VCC_3.3
4 V3.3V
0.1uFC118 C119
0.1uF
100
U27
19.440MHz
GND2 1
OE
OUT 3
6B1,7B1,28B1,29D8,33B1,34B1
1
2
3
R121
LB_RD*
LB_WR*
LB_D(0:31)
CLA(23:0)
ATM_RTCLK
1CM_MAX
NC
NC
NC
NC
ATM_RTCLK
NC
ATM_RTCLK
ATM2_RXDATA(7:0)
ATM2_TXADD(2:0)
ATM2_RXADD(2:0)
IRQ*(11:0)
NC
NC
NC
ATM2_RST*
ATM2_EN*
ATM2_CS*
DIFF_SERIES FIB2T3
DIFF_SERIES FIB2T3
SHORT
AREA_FILL
SHORT
NC
SHORT
ATM2_TXDATA(7:0)
DIFF_SERIES
FIB2T1
DIFF_SERIES
FIB2T1
AREA_FILL
DIFF_FIB FIB2R
DIFF_SERIES
FIB2T2
DIFF_SERIES
FIB2T2
SHORT_POWER
DIFF_FIB FIB2R
NC
NC
NC
NC
ATM2_TXENB*
ATM2_TXCLK
NC
NC
NC
ATM2_TXPRTY
ATM2_TXSOC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
ATM2_RXPRTY
ATM2_RXSOC
NC
NC
NC
NC
ATM2_TXCLAV
ATM2_RXENB*
ATM2_RXCLK
SHORT
NC
NC
NC
ATM2_RXCLAV
NC
NC
NC
NC
NC
NC
NC
NC
Title:Project:
Austin, Texas 78729
C
A
B
D
C
876521
1 2 3 4
freescaleFreescale Semiconductor
semiconductor
TM
5 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Gary Milliorn 32
1.2
CDS_CarrierFCC2/ATM2: PHY Power
11/8/2005
10:32:32 am
_3 4
7700 W. Parmer Ln
0.1uF 0.1uFC168C167
0.1uFC164
C2040.1uFC166
C2640.1uF
C1890.1uF 0.1uF
C2610.1uFC263
C2460.1uF
C2600.1uF 0.1uF
C2070.1uFC233C262
0.1uFC1910.1uF 0.1uF
C265
0.1uFC259
C2060.1uF
C1900.1uF 0.1uF
C2320.1uFC245
VSSQ0B1
N14VSSQ1
VCC_3.3
C2580.1uF 0.1uF
VSSO18
VSSO19N12
VSSO2B10
N13VSSO20
C2VSSO3
VSSO4D3
D13VSSO5
VSSO6E2
F4VSSO7
VSSO8F13
G2VSSO9
VSSI3
VSSO0B4
B6VSSO1
VSSO10G4
H13VSSO11
VSSO12K2
K13VSSO13
VSSO14N3
N4VSSO15
VSSO16N6
VSSO17N8
N10
E1
E3VDDO6
VDDO7F3
F12VDDO8
VDDO9G1
A1VDDQ0
VDDQ1P14
B8VSSI0
VSSI1G13
VSSI2G5
N7
H12
K3VDDO12
VDDO13K12
M4VDDO14
VDDO15M6
M8VDDO16
M10VDDO17
VDDO18M12
C6VDDO2
VDDO3C10
D12VDDO4
VDDO5
H8THERM_NC5
H9THERM_NC6
THERM_NC7J7
C8VDDI0
VDDI1G12
F5VDDI2
VDDI3M7
C1VDDO0
VDDO1C4
G3VDDO10
VDDO11
AVD0
AVD1H5
K4AVS0
AVS1H4
QAVDJ4
J3QAVS
THERM_NC0F8
G6THERM_NC1
THERM_NC2G7
G8THERM_NC3
THERM_NC4H7
C16210uF
PM5384NI
pm5384.pwr.2of2.stpbga196
U25
ATPH6
K5
0.1uF
1%R116 2.7
VCC_3.3
2.7R138 1%
VCC_3.3
C205
10uFC257
0.1uFC244
VCC_2.5
10uFC165
SHORT_POWER
PWR
0.1uFC163
SHORT_POWER PWR
Title:Project:
D
8
Flash Emulator(PromJet 16NVS)
B
7700 W. Parmer LnAustin, Texas 78729
CC
FLASH BANK 2FLASH BANK 1
7
A
54321
Gary Milliorn 331.2
CDC_CarrierFlash Memory + Flash Emulator
11/8/2005
10:28:57 am
6
2 3 4 5 6 71 8
A
B
D
Date Changed:freescale
Freescale Semiconductor
semiconductor
TM
Time Changed:Engineer:
Revision:Page:
20
21
32DQ9
28OE RESET
12
47VIO
WE11
14WP
11
19
DQ1545
DQ233
DQ335
DQ438
DQ540
DQ642
44DQ7
30DQ8
13
CE26
DQ029
DQ131
34DQ10
36DQ11
39DQ12
41DQ13
43DQ14
A21
A322
A421
A520
A619
18A7
8A8
A97
ACC
2
A151
48A16
A1717
A1816
A1915
A223
10A20
9
am29lv641d.tsop48w
U49
25A0
A124
A106
A115
A124
A133
A14
5
6
15
14
13
10
1
5
4
3
7
19
7
9
6
17
19
22
20
10
11
13
15
16
13
12
9
8
6C8
8
3
VCC_3.3
21
VCC_3.3
4
2
7C8,14D8,15D8,27D1,28D1,29C8,31C8,34A8
23
7C8,28D1,29C8,31C8,34B1
VCC_3.3
4.7K
R191
11
7
0
4
VCC_3.3
R185
4.7K
3
4
5
6
9
10
7C8
6C1
16
15
14
0
5
2
9
8
17
12
15
17
4.7K
R199
VCC_3.3
11
2
10
13
14
6
10
VCC_3.3
7B8,28C1,29C8,31C8,34B1
6B1,7B1,28B1,29D8,31D8,34B1
8
9
2
1111
12
1
3
9
4
VCC_3.3
6
7
14
13
12
20
7
7
18
8
3
2
1
6
15
0
1
116
21
7A8
5
50
6
7 8
9
5
15
42
43 44
45 46
47 48
49
35 36
37 38
39
4
40
41
29
3
30
31 32
33 34
21 22
23 24
25 26
27 28
14
15 16
17 18
19
2
20
8
header_2x25_05sp
J13
1
10
11 12
13
DQ6
DQ744
DQ830
DQ932
OE28 12
RESET
VIO47
11WE
WP 14
39
DQ1341
DQ1443
45DQ15
33DQ2
35DQ3
38DQ4
40DQ5
428
7A9
13ACC26
CE
29DQ0
31DQ1
DQ1034
DQ1136
DQ12
23A2
A2010
A219
22A3
21A4
20A5
19A6
A718
A8
4A12
3A13
2A14
1A15
A1648
17A17
16A18
15A19
4
U54
am29lv641d.tsop48w
A025
24A1
A106
5A11
12
145
18
0
12
3
5R176
2
1014
18
13
0
1
LB_WR*
FLASH0_CS*
LB_D(0:31)
CLA(23:0)
0
R200
4.7K
FLASH1_CS*PJET_CS*
LB_RD*
MEM_RST*
NC
NC
NC
C
B
D
7 84 653
Local Bus NVRAM/Debug Connectors11/8/2005
10:29:11 am
2
1 2
1
4 53 8
freescaleFreescale Semiconductor
semiconductor
A
B
D
TM
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
76
7700 W. Parmer LnAustin, Texas 78729
C
A
Gary Milliorn1.2
34CDS_Carrier
8
7
6
5
4
SCL38
37SDA
18
16
15
14
13
12
11
10
9
31
32
33
34
35
19
18
17
23
24
25
26
27
28
29
30
J16conn.mictor.38
ADDR
3
36
2GROUND
1LA5V
20
21
22
TP45
5
1
16
28
31
4
9
TP43
R192
4.7K
4
27
2
4.7K
R195
31
R196
4.7K
R194
4.7K
0
4.7K
R193
3
2
1
0
6C1,7A1,14A8,26C1
9C8
5
8
7
6
5
4
38SCL
SDA37
VCC_3.3
4
16
15
14
13
12
11
10
9
31
32
33
34
35
19
18
17
24
25
26
27
28
29
30
STAT
3
36
GROUND2
LA5V1
20
21
22
23
2
8
3
2
23
J14conn.mictor.38
1
14D8
0
4.7K
R184
1
R152
4.7K
10
7A8
4.7K
R190
9
3
7B8,12B8
4.7K
R189
5
VCC_3.3
2
11
12
2
7C8
7
2
7B8,12B8
6
1
0
7
4
3
4
12
16
17
07C1,15D8,26D1
7
5
4
TP44
17
7B8,28C1,29C8,31C8,33B1
9
0
7C8,28D1,29C8,31C8,33B1
11
7C8,14D8,15D8,27D1,28D1,29C8,31C8,33D1
8
0
7B8,9D8
1
0
5
6
11
6
7
6B8,7A1,14D1,18A8,20A1,26D1,28C1,29C8,31C8
14
1
22
21
3
19
20
3
6B1,7B1,28B1,29D8,31D8,33B1
1
0
9B8
7C8,14D8,26D1
14A8,26D1
3
2
7
6 7
11
10
R183
4.7K
4
38SCL
SDA37
4.7K
R151
12
11
10
9
8
7
6
5
35
19
18
17
16
15
14
13
26
27
28
29
30
31
32
33
34
2
1LA5V
20
21
22
23
24
25
13
12
DATA
conn.mictor.38
J17
3
36
GROUND
3
2
6
5
15
14
17GND
IRQ_FT1
OE7
4RST
VCC5
6WR
15
13
18
A8
A927
8CE
DQ016
15DQ1
DQ214
13DQ3
DQ412
11DQ5
DQ610
9DQ7
A119
28A10
A1129
30A12
20A2
A321
22A4
A523
24A6
A725
26
8
11
10
15D8,26D1
pcm34
DS1553WP-120
U51
18A0
6
29
30
TP46
23
24
25
26
R136
4.7K
10
4
19
20
21
22
NC
IRQ*(11:0)
LCL_RST*
CLA(23:0)
NC
NC
CDC_SPR1
0
8
9
5
LB_DP(0:3)
NC
NC
LB_RD*
NC
LB_LALE
LA_PCICLK
LB_LACLK
NC
NC
NC
NC
NC
LB_D(0:31)
NC
NVWD_RST*LB_WR*
NVRAM_CS*
NC
NC
NC
LB_LBCTL
NC
NC
NC
LB_CS*(0:7)
LB_WE*(0:3)
CDC_SPR2
NC
LB_GPL(0:5)
7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:
CDS_Carrier--reserved--
11/8/2005
10:29:23 amTitle:
Project:
D
B
7700 W. Parmer LnAustin, Texas 78729
8765
C
A
C
4321
1 2
freescaleFreescale Semiconductor
semiconductor
TM
3 4 5 6
Gary Milliorn 351.2
B
A
7700 W. Parmer LnAustin, Texas 78729
C
D
C
87
10:29:37 am
4 6521 3
Add or subtract based on density.
1 2
GLOBAL BYPASS CAPS.
3 4 5 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:freescale
Freescale Semiconductor
semiconductor
TM Gary Milliorn 361.2
CDS_CarrierBypass Capacitors
11/8/2005
0.1uF
C222 C269
0.1uF0.1uF
C287 C267
0.1uF0.1uF
C88 C89
0.1uF
C201
0.1uF
C181
0.1uF
C248
0.1uF
0.1uF
C149
0.1uF
C324 C345
0.1uF0.1uF
C339 C335
0.1uF
0.1uF
C180
VCC_2.5
VCC_2.5
330uF
C344+
C161
0.1uF
C332+
330uF
C133+
+C254
330uF
+
330uF 330uF
C138+C290
330uF
0.1uF
C326
C61
330uF
+
0.1uF
C319 C342
0.1uF
C142
0.1uF
C110
0.1uF
0.1uF
C294 C288
0.1uF0.1uF
C296 C280
0.1uF 0.1uF
C144C228
0.1uF
0.1uF
C200
C250
0.1uF
0.1uF
C220
C52
330uF
+
C170
0.1uF 0.1uF
C176C172
0.1uF 0.1uF
C171
C295
0.1uF
0.1uF
C173
C95
0.1uF
0.1uF
C279
0.1uF
C322
0.1uF
C323
0.1uF
C42
0.1uF
C321
0.1uF
C51 C195
0.1uF
C338
0.1uF
C177
0.1uF
0.1uF
C313 C108
0.1uF0.1uF
C93 C281
0.1uF
0.1uF
C194
0.1uF
C251
VCC_3.3
C92
0.1uF
0.1uF
C197
C169
0.1uF
0.1uF
C120 C318
0.1uF
C331
0.1uF
C343
C303
0.1uF
C340 C47
0.1uF 0.1uF
C337 C266
0.1uF 0.1uF
C330
0.1uF 0.1uF
+C126
330uF
+
0.1uF
C221
C148
0.1uF
330uF
C139
330uF
+
330uF
C308+
VCC_3.3
C174 C320
0.1uF
C346C325 C336
0.1uF 0.1uF
C333 C341
0.1uF 0.1uF
C143
C334
0.1uF 0.1uF
+
330uF
C140+
0.1uF
C141
0.1uF
C198
330uF0.1uF
C284
0.1uF
C236
0.1uF
C160 C277
0.1uF
VCC_5
0.1uF
C159 C270
0.1uF
C175
0.1uF
CDS Carrier Schematics, Rev. 1.2
MPC8555E Configurable Development System Reference Manual, Rev. 1
D-38 Freescale Semiconductor
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor E-1
Appendix ECDS Carrier BOM, Rev. 1.3This appendix provides CDS Carrier BOM for Rev. 1.3.
Item Number: 750-21600Description: SUB ASSEMBLY, SCHEMATIC PARTS,700-21600.
CARRIER 1.3Item Revision: C ECO13129
Item Description Qty Ref Des Notes1 SUB ASSEMBLY, SCHEMATIC PARTS,700-21600.
CARRIER 1.32 CAP CER 0.01UF 50V 10% X7R 0402 38 C286,C360-C3963 CAP TANT ESR=0.035 OHMS 330UF 10V 20% -- 7343-
4313 C52,C133,C138-C140,C198,C254,C290,C308,C310,C332,C344,C346
4 CAP TANT 10UF 16V 10% -- 6032-28 2 C60,C695 CAP CER 10UF 16V +80%/-20% Y5V 1210 9 C117,C162,C165,C255,C257,C282,C298,C300,C302
6 CAP TANT 22UF 16V 10% -- 6032-28 1 C2857 CAP TANT 47UF 16V 10% -- 7343-31 1 C1328 CAP CER 47PF 50V 5% C0G 0402 1 C2119 CAP CER 0.10UF 16V 10% X7R 0402 238 C8,C16,C25,C27,C36,C39,C41-C43,C45-C48,C50,C51,C53,C57,C58,C66-C68,C70-
C72,C77,C78,C84,C85,C92-C95,C97,C100,C102,C105,C108,C110-C116,C118-C125,C130,C131,C137,C141-C145,C147-C157,C159-C161,C163,C164,C166-C191,C194,C195,C197,C199-C207,C209,C210,C213-C233,C236-C246,C248-C253,C256,C258-C277,C279-C281,C283,C284,C287,C288,C294-C296,C299,C301,C303,C309,C311-C331,C333-C343,C345,C401-C414,C418,C419
10 CAP CER 1000PF 50V 10% X7R 0402 21 C17,C26,C33,C40,C49,C59,C63,C64,C74,C75,C81,C98,C101,C103,C104,C106,C415-C417,C420,C421
11 CAP CER 10UF 16V 10% X5R 0805 7 C353-C35912 CAP CER 1.0UF 10V +80%/-20% Y5V 0603 5 C34,C35,C128,C129,C13413 CAP ALEL 220UF 4.0V 20% -- 7343 14 C62,C86,C87,C127,C136,C146,C192,C212,C278,C289,C291,C292,C297,C306
14 CAP TANT LOW ESR 22UF 6.3V 10% 0805 7 C83,C196,C347-C35115 CAP TANT LOW ESR 68UF 25V CASE D 2 C352,C42216 IND FER BEAD 330OHM@100MHZ 2.5A 25% 8 FB8-FB1517 IND FER BEAD 100 OHM@100MHZ 3A -- 1206 4 FB4-FB718 IND PWR CHK 1.06UH@100KHZ 16A 20% 0505 1 L219 CON 8X10 RA SHLD SKT TH 2.5MM SP AU 1 P720 CON 3 PWR PLUG RA SHRD TH -- AU 2 P5,P621 CON 1X2 GIG MAG-JACK TAB-UP WITH LEDS 2 J18,J1922 HDR 2X5 TH 100 MIL CTR .100H AU 2 J1,J223 CON DSUB 9POS PLUG RA 1 J1524 CON 2X20 SHRD SKT SMT 50MIL SP AU 2 J4,J525 CON 2X13 SMT .05 IN CTR WITH KEY 1 J926 CON 38 SKT 25MIL CTR AU 3 J14,J16,J1727 CON 10X40 SKT SMT 50MIL CTR AU 3 J3,J10,J1128 HDR 2 X 25 .050 CTR AU SMT 1 J1329 OSC 125.000MHZ VCO 3.3V SMT 1 Y130 OSC 16.000MHZ VCO 3.3V SMT 1 U4431 OSC 19.440MHZ VCO 3.3V SMT 1 U2732 OSC 77.760MHZ FIXED 3.3V 7.0MM X 5.0MM 1 U2233 CON 1 PWR SKT TH -- -- 2 GM1,GM234 IC ATM-SONET AND POS SGL CHNL 155.52MBS -- 1 U2535 IC MUX CLK 200MHZ 3-5.5V TSSOP 16 2 U56,U5736 IC VSUP 2 1.2-5.5V SOIC 8 4 U34,U37,U63,U6437 IC CTLR 8BIT 400KHZ 2.3-5.5V TSSOP 16 4 U48,U52,U53,U5538 IC BUF TS 1.65-5.5V SC-70 13 U3,U4,U26,U28,U30,U32,U33,U35,U36,U38,U39,U43,U45
39 IC BUF 200MHZ 2.5/3.3V TQFP 32 1 U5040 IC XCVR SONET 4.75-5.25V SIP 1X9 1 U1241 IC BUF 400KHZ 2.7-5.5V MSOP 8 1 U242 IC XCVR -- 5/3.3V SOIC 28 2 U16,U4743 IC LIN SW 32BIT:16BIT 500MHZ 2.3-3.6V TSSOP 56 6 U7,U8,U17,U18,U20,U21 Unsolder and lift up the IC lead of U7, pin 4 away from
the pad on the PCB. Please make sure pins 3 and pin 5 of U7 is not shorted
44 IC LIN SW 2BIT:1BIT 500MHZ 2.3-3.6V TSSOP 16 2 U19,U4145 IC BUF DRV 16BIT TS 1.65-3.6V TSSOP 48 2 U40,U4646 IC VREG LDO ADJ VOLTAGE 3A S-PAK-5 1 U6747 IC BUF 0.25NS 3-3.6V TSSOP 16 2 U9,U1148 IC XCVR MULTIMODE LOW COST 1 X 9 PKG 1 U1349 IC CLOCK GEN 200MHZ 3-5.5V SSOP 28 1 U4250 IC BUS SWITCH LOW VOLTAGE QSOP20 3 U58,U59,U6251 IC VREG LDO 2IN ADJ 1.5A 1.4-6.5V S-PAK 5 1 U6652 IC LIN COMP 2 2-36V SOIC 8 1 U6853 IC MEM SRAM 8KX8 3.3V POWERCAP 34 1 U5154 POWER CAP MODULE WITH CRYSTAL SM, ROHS
COMPLIANT1 U51A
55 IC XCVR QUAD GIG E HSLBGA364 ROHS COMPLIANT
1 U65
56 IC LIN AMP HIGH SIDE CURRENT SENSING SOT-23 1 U1457 IC LIN NON ISOLATED DC/DC CONVERTER DIP 12 1 U8058 IC ATM-SONET PHY -- 3.3V SBGA 304 1 U2359 IC FPGA 150K GATE 3.3V BGA-256 1 U2460 IC,EEPROM,NOR
FLASH,4MX16,CMOS,TSSOP,48PIN,PLASTIC, ROHS COMPLIANT
2 U49,U54
61 IC MEM EEPROM 8192X8 400KHZ 2.7-5.5V SOIC 8 1 U162 LED GRN SGL 2.2V 20MA 0603 2 D9,D1063 LED RED SGL 1.8V 25MA 0603 20 D1-D8,D11-D2264 RES MF 22.1 OHM 1/16W 1% 0402 34 R250-R28365 RES MF 100 OHM 1/16W 0.1% 0402 12 R36,R37,R121,R132,R137,R140,R144,R170,R171,R175,R178,R179
66 RNET BUS 8 1.0K 1/16W 5% 1608 4 RN1,RN5-RN767 RNET BUS 8 4.7K 1/16W 5% 1608 4 RN2-RN4,RN868 RES MF 5.6K 1/16W 5% 0402 1 R21669 RES MF 150 OHM 1/16W 1% 0402 4 R100-R102,R24970 RES MF 158 OHM 1/16W 1% 0402 4 R106-R10971 RES MF 15.0 OHM 1/16W 1% 0402 3 R145,R159,R16072 RES MF 2.00K 1/16W 1% 0402 1 R13173 RES MF 2.70 OHM 1/16W 1% 0402 2 R116,R13874 RES MF 301 OHM 1/16W 1% 0402 5 R97,R98,R110,R113,R12075 RES MF 49.9 OHM 1/16W 1% 0402 36 R86-R89,R217-R24876 RES MF 4.70 OHM 1/16W 1% 0402 2 R99,R14977 RES MF ZERO OHM 1/16W -- 0402 37 R56,R63,R67,R68,R74,R85,R104,R105,R111,R112,R114,R126,R127,R133,R134,R147,R
154,R158,R161,R162,R284-R289,R304,R306-R311,R352,R383,R384,R387
78 RES MF ZERO OHM 1/8W -- 0805 3 R208-R21079 RES MF 10K 1/16W 5% 0402 12 R75,R119,R122-R125,R128-R130,R296-R29880 RES MF 100K 1/16W 5% 0402 5 R135,R153,R163,R294,R29581 RES MF 220 OHM 1/16W 5% 0402 10 R28-R35,R78,R8082 RES MF 330 OHM 1/16W 5% 0402 14 R53,R54,R59,R60,R79,R81,R373-R38083 RES MF 4.7K 1/16W 5% 0402 65 R47,R48,R51,R52,R57,R58,R82-R84,R92-R96,R103,R115,R118,R136,R141-
R143,R151,R152,R155-R157,R168,R183-R185,R189-R196,R199,R200,R314-R320,R355-R372
84 RES MF 47 OHM 1/16W 5% 0402 8 R343-R35085 RES MF 33 OHM 1/16W 5% 0402 12 R146,R148,R164-R167,R173,R174,R186,R197,R198,R351
86 RES MF 2.2K 1/16W 5% 0402 16 R321-R328,R332,R336-R34287 RES MS 0.01 OHM 1.0W 1% 1206 3 R44,R313,R38688 RES MF 10.0 OHM 1/8W 1% 0805 2 R150,R207
89 RES MF 2.7K 1/16W 5% 0402 2 R211,R21290 RES MF 10.0 OHM 1/16W 1% 0402 3 R201-R20391 RES MF 1.0K 1/16W 5% 0402 7 R25,R45,R46,R90,R117,R299,R38592 RES MF 5.11K 1/16W 1% 0402 4 R290-R29393 RES MF 511 OHM 1/16W 1% 0402 1 R21594 RES MF 5.0 OHM 1/8W 5% 0805 1 R17695 RES MF 4.75K 1/16W 1% 0402 1 R21496 RES MF 147 1/16W 1% 0402 1 R21397 SW SPST DIP 50V 100MA SMT 4 SW1-SW498 SW SPDT ULTRA-MIN PUSHBUTTOM GULL R ANGLE 3 SW5-SW7
Created By:Create Time:
CDS Carrier BOM, Rev. 1.3
MPC8555E Configurable Development System Reference Manual, Rev. 1
E-6 Freescale Semiconductor
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor F-1
Appendix F CDS Carrier Schematics, Rev. 1.3This appendix provides CDS carrier board schematics for Rev. 1.3.
Table F-1 lists the hardware differences between carrier card Rev. 1.2 and Rev. 1.3.Table F-1. Differences Between Carrier Card Rev. 1.2 and Rev. 1.3
Item No. What is Changed on CDS Carrier Card Rev. 1.3Schematic Sheet No.
1 Replace Cicada Quad PHY with MARVELL Quad PHY. Also added level shifters. All four Ethernet ports are connected with the PHY.
19–22
2 Moved all the IO card functionality except the USB port to the carrier. The USB port was not connected to anything on Rev. 1.2.
22
3 Replace the obsolete RC5051M DC-DC converter to Belfuse SRDB-30B1AH. It will convert 5 V to 2.5 V.
8
4 Update the existing clock structure to support MPC8555E SYSCLK and PCICLK signals. 9
5 Power pin filtering for clock drivers and oscillator. 9, 10
6 Remove IO card connector J7 (see schematic ver. 1.2a) since there is no RoHS compliant replacement from Samtec.
22
7 Replaced obsolete 77.76 MHz oscillator (U22) with a different package that has multiple source. 29
8 Convert BOM to use RoHS compliant part number (lead free) All
9 Allow I2C communication with the Arcadia to gather information such as FPGA version from the Arcadia.
7, 18
10 Connect unused DIP switch pin to the FPGA for future use. 5, 6
Project:7700 W. Parmer Ln
CDS_CarrierCover Story
2/23/2006
1:00:46 pmAustin, Texas 78729
Carrier
freescaleFreescale Semiconductor
semiconductor
TMDate Changed:
Time Changed:Engineer:
Revision:Page:Title:Gary Milliorn 01
1.3
15
PCI Bus #1 Edge Connector18HMZD Connector + Banjo Headers17
Quad Ethernet PHY MAC Interface
DATE
33
Bypass Capacitors35
IOCard Connector
27
All rights reserved. No warranty is made, express or implied.
14DaughterCard Connector (Right, Part II)
Unless otherwise specified:All resistors are SMD0402, in ohms, 0.08W, +/-5%All capacitors are SMD0402, in microfarads (uF), +/-20%.
26
FCC1/ATM1 (622Mbps) Interface28
32
Austin, Texas 78729
11DaughterCard Connector (Left, Part I)Misc: LEDs, Debug Port, I2C
the most-significant bit), except where industry standards
Components with the label "No_Stuff" are not to be installed bydefault; they are for test or manufacturing purposes only.
V1.3 27Jan06 Replace Ethernet PHY, RoHS
VCC_2.5
Block Diagram
01
Freescale Sale/FAEs to obtain the latest information on
System Logic (part I)
General Information
07Local Power Supply08Local (non-PCI) Resources: Clock, Reset
VCC_1.2
Sheet VertZoneLetter HorizZoneNumber
DaughterCard High-Speed Connector16
Part numbers used are for reference only; compatibleparts may be used; refer to the bill of materials.
Freescale and the Freescale logo are registered
LocalBus NVRAM/Debug
Date Changed:
trademarks of Freescale Semiconductor. PowerPC is a trademark
All ferrites are Z=50 ohms at 100 MHz.
20
GNDVCORE
DaughterCard Connector (Left, Part II)13DaughterCard Connector (Right, Part I)
FCC1/ATM1: PHY Power
Initial version
FCC2/ATM2: PHY Power31
PCI/PCIX34
30
LocalBus Flash
5.
6.
7.
10
All buses follow big-endian bit numbering order (bit 0 is
Placement and PCB Stackup
02
Page ContentsSchematic Notes
respective copyright holders. For Kristi, with love.
12
CPM Routing: ATM2 and FE25uTCOM Header, part I
22
04
FCC2/ATM2: (155Mbps) Interface
Carrier
V1.2 04Oct04 Errata fix; see errata.
uTCOM Header, part II
System Logic (part II)
This schematic is provided for reference purposes only.All information is subject to change without notice.No warranty, expressed or applied, is made as to the
06
CHANGES
The sheet-to-sheet cross reference format is:
Configuration05
apply (i.e. PCI). Little-endian numbering is noted at thesource component.
Board impedance is 55 +/- 5 ohms.
19Quad Enet PHY Power/System Interface
Revision:Page:Title:
accuracy of the information contained herein. Contact
Project:
Ethernet Ports #1 and #221
CPM Routing: ATM124
Cover Page
Time Changed:
03Nov03V1.0
7700 W. Parmer Ln
this product.
All fuses are self-resetting polyswitch (PTC) devices.
Integrated circuits have default connections to power
1.
2.
VCC_3.3VCC_5
3.
Local High-Speed Clock
Information, please2/23/2006
1:01:30 pm
and ground unless explicitly shown otherwise. Global powerconnections are:
09
23
All inductances are in microhenries (uH).
29
4.
freescaleFreescale Semiconductor
semiconductor
TM
V1.1 04Apr08 Errata fix; see errata.
03
Serial Port
36
AdTech Adapter Connector
of IBM. Other trademarks are the respective property of their
Engineer:
REV
Gary Milliorn1.3
02CDS_Carrier
06-07
Supplies08
CPM Select
Mezzanine
freescaleFreescale Semiconductor
semiconductor
TM
Local Bus
Revision:Engineer:7700 W. Parmer Ln
Austin, Texas 78729
HmZd
PHY
High-Speed
19-22
10/100/1000baseTConnectors
19 24-25
26-27
ConnectorATM PHYs
29-32
Date Changed:
Time Changed:
Interface
Configuration
Page:Title:Project:
11, 34
Connector
34
Debug
17
05
Logic
LogicSystem
Block Diagram2/23/2006
1:02:04 pm
Clocks
Power
09-10
12-14
Connectors
LocalBus
I2C Devices
11
Test Access
33-34
Flash + NVRAM
PCI/PCI-X
18
Connector
Quad Ethernet
15-16
uTCOM
Gary Milliorn1.3
03CDS_Carrier
LAYER 2LAYER 3
Title:
SIGNAL: 7SIGNAL: 8
PLANE: GND
PLANE
BURIED CAPACITANCE LAYER
0.5ozPLANE: VCC_2.5
LAYER 1
freescaleFreescale Semiconductor
semiconductor
TM
0.5oz0.5oz
PLANE: VCC_3.3SIGNAL: 9
SIGNALSIGNAL
Date Changed:
Time Changed:Engineer:
Revision:
PLANE: VCC_3.3
SIGNALSIGNALPLANESIGNAL
SIGNAL
Project:7700 W. Parmer Ln
0.5oz
SIGNAL: 1
SIGNAL: 10
PLANE: GNDSIGNAL: 2
LAYER 4
LAYER 10LAYER 11
.062
Austin, Texas 78729
LAYER 18LAYER 17
SIGNALSIGNAL
0.5ozLAYER 14LAYER 15
LAYER 5LAYER 6LAYER 7
PLANE
PLANE
0.5oz
0.5oz
COMP 0.5oz PLANE: GND
SIGNAL: 3
SIGNAL: 4
SOLDERSIGNAL
0.5oz
SIGNAL: 5SIGNAL: 6
0.5oz
0.5oz0.5oz0.5oz
Placement (approximate) and PCB Stackup2/23/2006
1:02:42 pmPage:
PLANE: GND
PLANE: VCC_2.5
0.5oz
LAYER 13
LAYER 16
LAYER 8LAYER 9
LAYER 12
SIGNALPLANE
BURIED CAPACITANCE LAYER
0.5oz0.5oz0.5oz0.5oz
Gary Milliorn1.3
04Carrier
REMOTE CONTROL 1+2ADDR=0x18+0x19
Gary Milliorn1.3
05CDS_Carrier
Carrier Configuration2/23/2006
1:03:18 pmTime Changed:Engineer:freescale
Freescale Semiconductor
semiconductor
TMDate Changed:
Revision:Page:
REMOTE CONTROL 3+4
7700 W. Parmer Ln Title:Project:
ADDR=0x1A+0x1B
Austin, Texas 78729
Date Changed:
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Freescale Semiconductor
semiconductor7700 W. Parmer Ln Title:
Project:
Austin, Texas 78729
ACTEL PROGRAMMING HEADERLocate within 3" of device.
Gary Milliorn 061.3
CDS_CarrierSystem Control Logic (part I)
2/23/2006
1:03:59 pm
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Revision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
freescaleFreescale Semiconductor
Gary Milliorn1.3
07CDC_Carrier
System Logic (part II)2/23/2006
1:04:56 pmsemiconductor
TM
Date Changed:
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Revision:
POWER SUPPLY LAYOUT RULES
Project:Page:Title:
should be on the same layer, with area filled connections.
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TM
2. No vias or thermal reliefs allowed on power path components.
3. Ground plane connections should be made with two vias closeto the component.
THERMAL HEATSINK PLANE FILL10 cm^2 on top layer
Gary Milliorn1.3
08CDS_Carrier
System +2.5V Power Supply2/23/2006
1:07:50 pm
1. All components in the power path (large/red bus)
7700 W. Parmer LnAustin, Texas 78729
Date Changed:
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Project:
SPECIAL PLACEMENTPLACE BOTH ICS580 NEXT TO EACH OTHER
Time Changed:Engineer:freescale
Freescale Semiconductor
semiconductor
Non-re-config reset.
Austin, Texas 78729
TM 7700 W. Parmer Ln
LOCAL RESET
Gary Milliorn1.3
09CDS_Carrier
Local (non-PCI) Resources: System Clock, System Reset2/23/2006
2:04:26 pm
Engineer:Project:
Revision:Page:Title:
HIGH-SPEED EXTERNAL CLOCKOptional high-speed/flexible
clock source.
DEFAULT=124MHz
freescaleFreescale Semiconductor
LOCAL SYSTEM CLOCKUsed on non-PCI HIP boards or stand-alone.
semiconductor
Gary Milliorn1.3
10CDS_Carrier
High-Speed Clock Generation2/23/2006
1:11:54 pmTM
Date Changed:
Time Changed:7700 W. Parmer LnAustin, Texas 78729
TM
POWER-ON RESET
Re-config reset.
CARRIER CONFIGAddr=0x56
REMOTE CONTROL ACCESS HEADER
Time Changed:
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Revision:Page:Title:freescale
Project:Freescale Semiconductor
semiconductor
Gary Milliorn1.3
11CDS_Carrier
Miscellaneous: LEDs, Debug Port and I2C Devices2/23/2006
1:12:47 pm7700 W. Parmer LnAustin, Texas 78729
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Project:
Austin, Texas 787297700 W. Parmer Ln 12
CDS_CarrierCDC DaughterCard Connector (Left, Part I)
1/27/2006
2:13:56 pmfreescaleFreescale Semiconductor
semiconductor
TM Gary Milliorn1.3
Date Changed:Freescale Semiconductor
semiconductor
TM Engineer:Revision:
Page:Title:Project:
7700 W. Parmer LnAustin, Texas 78729
Gary Milliorn 131.3
CDS_CarrierCPU DaughterCard Connector (Left, part II)
2/23/2006
1:13:38 pmTime Changed:freescale
freescaleFreescale Semiconductor
semiconductor
TMDate Changed:
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Revision:Page:Title:
Project:7700 W. Parmer Ln Gary Milliorn
1.214
CDS_CarrierCDC DaughterCard Connector (Right, Part I)
2/23/2006
1:14:17 pmAustin, Texas 78729
Austin, Texas 78729
Date Changed:Gary Milliorn
1.215
CDS_CarrierCDC DaughterCard Connector (Right, Part II)
2/23/2006
1:28:53 pmTime Changed:Engineer:
Revision:Page:freescale
Freescale Semiconductor
semiconductor
TM Title:Project:
7700 W. Parmer Ln
Title:Project:
7700 W. Parmer LnAustin, Texas 78729
2/23/2006
1:39:59 pm
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Expansion Ports
Revision:Page:Gary Milliorn 16
1.3
CDS_CarrierHigh-Speed IO Daughtercard Connector
The high-speed protocol signals are
routed THROUGH the Tek P6880
Yes, the connector connections are
connected correctly! Polarity
Transmit PathFrom processor to motherboard/target.
Receive PathTo processor from motherboard/target.
freescaleFreescale Semiconductor
semiconductor
TMDate Changed:
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Title:Gary Milliorn 17
1.3
CDS_Carrier High-Speed Differential IO, HMZD/HIP Interface and P6880 "Banjo" Receive probes2/23/2006
1:43:55 pm
Project:
disassembler.
7700 W. Parmer LnAustin, Texas 78729
connectors, despite appearances!
differences are handled in the
Date Changed:
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Revision:Page:Title:
Project:Gary Milliorn
1.318
CDS_CarrierPrimary PCI/PCI-X Edge Connector
2/23/2006
1:44:34 pm7700 W. Parmer LnAustin, Texas 78729
(motherboard-dependant option also).
Place sense Rs within 1cm of edge connector
NON-STANDARDAllow PCI/HIP card to reset motherboard
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TM
semiconductor
TMfreescaleFreescale Semiconductor
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Project:Gary Milliorn 19
1.3
CDS_CarrierQuad 10/100/GB PHY MAC Interfaces
2/23/2006
1:45:31 pm
ETHERNET PORT #2
ETHERNET PORT #1
Austin, Texas 787297700 W. Parmer Ln
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Revision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
+1.0V
freescaleFreescale Semiconductor
semiconductor
TM
+2.5V
Gary Milliorn 201.3
CDS_CarrierQuad 10/100/Gb PHY Power/System Interface
2/23/2006
2:00:40 pm
ETHERNET PORT #4
TMProject:
Revision:freescaleFreescale Semiconductor
semiconductor
Page:Title:
ETHERNET PORT #3
7700 W. Parmer LnAustin, Texas 78729
Date Changed:
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1.3
CDS_CarrierEthernet Ports #3 and #4
2/23/2006
2:02:03 pm
freescaleFreescale Semiconductor
semiconductor
TMDate Changed:
Time Changed:Engineer: Gary Milliorn
1.322
CDS_CarrierCarrier-to-IOCard Connector
1/27/2006
2:11:35 pmRevision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
SERIAL PORT #1
7700 W. Parmer LnAustin, Texas 78729
Primary Serial Port
SERIAL PORT #2Secondary Serial Port
Gary Milliorn1.3
23CDS_Carrier
Serial Ports2/23/2006
2:03:23 pmfreescaleFreescale Semiconductor
semiconductor
TMDate Changed:
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Project:
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Revision:Page:Title:
Project:Gary Milliorn
1.324
CDS_CarrierCPM Routing for ATM1
2/23/2006
2:05:09 pm7700 W. Parmer LnAustin, Texas 78729
freescaleFreescale Semiconductor
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TM
Date Changed:
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Revision:7700 W. Parmer LnFreescale Semiconductor
Austin, Texas 78729Gary Milliorn 25
1.3
CDS_CarrierCPM Routing for ATM2 and FastEthernet
2/23/2006
2:05:58 pmfreescalesemiconductor
TM Page:Title:Project:
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:freescale
Freescale Semiconductor
semiconductor
TM 7700 W. Parmer LnAustin, Texas 78729
Gary Milliorn 261.3
CDS_CarrieruTCOM Connector (part I)
2/23/2006
2:09:47 pm
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:Gary Milliorn
1.327
CDS_CarrieruTCOM Connector (part II)
2/23/2006
2:10:31 pm
Project:freescale
Freescale Semiconductor
semiconductor
TM 7700 W. Parmer LnAustin, Texas 78729
ADTECH RX
Place and Group Connectors per spec
ADTECH TX
freescaleFreescale Semiconductor
semiconductor
TM Gary Milliorn 281.3
CDS_CarrierFCC1/ATM1: AdTech Adapter Connector
2/23/2006
2:11:41 pm
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
Austin, Texas 787297700 W. Parmer Ln
Title:7700 W. Parmer LnAustin, Texas 78729
freescaleFreescale Semiconductor
semiconductor
TMDate Changed:
Revision: Time Changed:Page:Gary Milliorn
1.329
CDS_CarrierFCC1/ATM1: 622 Mbps Interface
2/23/2006
2:12:40 pmEngineer:
Project:
Title:Date Changed:
Time Changed:Engineer:
Project:freescale
Freescale Semiconductor
semiconductor
SENSITIVE POWER FILTERS’Capacitors without VCC_3.3V resistorsMUST be placed near corresponding power pad.
CDS_CarrierFCC1/ATM1:PHY Power
2/23/2006
2:13:27 pmTM 7700 W. Parmer Ln
Austin, Texas 78729 Revision:Page:Gary Milliorn 30
1.3
freescaleDate Changed:
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Revision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
Gary Milliorn 311.3
CDS_CarrierATM2: 155Mbps Interface
2/23/2006
2:14:04 pm
Freescale Semiconductor
semiconductor
TM
freescaleFreescale Semiconductor
semiconductor
TMDate Changed:
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Revision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
Gary Milliorn1.3
32CDS_Carrier
FCC2/ATM2: PHY Power1/27/2006
2:12:39 pm
Date Changed:freescale
Freescale Semiconductor
semiconductor
TM
Time Changed:Engineer:
Revision:Page:Gary Milliorn
1.333
CDC_CarrierFlash Memory + Flash Emulator
2/23/2006
2:14:39 pmTitle:
Project:
Flash Emulator(PromJet 16NVS)
7700 W. Parmer LnAustin, Texas 78729
FLASH BANK 2FLASH BANK 1
TMDate Changed:
Time Changed:Engineer:
Revision:Page:Title:
2/23/2006
2:15:30 pm
Project:7700 W. Parmer LnAustin, Texas 78729
freescaleFreescale Semiconductor
semiconductor
Gary Milliorn1.3
34CDS_Carrier
Local Bus NVRAM/Debug Connectors
Page:Title:Austin, Texas 787297700 W. Parmer LnfreescaleFreescale Semiconductor
Gary Milliorn 351.2
CDS_Carrier--reserved--
2/23/2006
2:16:14 pmsemiconductor
TMDate Changed:
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Revision:
Project:
Page:Title:Freescale Semiconductor
semiconductor7700 W. Parmer LnAustin, Texas 78729
Add or subtract based on density.GLOBAL BYPASS CAPS.
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Revision:Gary Milliorn 36
1.2
CDS_CarrierBypass Capacitors
2/23/2006
2:16:47 pm
Project:freescaleTM
CDS Carrier Schematics, Rev. 1.3
MPC8555E Configurable Development System Reference Manual, Rev. 1
F-38 Freescale Semiconductor
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor G-1
Appendix GCDS CDC BOM This appendix provides CDC BOM for Rev. 1.1.
# Board Station BOM file CDS MPC85XX V 1.1 BOM# date : Tuesday July 6, 2004; 12:09:48 Updated on 8/18/04# Variant : No_Stuff
ITEM_NO COMPANY PART NO. GEOMETRY COUNT DESCRIPTION REFERENCE
1 PCB 12 0603YC104JAT2A cc0603 1 cap, 0.1uF, AVX C473 102972-3 header_1x3 1 header.1x3, AMP J34 103309-3 header_riscwatch 1 header.2x8 J15 218-8LPST sw_som16 4 sw.8spst.cts, CTS SW1 SW2 SW3 SW46 293D476X9016D2T cct7343 1 cap_tant, 47uF, SPRAGUE C87 33-40111-1 1 pbga_28x28_socket_tecknit8 597-5112-40X led_0603 12 led, Dialight, Red D1 D2 D3 D4 D5 D6
D7 D8 D9 D10 D11D12
9 71243-3002 conn_184ddr_Molexdimm_vert 1 conn_184_ddr_dimm_2.5v_angled_1of2, AMP P310 SN74LVC74APW so14 1 sn74lvc74a.sso14, TI U2
sub SN74LV74APW 11 74lv08d so14 1 74lv08d.so14, TI U512 84740-002 connFCI_array_10x40_sm 2 conn.megarray.10x40.1of5, FCI J4 J513 981131-120-2MCF pciconn_3.3v_ra_32bit 1 pciconn_3.3V_ra_32bit_block, MERITEC J214 AT24C64AN-10SI-2.7 so8 2 at24c64a.s08, ATMEL U25 U3115 EEFUE0E221R cc_7.3x4.3_ue 6 cap_tant, 220uF, PANSONIC C79 C80 C94 C179
C209 C21016 EH2645TS-66.000M osc_smd_5x7mm 1 osc.3_3v.smd, 66.666MHz, ECLIPTEK U317 EMK107F224ZA cc0603 1 cap, .22uF, TAIYO_YUDEN C1518 ERJM1WTJ1M5U rc2512 2 res, 1.5mohm, PANASONIC R149 R26619 EXCCL4532U1 induct_4532 1 exccl4532.smd, PANASONIC L220 IDTQS3VH257PA tssop16 2 idtqs3vh257.tssop16, IDT U10 U1121 IRF6604 irf6604 2 irf66xx.dirfet, IRF Q1 Q222 IRF6607 irf6607 2 irf66xx.dirfet, IRF Q3 Q423 JMK107F225ZA cc0603 10 cap, 2.2uF, TAIYO_YUDEN C169 C170 C171
C172 C173 C174C175 C185 C186C187
24 K4S561632E-TC75 tsop54 2 sdram.sdr.jedec.tsop54, VAR U15 U1725 LM358D so8 1 lm358d.so8, NATSEMI U2726 LMK107F105ZA cc0603 3 cap, 1.0uF, TAIYO_YUDEN C13 C14 C4627 LP2995M so8 1 lp2995m.so8, National Semi U828 MAX1037EKA-T sot23_8p 1 max1037eka_t.sot23_8, Maxim U2629 MAX1813EEI ssop28_pit635mm 1 max1813eei.qsop28, MAXIM U930 MAX4372FEUK-T sot23_5p 1 max4372f.sot23_5, Maxim U1331 MBRS140T3 smb_403a 1 mbrs140t3.smb, MOT CR132 MBRS340T3 smb_403 1 mbrs340t3.smb, MOT CR233 MCCA104K0NRT cc0402 140 cap, 0.1uF, SMEC C1 C2 C3 C4 C5 C6
C9 C10 C16 C17 C18C19 C20 C21 C22C23 C24 C25 C26C27 C28 C29 C30C31 C33 C34 C35C36 C37 C38 C39C40 C41 C42 C52C81 C82 C83 C87C88 C89 C90 C91C92 C95 C96 C97C98 C99 C100 C101C102 C103 C104C105 C106 C107C108 C109 C110C111 C112 C113C114 C115 C116C117 C119 C120C121 C123 C124C125 C126 C127C128 C129 C130C131 C132 C133C134 C135 C136C137 C138 C139C140 C141 C142C143 C144 C145C146 C147 C148C149 C150 C151
C152 C153 C154C155 C156 C160C161 C162 C163C164 C165 C166C168 C176 C177C178 C180 C181C182 C183 C184C188 C189 C190C191 C192 C193C194 C195 C196C197 C198 C199C200 C201 C202C203 C204 C206C207 C208
34 MCCA470K0NRT cc0402 1 cap, 47pF, SMEC C5035 MCCE102KONRT cc0402 2 cap, 1000pF, muRATA C48 C4936 MNR14-EOAB-J-390 rnet1632 4 rnet, 39, Rohm RN4 RN5 RN6 RN737 MPC8555 pbga_28x28_1mm_skt 1 dracomLITE.1of9.ddr.pbga783, Motorola U1938 Not_a_component jump_2x1_1mil 1 splice.1, PCB SP139 P6880 conn_banjo 1 conn.banjo_alt, Tektronix P240 PCA9557PW tssop16 4 pca9557pw.tssop16, PHILIPS U23 U24 U28 U3041 RC73L2Z000JT rc0402 11 res, 0, KOA R145 R222 R223
R302 R303 R307R317 R320 R322R334 R346
42 RC73L2Z100JT rc0402 6 res, 10, KOA R87 R319 R327 R329R332 R336
43 RC73L2Z101JT rc0402 6 res, 100, KOA R8 R146 R148 R295R296 R341
44 RC73L2Z102JT rc0402 13 res, 1K, KOA R19 R26 R284 R288R293 R294 R304R305 R306 R315R337 R339
45 RC73L2Z103JT rc0402 3 res, 10K, KOA R25 R344 R34546 RC73L2Z104JT rc0402 11 res, 100K, KOA R22 R283 R291 R292
R297 R310 R311R312 R313 R314
R32447 RC73L2Z124JT rc0402 1 res, 120K, KOA R14748 RC73L2Z154JT rc0402 1 res, 150K, KOA R2449 RC73L2Z200JT rc0402 2 res, 20, KOA R20 R31850 RC73L2Z220JT rc0402 129 res, 22, KOA R3 R4 R150 R151
R152 R153 R154R155 R156 R157R158 R159 R160R161 R162 R163R164 R165 R166R167 R168 R169R170 R171 R172R173 R174 R175R176 R177 R178R179 R180 R181R182 R183 R184R185 R186 R187R188 R189 R190R191 R192 R193R194 R195 R196R197 R198 R199R200 R201 R202R203 R204 R205R206 R207 R208R209 R210 R211R212 R213 R214R215 R216 R217R218 R219 R220R221 R224 R225R226 R227 R228R229 R230 R231R232 R233 R234R235 R236 R237R238 R239 R240R241 R242 R243R244 R245 R246R247 R248 R249
R250 R251 R252R253 R254 R255R256 R257 R258R259 R260 R261R262 R263 R264R265 R269 R270R271 R272 R273R274 R275 R276R277 R290 R298R300 R301
51 RC73L2Z221JT rc0402 12 res, 220, KOA R6 R7 R9 R10 R11R12 R13 R14 R15R16 R17 R18
52 RC73L2Z223JT rc0402 2 res, 22K, KOA R279 R34353 RC73L2Z270JT rc0402 116 res, 27, KOA R27 R28 R29 R30
R31 R32 R33 R34R35 R36 R37 R38R39 R40 R41 R42R43 R44 R45 R46R48 R49 R50 R51R52 R53 R54 R55R56 R57 R58 R59R60 R61 R62 R63R64 R65 R66 R67R68 R69 R70 R71R72 R73 R74 R75R76 R77 R78 R79R80 R81 R82 R83R84 R85 R86 R88R89 R90 R91 R92R93 R94 R95 R96R97 R98 R99 R100R101 R102 R103R104 R105 R106R107 R108 R109R110 R111 R112R113 R114 R115
R116 R117 R118R119 R120 R121R122 R123 R124R125 R126 R127R128 R129 R130R131 R132 R133R134 R135 R136R137 R138 R139R140 R141 R142R143 R144
54 RC73L2Z331JT rc0402 1 res, 330, KOA R555 RC73L2Z333JT rc0402 1 res, 33K, KOA R28056 RC73L2Z390JT rc0402 2 res, 39, KOA R281 R28257 RC73L2Z391JT rc0402 1 res, 390, KOA R299 58 RC73L2Z472JT rc0402 1 res, 4.7K, KOA R4759 RC73L2Z563JT rc0402 1 res, 56K, KOA R34260 RC73L2Z862JT rc0402 1 res, 8.6K, KOA R34061 RNA4A8E102JT rna4a 4 rnet8.bussed.rna4a, 1K, AVX RN12 RN15 RN17
RN1862 RNA4A8E472JT rna4a 4 rnet8.bussed.rna4a, 4.7K, AVX RN13 RN14 RN16
RN1963 RNA4A8E472JT rna4a 7 rnpullup_3.3v.rna4a, 4.7K, AVX RN1 RN2 RN3 RN8
RN9 RN10 RN1164 SN74ALVCH32973KR lfbga96 2 74alvch32973kr.lfbga96, TI U16 U2065 SN74CBT16211ADGGR ssop56_20mil 2 74cbt16211dggr.ssop56, TI U14 U1866 SN74LVC04APW tssop14 1 74lvc04a.tssop14, TI U767 SN74LVC16244ADGG tssop48 2 74lvc16244adgg.tssop48, TI U22 U2968 SN74LVC1G04DCKR sot_5p 1 sn74lvc1g04.sot_5p, TI U669 SN74LVC1G125DCKR sc70 3 74lvc1g125.sc70, TI U1 U4 U2170 SN74LVCH32244GKER lfbga96 1 sn74lvch32244gker.lfbga96, TI U1271 T510X337M010AS cct_casee 6 cap_tant, 330uF, Kemet C84 C85 C86 C122
C167 C20572 TMK432BJ106MM cc1812 7 cap, 10uF, TAIYO_YUDEN C11 C12 C43 C44
C45 C93 C11873 TPSE227K010R0100 cct_casee 3 cap_tant, 220uF, AVX C7 C32 C5174 RC73L2Z000JT rc0402 1 res, 0 ohm, KOA R21 R2375 ETQP6F0R6BFA induct_12.5x12.5 1 indutor, 0.6IH L1
CDS CDC BOM
MPC8555E Configurable Development System Reference Manual, Rev. 1
G-8 Freescale Semiconductor
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor H-1
Appendix HCDS CPU Schematics (CDC)This appendix provides CPU board schematics for Rev. 1.1.
Freescale Semiconductor
semiconductor
CDC_MPC85xx_783
Cover Story6/11/2004
2:36:16 pmTM Title:freescale
Project: Date Changed:
CDC_MPC85xx
ofAustin, Texas 787297700 W. Parmer Ln
Time Changed:Engineer:
Revision:Page: 35Gary Milliorn
1.101
DDR Termination and Term PowerDDR DIMM #1
I2C Devices
Processor DDR Interface
General Information
All information is subject to change without notice.No warranty, expressed or applied, is made as to theaccuracy of the information contained herein.
VCC_12OVDD
All fuses are self-resetting polyswitch (PTC) devices.
Integrated circuits have default connections to power
01
3.
16
All resistors are SMD0402, in ohms, 0.08W, +/-5%
Daughtercard Connector (left, part II)
8.
reserved. No warranty is made, express or implied.
12
IBM. Other trademarks are the respective property of their
All capacitors are SMD0402, in microfarads (uF), +/-20%.
Power Supply
All inductances are in microhenries (uH).
VCC_5
06
Unless otherwise specified:
27
13
Sheet VertZoneLetter HorizZoneNumber
Jon Burnett...............Simulation/Program Management
2.
GND
0708
Clock/JTAG/Debug InterfaceProcessor Configuration
Processor PCI #1 Interface
Daughtercard Connector (left, part I)
4.
Block Diagram
23
respective copyright holders. Don't wait for tomorrow. All rights
04
19
Schematic Notes
05
Margarito Trevino.....Tech/Debug
This schematic is provided for reference purposes only.
Initial version
09
the most-significant bit), except where industry standards
Gary Milliorn.............Hardware DesignCindy Callis..............CAD/Layout
1.
Freescale Semiconductor and the Freescale logo are registered
CHANGES
Title:Project:
VCC_3.3
6.
Date Changed:
Time Changed:Engineer:
Revision:
02
connections are:
Part numbers used are for reference only; compatible
18Processor LocalBus InterfaceLocalBus Memory
Secondary PCI Slot
Processor PCI #0 Interface
21
All ferrites are Z=50 ohms at 100 MHz.
14
REV
Page
All buses follow big-endian bit numbering order (bit 0 is
Components with the visible property "NO STUFF" are
Page:
11 ECC Breakout
Daughtercard Connector (right, part I)Daughtercard Connector (right, part II)
TM
New P/S ---->
15
7700 W. Parmer Ln
03Routing and Layout Information
The sheet-to-sheet cross reference format is:
10
Processor CPM/CE Interface
26
parts may be used; refer to the bill of materials.
Processor TSEC Interface
Processor PowerProcessor System Interface
Miscellany
22
DATEV1.0 03SEP25
CDC_MPC85xxTeam CDS is:
Austin, Texas 78729
not to be installed by default; they are for test or manufacturing
VCC_2.5
Contents
Tony Saucedo..........Purchasing
7.
CDC_MPC85xx_783Cover Story
6/11/2004
1:19:38 pm
20
Board impedance is 55 +/- 5 ohms.
purposes only.
source component.
trademarks of Motorola. PowerPC is a trademark of
apply (i.e. PCI). Little-endian numbering is noted at the
Alex Milliorn..............Best Buddy
5.
17
Capacitors28
Cover Page
VCORE
High-Speed Differential Connector
2425
and ground unless explicitly shown otherwise. Global power
V1.1 04APR04 Errata fixes
freescaleFreescale Semiconductor
semiconductorGary Milliorn 02
1.1
Revision:Page:Title:
Project:
05Supplies
09
12
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Processor
06/10/14/15/17-19
X
Local PCI Bus
16Connector
DDR DIMM
12
Time Changed:Engineer:
Block Diagram6/11/2004
1:20:22 pm
Socket
DDR Termination13
Mezzanine
22-25Connector
High-Speed
26Connector
Configuration
Power
Clocks
I2C Devices
Test Access
08Logic
Date Changed:
LocalBus
20Memory
LocalBus
19Demux/Buffer
Austin, Texas 78729Gary Milliorn
1.103
CDC_MPC85x_783
[4.7in]
BURIED CAPACITANCE LAYER
Date Changed:
Time Changed:Engineer:
PLANE
PLANE: GND
1.0oz
SIGNAL
1.0oz
PLANE
Revision:Page:Title:
Project:
0.5oz0.5oz0.5oz
PLANE
PLANE: VCC_2.5SIGNAL: 5SIGNAL: 6
0.5oz0.5oz0.5oz0.5oz
COMP
SIGNALPLANE
PLANESIGNALSIGNALPLANE
SIGNAL
SIGNAL
SOLDER
SIGNAL: 1
Austin, Texas 78729
160.0 mm [6.3in]
130.0 mm [5.1in]
120.0 mm
freescaleFreescale Semiconductor
semiconductor
TM
SIGNAL
SIGNAL: 7PLANE: GND
LAYER 1
PLANE: VCORE
LAYER 15SIGNAL: 2
LAYER 14
SIGNAL: 3
.095
LAYER 13
LAYER 16
0.5oz0.5oz
SIGNAL
SIGNAL: 4
Cover Story6/11/2004
12:20:26 pm
PLANE: VCC_3.3 + OVDDSIGNAL: 9SIGNAL: 10PLANE: GND
0.5oz0.5oz
LAYER 12
LAYER 10LAYER 11
LAYER 6LAYER 7LAYER 8LAYER 9
SIGNAL: 8
LAYER 2
LAYER 4LAYER 3
0.5oz
0.5oz0.5ozLAYER 5
7700 W. Parmer Ln Gary Milliorn1.1
04CDC_MPC85xx_783
1A Maximum
to the component.
18A Maximum
3. Ground plane connections should be made with two vias close
FANSINK HEADER
VCORE Output
1. All components in the power path (large/red bus)
2. No vias or thermal reliefs allowed on power path components.should be on the same layer, with area filled connections.
10 cm^2 on top layer
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:freescale
Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729
Gary Milliorn1.1
05CDC_MPC85xx_783
Processor Core Power Supply6/11/2004
2:52:16 pmsemiconductor
TM
POWER SUPPLY LAYOUT RULES
THERMAL HEATSINK PLANE FILL
Project:7700 W. Parmer LnAustin, Texas 78729
TSEC POWER
DDR POWER
CORE POWER, GUH
Gary Milliorn 061.1
CDC_MPC85xx_783
Processor Power Connections6/11/2004
2:51:02 pmfreescaleFreescale Semiconductor
semiconductor
TM
EVERYTHING ELSEPOWER
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Date Changed:
Time Changed:Engineer:
Revision:Page:freescale
Freescale Semiconductor
semiconductor
TM Title:
Reserved forFreescale only.
Project:7700 W. Parmer Ln Gary Milliorn
1.107
CDC_MPC85xx_783
System Interface6/11/2004
11:34:54 amAustin, Texas 78729
CONFIG OPTIONS
Freescale Semiconductor
semiconductor
TM
REMOTE CONTROL 2+3ADDR=0x22+0x23
Title:Project:
7700 W. Parmer Ln
ADDR=0x20+0x21
Austin, Texas 78729
REMOTE CONTROL 0+1
NOTE: Due to PCA9557 IssuesI2C Control pins are re-arranged.See V1.0 errata or V1.1 User's Manual
freescale Gary Milliorn1.1
08CDC_MPC85xx_783
DaughterCard Configuration10/30/2003
10:33:15 am
Date Changed:
Time Changed:Engineer:
Revision:Page:
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:freescale
Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729
Gary Milliorn 091.1
CDC_MPC85xx_783
PCI2 Clock Gen, Debug Interfaces, Reset6/11/2004
11:30:39 amsemiconductor
TM
CPU JTAG Header
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:freescale
Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729semiconductor
Gary Milliorn 101.1
CDC_MPC85xx_783
Processor DDR Interface6/11/2004
3:11:01 pmTM
semiconductor
TM
= 0.25nsPD
Compensation required on non-ECC/CB datapaths.
PATH t
Date Changed:
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Revision:Page:Title:
Project:freescale
Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729
Gary Milliorn 111.1
CDC_MPC85xx_783
ECC Debug Access Breakout7/27/2004
3:18:28 pm
DIMM #1 SPD
Date Changed:
Time Changed:
CDC_MPC85xx_783DDR SDRAM DIMM #1
6/11/2004
1:23:21 pmEngineer:
Revision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
freescaleFreescale Semiconductor
semiconductor
TM
ADDR=0x51
Gary Milliorn 121.1
Date Changed:
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Revision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
Gary Milliorn 131.1
CDC_MPC85xx_783
VTT+Termination Power and Termination Array6/11/2004
1:24:27 pmfreescaleFreescale Semiconductor
semiconductor
TM
Attach at mid-point of plane.
VTT TERMINATION PLANE
Place capacitors behind or intermingled with resistors.Place resistors immediately behind DIMM on a plane
Date Changed:
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Project:freescale
Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729
ofsemiconductor
TM
10K removed: PCI-X + 133 MHz
Not PCI compliant, yet required for non-PCI HIP.Minimal interference with actively driven signals.
10K installed: PCI-X + 66 MHz
PCI PULLUPS/PULLDOWNS
PCI-X SPEED ENCODING
Gary Milliorn1.1
14CDC_MPC85xx_783
PCI Interface #16/11/2004
3:17:32 pm35
Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729
6/11/2004
1:44:27 pmsemiconductor
TMDate Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:freescale Gary Milliorn
1.115
CDC_MPC85xx_783
PCI Interface #2
semiconductor
TM Gary Milliorn1.1
16CDC_MPC85xx_783
Secondary PCI Slot6/11/2004
2:08:26 pm
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:freescale
Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729
Date Changed:CDC_MPC85xx_783
Processor CPM/CE Interface6/11/2004
2:09:56 pmTime Changed:Engineer:
Revision:Page:Title:
Project:freescale
Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729semiconductor
TM Gary Milliorn1.1
17
freescaleFreescale Semiconductor7700 W. Parmer LnAustin, Texas 78729semiconductor
TMDate Changed:
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Revision:Page:Title:
Project:Gary Milliorn
1.118
CDC_MPC85xx_783
TSEC Ethernet Interface6/11/2004
2:11:21 pm
routes.
attempts to minimize loading on the address pins
slower local bus.of the local SDRAM, at a small cost to the remote/
Always 8 or 16 bits; see config
CDS LOCAL BUS WIDTH
Note: The admittedly convoluted buffering scheme
ADDRESS LATCH/BUFFER
Date Changed:
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Revision:Page:Title:
Project:freescale
Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729
for LB_SIZ(1) control.
semiconductor
TM
1ns (6cm) shorter than LBUS
NOTE: LALE LENGTHLALE (LBUS_SHORT) must be
Gary Milliorn1.1
19CDC_MPC85xx_783
Processor LocalBus and DeMux6/11/2004
2:12:40 pm
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:freescale
Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729semiconductor
TM Gary Milliorn 201.1
CDC_MPC85xx_783
LocalBus SDRAM and Buffers6/11/2004
3:00:27 pm
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:freescale
Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729
ID = 0x57
semiconductor
TM
BOOT SEQUENCER MEMORY
MODULE ID MEMORY
ID = 0x50
THERM AMPLIFIER
Gary Milliorn1.1
21CDC_MPC85xx_783
I2C Bus and Components6/11/2004
2:16:23 pm
Date Changed:
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Revision:Page:Title:
Project:freescale
Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729
Gary Milliorn1.1
22CDC_MPC85xx_783
CDC DaughterCard Connector (Left, Part I)6/11/2004
2:20:19 pmsemiconductor
TM
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:freescale Gary Milliorn
1.123
CDC_MPC85xx_783
CPU DaughterCard Connector (Left, part II)6/11/2004
2:21:38 pm
Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729semiconductor
TM
semiconductor
TM
CDC DaughterCard Connector (Right, Part I)6/11/2004
2:22:18 pm
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:freescale
Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729
Gary Milliorn1.1
24CDC_MPC85xx_783
semiconductor
TMDate Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:freescale
Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729
Gary Milliorn1.1
25CDC_MPC85xx_783
CDC DaughterCard Connector (Right, Part II)6/11/2004
2:24:22 pm
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:freescale
Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729
Gary Milliorn1.1
26CDC_MPC85xx_783
High-Speed Differential Connector6/11/2004
2:27:25 pmsemiconductor
TM
7700 W. Parmer LnAustin, Texas 78729semiconductor
TM Gary Milliorn1.1
27CDC_MPC85xx_783
Miscellany6/11/2004
2:33:23 pm
Date Changed:
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Revision:Page:Title:
Project:freescale
Freescale Semiconductor
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:freescale
Freescale Semiconductor7700 W. Parmer Ln Gary Milliorn
1.128
CDC_MPC85xx_783
Bypass Capacitors6/11/2004
2:34:52 pmAustin, Texas 78729semiconductor
TM
Add or subtract based on density.GLOBAL BYPASS CAPS.
CDS CPU Schematics (CDC)
MPC8555E Configurable Development System Reference Manual, Rev. 1
H-30 Freescale Semiconductor
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor I-1
Appendix ICDS I/O Board SchematicsThis appendix provides CDS I/O board schematics.
6/11/2004
9:30:23 amfreescaleFreescale Semiconductor
semiconductor
TM
IOCard
Gary Milliorn 011.1
�CDS_IOCard
Cover StoryDate Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
DATE
Freescale Semiconductor and the Freescale logo are registered
and ground unless explicitly shown otherwise. Global power
All information is subject to change without notice.
05
No warranty, expressed or applied, is made as to the
The sheet-to-sheet cross reference format is:
04
Miscellaneous09
Sheet VertZoneLetter HorizZoneNumber
parts may be used; refer to the bill of materials.
All resistors are SMD0402, in ohms, 0.08W, +/-5%
Block Diagram
GND
of IBM. Other trademarks are the respective property of theirrespective copyright holders.
connections are:
All inductances are in microhenries (uH).
0302
apply (i.e. PCI). Little-endian numbering is noted at the
Initial version
VCC_3.3
All rights reserved. No warranty is made, express or implied.
USB InterfacePart numbers used are for reference only; compatible
CDS Carrier Connector
Board impedance is 55 +/- 5 ohms.
Page
07
the most-significant bit), except where industry standards
All capacitors are SMD0402, in microfarads (uF), +/-20%.
7.
Event Switches
source component.
V1.0
IOCard
VCORE
4.
Components with the label "No_Stuff" are not to be installed bydefault; they are for test or manufacturing purposes only.
3.
VCC_1.2
5.
Unless otherwise specified:
Integrated circuits have default connections to power
trademarks of Freescale Semiconductor. PowerPC is a trademark
All ferrites are Z=50 ohms at 100 MHz.All fuses are self-resetting polyswitch (PTC) devices.
6.
CHANGES
6/11/2004
9:32:25 amfreescaleFreescale Semiconductor
semiconductor
TM
V1.1 04JUN11 Switch and RJ45 pinout fixes.
Cover Page
08
General Information
VCC_5
accuracy of the information contained herein.
01
03SEP25
ContentsSchematic Notes1.
2.
VCC_2.506
This schematic is provided for reference purposes only.
Placement and PCB Stackup
All buses follow big-endian bit numbering order (bit 0 is
Ethernet Ports #3 and #4
REV
Gary Milliorn 021.1
�CDS_IOCard
Information, please.Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
6/11/2004
9:13:59 amfreescaleFreescale Semiconductor
semiconductor
TM
Connectors06
Ethernet RJ45
CDS DC
07
USB PortsConnector
Event Switches
05 08
Gary Milliorn 031.1
�CDS_IOCard
Block DiagramDate Changed:
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Revision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
SW1
SW2
SIGNAL
LAYER 8
COMP
PLANE
0.5oz
0.5oz
SIGNAL: 7
PLANE
SIGNAL
SIGNAL
LAYER 3
LAYER 2
SIGNAL: 6
LAYER 4
PLANE: VCC_3.3
PLANE: GND
0.5oz
0.5oz
SIGNAL: 4
#3
RJ45
SIGNAL: 8
SA
MT
EC
SIGNAL: 5
#4
USB
USB
SIGNAL: 3
PLANE: VCC_2.5
0.5oz
POWER
6/11/2004
9:12:28 amfreescaleFreescale Semiconductor
semiconductor
TM
LAYER 1
0.5oz
0.5oz
SIGNAL
LAYER 5
LAYER 6
LAYER 7
0.25oz
0.5oz
PLANE
0.5oz
0.5oz
PLANE
.062
LAYER 11
LAYER 10
SIGNAL
SIGNAL: 1
PLANE: GND
LAYER 9
SIGNAL
RJ45
Gary Milliorn 041.1
�CDS_IOCard
Placement and StackupDate Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
Gary Milliorn 051.1
�CDS_IOCard
Carrier-to-IOCard ConnectorDate Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
6/11/2004
9:09:53 amfreescaleFreescale Semiconductor
semiconductor
TM
ETHERNET PORT #3
Gary Milliorn 011.1
�CDS_IOCard
Ethernet Ports #3 and #4Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
4/9/2004
1:54:15 pmfreescaleFreescale Semiconductor
semiconductor
TM
ETHERNET PORT #4
1:54:15 pmfreescaleFreescale Semiconductor
semiconductor
TM
USB PORTS #1 and #2
Gary Milliorn 011.1
�CDS_IOCard
USB Ports and PowerDate Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
4/9/2004
Freescale Semiconductor
semiconductor
TM
EVENT 2
EVENT 1
Gary Milliorn 081.1
�CDS_IOCard
Event SwitchesDate Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
6/11/2004
9:53:24 amfreescale
091.1
�CDS_IOCard
MiscellaneousDate Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
6/11/2004
10:19:09 amfreescaleFreescale Semiconductor
semiconductor
TM
POWER
Gary Milliorn
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor J-1
Appendix JCDS uTCOM SchematicsThis appendix provides uTCOM schematics.
uTCOM
CDS_uTCOMTitle Page
1/12/2004
2:20:33 pm
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:MOTOROLA MOTOROLA INC.7700 W. Parmer LnAustin, Texas 78729
Mark S. Harris 011.0
�
No warranty, expressed or applied, is made as to theaccuracy of the information contained herein. ContactMotorola Sale/FAEs to obtain the latest information onthis product.
Carrier-to-uTCOM Connector, 1st page05
uTCOM Adapter
Carrier-to-uTCOM Connector, 2nd page06ADS Local Bus CPLD07CPLD pull-ups/pull-downs08
10 TCOM Connectors11 USB Interface12 Logic Analyzer Connectors
Title:Date Changed:
Time Changed:Page:
Project:MOTOROLA MOTOROLA INC.7700 W. Parmer LnAustin, Texas 78729
All buses follow big-endian bit numbering order (bit 0 is
This schematic is provided for reference purposes only.All information is subject to change without notice.
source component.
Board impedance is 55 +/- 5 ohms.
0403
Placement and PCB Stackup
02Block Diagram
01General InformationCover Page
Page ContentsSchematic Notes1.
2.
VCC_3.3VCC_5
3.
4.
5.
6.
7.
VCC_2.5
VCC_1.2
All rights reserved. No warranty is made, express or implied.
GND
VCORE
REV DATE
Engineer:Revision:
CHANGES
X1
CDS_uTCOMGeneral Information
1/28/2004
12:20:17 pm
CPM Signal Swap Area09
28Jan04 Initial version
Unless otherwise specified:
All resistors are SMD0603, in ohms, +/-5%All capacitors are SMD0402, in microfarads (uF), +/-20%.All inductances are in microhenries (uH).
Part numbers used are for reference only; compatibleparts may be used; refer to the bill of materials.
Motorola and the Motorola logo are registered trademarks of Motorola. PowerPC is a trademark of
All ferrites are Z=50 ohms at 100 MHz.All fuses are self-resetting polyswitch (PTC) devices.
Integrated circuits have default connections to powerand ground unless explicitly shown otherwise. Global powerconnections are:
The sheet-to-sheet cross reference format is:Sheet VertZoneLetter HorizZoneNumber
IBM. Other trademarks are the respective property of theirrespective copyright holders.
Components with the label "No_Stuff" are not to be installed bydefault; they are for test or manufacturing purposes only.
the most-significant bit), except where industry standardsapply (i.e. PCI). Little-endian numbering is noted at the
Mark S. Harris 021.0
�
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:MOTOROLA MOTOROLA INC.7700 W. Parmer LnAustin, Texas 78729
CPM Signal Swap Area
<09>
CDS_uTCOMBlock Diagram
1/28/2004
2:15:53 pm
USB,
<11>
USB Connector
Banjo Headers
TCOM LB ConnectorTCOM CPM Connector
<10> <10>
ADS CPM CPLD
<07-08>
<05-06>
uTCOM Connector
Logic Analyzer
<12>
Mark S. Harris 031.0
�
0.5oz
0.5oz
0.5oz
SOLDER
SIGNAL
PLANE
PLANE
Title:
SIGNAL: 4
PLANE: VCC_3.3
0.5oz
0.5oz
0.5oz
0.5oz
0.5oz
LAYER 1
LAYER 2
LAYER 3
LAYER 4
LAYER 5
LAYER 6
LAYER 7
LAYER 8
LAYER 9
0.5oz
Page:Date Changed:
Time Changed:Engineer:
Revision:
0.5oz
PLANE
7700 W. Parmer Ln
SIGNAL
LAYER 12
.062
COMP
PLANEBURIED CAPACITANCE LAYER
PLANE: GND
BURIED CAPACITANCE LAYER
SIGNAL: 2
SIGNAL: 6
PLANE: GND
PLANE: VCC_5
SIGNAL: 5
1.0
�CDS_uTCOM
Placement and PCB Stackup2/18/2004
6:22:57 pm
LAYER 11 PLANE
LAYER 10
PLANE: GNDPLANE 0.5oz
Project:MOTOROLA MOTOROLA INC.
Austin, Texas 78729
SIGNAL: 3
SIGNAL: 1
SIGNAL
SIGNAL
0.5oz PLANE: GND
Mark S. Harris 04
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:MOTOROLA MOTOROLA INC.7700 W. Parmer LnAustin, Texas 78729
Mark S. Harris1.0
05CDS_uTCOM
�
Carrier-to-uTCOM Connector2/18/2004
2:40:22 pm
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:Mark S. Harris 06
1.0
�CDS_uTCOM
Carrier-to-uTCOM Connector2/18/2004
2:46:19 pm
Project:MOTOROLA MOTOROLA INC.7700 W. Parmer LnAustin, Texas 78729
B idir
ADS_BLA21_PU
ADS_D_SELRSTXD2_PD
ADS_D_ATM1_PD
ADS_BLA22_PU
ADS_D_FE2_PD
ATMEN*
ADS_D_PC21_CKEN_PDADS_D_PC20_EXP_EN_PD
ADS_D_CNT_PDADS_D_DRACO_PD
ADS_INPUT_GCLRN_PDADS_INPUT_OE2_GCLK2_PD
TDO ADS_D_SELRSTXD1_PD
S chem atic N otes
MOTOROLA
TDI
Austin, Texas 78729Page:Title:
to the M S IL design on the A D S board
TMSTCLK
Date Changed:
Time Changed:Engineer:
TOOLID(0:3)
ADS_LBBOE2*
DS3_RT2*ENDS3_1ENDS3_2
ATMRST*
Inputs
F P G A S IG N A LS
ADS_D_UTP1_UTP2_PDADS_D_RS232_1_PD
LB_WE*(0)ADS_D_SELRSRXD2_PD
TOOLREV(0:3)
ADS_D_RS232_2_PD
ADS_D_ATM2_16_PD
DS3_TR1*DS3_RT1*
ADS_BLA20_PU
2/18/2004
5:52:37 pm
ADS_LCS0_PUADS_LCS3_PU
* A D S F P G A pinout is identical
Revision:
Project:
ADS_D_ATM2_8_PD
RST_ADS_SRESET*
LB_A_(29:31)
LB_D(0:7)
DS3_TR2*
JT A G
LB_CS*(4)LB_CS*(7:6)uTCOM_RST*
ADS_D_SELRSCTS2_PD
MOTOROLA INC.7700 W. Parmer Ln
LB_GPL(2)
ADS_D_SELRSCTS1_PD
O utputs U nused Inputs
FETHRST*
ADS_D_FE3_PD
Mark S. Harris 071.0
�CDS_uTCOM
ADS Local Bus FPGA
* P lace near the C P LD .
* LB expansion connector signals
* P lace nearexpansion connector
* A D S C P LD inputs and outputs
* P lace near the A D S C P LD
Austin, Texas 78729
Project:MOTOROLA Date Changed:Mark S. Harris 08
1.0
�CDS_uTCOM
Expansion Connector and CPLD Termination2/18/2004
2:53:45 pmTime Changed:Engineer:
Revision:Page:Title:
* U nused A D S C P LD inputs
* P lace near the A D S C P LD
* Inputs to A D S C P LD from expansion connector
MOTOROLA INC.7700 W. Parmer Ln
Austin, Texas 78729Page:
Project:MOTOROLA MOTOROLA INC.
Revision:7700 W. Parmer Ln CPM Signal Swap Area2/18/2004
2:58:37 pmTitle:
Date Changed:
Time Changed:Engineer: Mark S. Harris 09
1.0
�CDS_uTCOM
KEYSIDE
CONNECTOR
D 1
5V5V
GNDGND
V P P _IN (N C )
1. IR Q 6+ 7 m ust not be actively
A 31
B 32
B 31
C 32D 32
D 31
D 2GND
5V
A 2PD30
B 2
ADDR17B 2
C 31
A 31
Title:Project:
3.3VPA1
PA30
C 2GND
C 2
ERNI023762
C 32
Time Changed:
GNDB 32
Revision:Page:
CONNECTORKEYSIDE
CONNECTOR
C 31
LOCALBUSSIGNALS
CPMSIGNALS
D 1
ERNI023762
A S V IE W E D F R O M T O P E D G EO F uT C O M A D A P T E R C A R D
ADDR16
Engineer:
GNDPC1
GND
S C H E M A T IC N O T E S
KEYSIDE
uTCOMBOARD
D ouble check orientation
D 32
D 31NC
PC0
PD31
GNDA 1B 1
GND
CONNECTOR
B 1
C 1
driven because of open drain outputson the expansion card
2. V P P _IN w as a 12V pow er input to supplythe A D S board for flash program m ing
A 2
PC30
PA31PB31
5VNC
GND
TCOM Connectors1/29/2004
11:49:00 am
PB30D 2
A 32
B 31
PC31A 1
Date Changed:
C 1
KEYSIDE
A 32
Austin, Texas 78729MOTOROLA MOTOROLA INC.
7700 W. Parmer Ln
3.3VPA0
Mark S. Harris 101.0
�CDS_uTCOM
Time Changed:MOTOROLA MOTOROLA INC.
Austin, Texas 787297700 W. Parmer Ln Engineer:
Revision:Page:Title:
Project: Date Changed:Mark S. Harris
1.011
CDS_uTCOM�
USB Interface2/18/2004
3:08:10 pm
Mark S. Harris1.0
12CDS_uTCOM
�
Visibility2/18/2004
3:10:18 pm
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:MOTOROLA MOTOROLA INC.7700 W. Parmer LnAustin, Texas 78729
CDS uTCOM Schematics
MPC8555E Configurable Development System Reference Manual, Rev. 1
J-14 Freescale Semiconductor
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor K-1
Appendix KCDS Arcadia BOMThis appendix provides Arcadia X3 BOM for Rev. 3.1.
Board Station BOM file Updated on 08/19/05
date : June 30, 2005; 15:09:37 Arcadia Rev X3.1
Variant : No_Stuff
ITEM_NO COMPANY PART NO. GEOMETRY COUNT DESCRIPTION REFERENCE
1 PCB_arcadia 1
2 0603YC104JAT2A cc0603 12 cap, 0.1uF, AVX, 5% C11 C12 C14 C15
C18 C19 C20 C21
C22 C23 C30 C31
3 102972-2 header_1x2 10 header.1x2, AMP J10 J11 J13 J14
J15 J16 J17 J18
J20 J23
4 102972-3 header_1x3 4 header.1x3, AMP J21 J25 J27 J28
5 103309-7 header_2x17_shrouded 1 header.2x17, AMP J19
6 103309-8 header_2x20_shrouded 2 header.vertical.shrouded.2x20, AMP J22 J26
7 120521-1 recp2x32_amp_fh 3 conn.2x32.ieee1386, AMP J6 J7 J8
8 120591-1 conn_battery 1 conn.battery, Keystone J24
9 145154-4 conamp_145154_4 2 pciconn_5V_32bit_block, AMP SLOT6 SLOT7
10 145165-1 conamp_univ_14516x 4 pcix_conn_univ_64bit_block, AMP SLOT2 SLOT3 SLOT4
SLOT5
11 1469002-1 conn_hmzd_4x10 2 conn.amp.HM-Zd.40pr.plug.vert, Tyco P3 P4
12 218-8LPST sw_som16 3 sw.8spst.cts, CTS SW1 SW2 SW3
13 223955-2 conamp_223955-2 4 conn.pwr.3pos.vert, AMP P5 P6 P7 P8
14 223985-1 guide_pin 4 guide_pin.keyed, AMP P1 P2 P9 P10
15 293D106X9016C2T cct6032 5 cap_tant, 10uF, SPRAGUE, 10% C261 C266 C275
C298 C302
16 293D226X9016C2T cct6032 7 cap_tant, 22uF, SPRAGUE, 10% C89 C154 C155 C216
C231 C276 C287
17 293D476X9016D2T cct7343 2 cap_tant, 47uF, SPRAGUE, 10% C291 C296
18 39-29-3206 atxpwr_2x10_vert 1 atxpwr_2x10vert_nopeg, Molex J12
19 39-29-9042 conn_atx12v_2x2 1 atxpwr_12v_2x2vert, Molex J9
20 440173-3 conn_dual_stacked_din 1 conn.din6.dual.stacked.ra, AMP J3
21 597-5312-40X led_0603 17 led, Dialight D1 D2 D3 D4 D5 D6
D7 D8 D9 D10 D11
D12 D13 D14 D15
D16 D17
22 74AHCT74DB so14 1 74ahct74db.sso14, TI U30
23 74LVT244APW tssop20 1 74lvt244.tssop20, Phillips U32
24 APA150-FG256 fbga256 1 apa150.1of2.fbga256, ACTEL U14
25 BAS16LT1 sot23 4 bas16lt1.sot23, MOT CR4 CR5 CR6 CR7
26 DEM9PL conn_db9_plg_ra 2 conn.db9.plug.rta, ITT Cannon J1 J2
27 ECE-V1CA331P lytic_case_g 1 cap_lytic, 330uF, Panasonic, 20% C210
28 ECPSM310T1_32_768KTR sm_xtal_4p 1 smdxtal_32kHz, Ecliptek Y5
29 EH2645TS-133.000M osc_smd_5x7mm 1 osc.3_3v.smd, 133.33MHz, Ecliptek U11
30 EMK107F224ZA cc0603 8 cap, .22uF, TAIYO_YUDEN, +80-20% C2 C3 C4 C5 C107
C111 C218 C224
31 EXCCL4532U1 induct_4532 19 exccl4532.smd, PANASONIC F1 F2 F4 FB1 FB2
FB3 FB4 FB5 FB6
FB7 FB8 FB9 FB10
FB11 FB12 FB13
FB14 FB15 FB16
32 FPX250F-20 crystal_4pin_smd 1 crystal_4pin.smd, 25MHZ, FOX Y1
33 FTSH-113-01-L-DV-K conn_2x13_050_sma 1 conn.2x13, Samtec J5
34 GRM39X7R104K050AD cc0603 1 cap, 0.1uF, muRATA, 10% C300
35 GSP-B-S2-GG-9100 rj45led_usbdual_over_ra 1 conn.rj45led_over_dualusb.ra, KYCON J4
36 HC49SD33.333 crystal_2pin_smd 1 crystal.2pin.smd, Fox Y3
37 HF30ACB453215-T induct_4532 2 ferrite, TDK F5 F6
38 IS24C02-3G so8 2 is24c02-3g.so8, ISSI U26 U27
39 LM393M so8 1 lm393m.so8, NATIONAL U13
40 LMK107F105ZA cc0603 1 cap, 1.0uF, TAIYO_YUDEN, +80-20% C272
41 LT1117CST-3.3 sot223 1 lt1117cst_3.3.sot223, Linear Tech. U31
42 LT1331CG ssop28 2 lt1331cg.ssop28, Linear U1 U2
43 MBRS360T3 smc_403 3 mbrs360t3.smb, ONSEMI CR1 CR2 CR3
44 MCCA104K0NRT cc0402 216 cap, 0.1uF, SMEC, 10% C8 C26 C29 C32 C33
C35 C36 C40 C42
C43 C44 C45 C46
C49 C50 C51 C52
C53 C54 C55 C56
C57 C60 C61 C62
C63 C64 C65 C66
C69 C70 C71 C72
C75 C76 C78 C79
C80 C81 C82 C83
C84 C85 C86 C87
C88 C90 C91 C92
C93 C94 C95 C96
C97 C98 C99 C100
C101 C102 C103
C104 C105 C108
C109 C110 C114
C116 C117 C118
C119 C120 C121
C122 C123 C124
C125 C126 C127
C128 C129 C130
C131 C132 C133
C134 C135 C136
C139 C142 C143
C144 C145 C146
C147 C148 C149
C150 C151 C152
C153 C156 C157
C158 C159 C160
C161 C162 C163
C164 C165 C166
C167 C168 C169
C170 C171 C172
C173 C174 C175
C176 C177 C178
C179 C180 C181
C183 C185 C187
C189 C190 C192
C193 C194 C195
C196 C197 C198
C199 C200 C201
C202 C203 C204
C205 C206 C207
C208 C209 C211
C212 C213 C214
C215 C217 C219
C220 C221 C222
C223 C225 C226
C227 C228 C229
C230 C232 C233
C234 C235 C236
C237 C238 C239
C240 C241 C242
C243 C244 C245
C246 C247 C248
C251 C252 C253
C254 C255 C256
C257 C258 C259
C260 C262 C263
C264 C267 C268
C269 C270 C273
C274 C277 C279
C280 C281 C282
C284 C285 C286
C290 C293 C294
C295 C301 C303
45 MCCA180K0NRT cc0402 2 cap, 18pF, SMEC, 10% C24 C25
46 MCCA270K0NRT cc0402 7 cap, 27pF, SMEC, 10% C1 C13 C16 C17 C27
C28 C34
47 MCCA470K0NRT cc0402 5 cap, 47pF, SMEC, 10% C6 C7 C9 C10 C278
48 MCCE100JONRT cc0402 2 cap, 10pF, muRATA, 5% C265 C271
49 MCR03-EZH-F-49R9 rc0603 4 res, 49.9, Rohm, 1% R10 R11 R12 R13
50 MIC2526-2 so8 1 mic2526_2.so8, MICREL U3
51 MIC29152BU to263_5p 1 mic29152bu.to263_5, MICREL U20
52 MMBT3904 sot23 1 mmbt3904_npn.sot23, Motorola Q1
53 MNR14-EOAB-J-102 rnet1632 1 rnet, 1K, Rohm, 5% RN17
54 MNR14-EOAB-J-330 rnet1632 12 rnet, 33, Rohm, 5% RN25 RN26 RN27
RN28 RN29 RN30
RN31 RN32 RN33
RN34 RN35 RN36
55 MPC9109FA lqfp32 1 mpc9109fa.lqfp32, Freescale U24
56 MPC9855VF bga_10x10 1 mpc9855.bga_10x10, Freescale U25
57 NOT_A_COMPONENT tp_pth 9 test.pth, None TP1 TP2 TP3 TP4
TP5 TP6 TP7 TP8
TP9
58 RC73A2Z1000FT rc0402 1 res, 100, SMEC, 1% R275
59 RC73A2Z1002FT rc0402 2 res, 10.0K, SMEC, 1% R41 R45
60 RC73L2Z000JT rc0402 7 res, 0, SMEC, 5% R34 R40 R198 R201
R244 R245 R147
61 RC73L2Z050JT rc0402 1 res, 5, SMEC, 5% R33
62 RC73L2Z100JT rc0402 1 res, 10, SMEC, 5% R58
63 RC73L2Z101JT rc0402 4 res, 100, SMEC, 5% R18 R19 R291 R294
64 RC73L2Z102JT rc0402 22 res, 1K, SMEC, 5% R15 R16 R17 R27
R35 R56 R88 R110
R125 R126 R145
R204 R220 R229
R238 R243 R254
R261 R265 R273
R281 R285
65 RC73L2Z103JT rc0402 13 res, 10K, SMEC, 5% R28 R29 R30 R197
R202 R203 R221
R224 R228 R235
R264 R282 R283
66 RC73L2Z471JT rc0402 1 res, 470, SMEC, 5% R66
67 RC73L2Z153JT rc0402 4 res, 15K, SMEC, 5% R2 R4 R6 R9
68 RC73L2Z220JT rc0402 4 res, 22, SMEC, 5% R32 R189 R196 R280
69 RC73L2Z221JT rc0402 18 res, 220, SMEC, 5% R5 R54 R185 R186
R246 R249 R250
R251 R255 R256
R257 R258 R259
R260 R262 R270
R271 R272
70 RC73L2Z222JT rc0402 2 res, 2.2K, SMEC, 5% R31 R55
71 RC73L2Z270JT rc0402 4 res, 27, SMEC, 5% R1 R3 R7 R8
72 RC73L2Z272JT rc0402 2 res, 2.7K, SMEC, 5% R22 R24
73 RC73L2Z330JT rc0402 33 res, 33, SMEC, 5% R20 R26 R36 R37
R38 R39 R43
R148 R149 R150
R151 R152 R153
R156 R175 R176
R177 R179 R180
R182 R183 R190
R191 R192 R193
R194 R266 R267
R274 R286 R288
R292
74 RC73L2Z331JT rc0402 5 res, 330, SMEC, 5% R14 R205 R241 R242
R253
75 RC73L2Z332JT rc0402 2 res, 3.3K, SMEC, 5% R237 R278
76 RC73L2Z470JT rc0402 1 res, 47, SMEC, 5% R231
77 RC73L2Z471JT rc0402 6 res, 470, SMEC, 5% R69 R222 R269 R276
R287 R295
78 RC73L2Z472JT rc0402 39 res, 4.7K, SMEC, 5% R25 R100 R178 R181
R184 R195 R199
R200 R206 R207
R208 R209 R210
R211 R212 R213
R214 R215 R216
R217 R218 R219
R223 R225 R226
R227 R230 R232
R233 R234 R239
R240 R247 R252
R268 R279 R289
R290 R293
79 RC73L2Z562JT rc0402 1 res, 5.6K, SMEC, 5% R23
80 RC73L2Z563JT rc0402 1 res, 56K, SMEC, 5% R146
81 RC73L2Z682JT rc0402 1 res, 6.8K, SMEC, 5% R277
82 RC73L2Z750JT rc0402 2 res, 75, SMEC, 5% R263 R284
83 RC73L2Z822JT rc0402 103 res, 8.2K, SMEC, 5% R44 R48 R49 R50
R51 R52 R53 R57
R60 R61 R63 R64
R65 R67 R68 R70
R71 R72 R73 R74
R75 R76 R77 R78
R79 R80 R81 R82
R83 R84 R85 R86
R87 R89 R90 R91
R92 R93 R94 R95
R96 R97 R98 R99
R101 R102 R103
R104 R105 R106
R107 R108 R109
R111 R112 R113
R114 R115 R116
R117 R118 R119
R120 R121 R122
R123 R124 R127
R128 R129 R130
R131 R132 R133
R134 R135 R136
R137 R138 R139
R140 R141 R142
R143 R144 R157
R158 R159 R160
R161 R162 R163
R164 R165 R166
R167 R168 R169
R170 R171 R172
R173 R174
84 RK73H2AT1602F rc0805 1 res, 16K, KOA, 1% R236
85 RM73B1JT050JF rc0603 4 res, 5, KOA, 5% R21 R154 R187 R188
86 RM73B1JT100J rc0603 2 res, 10, KOA, 5% R46 R47
87 RM73B1JT150J rc0603 1 res, 15, KOA, 5% R155
88 RM73B2ETE-100J rc1210 1 res, 10, KOA, 5% R62
89 RNA4A8E102JT rna4a 3 rnet8.bussed.rna4a, 1K, AVX, 5% RN5 RN7 RN9
90 RNA4A8E103JT rna4a 2 rnpullup_3.3v.rna4a, 10K, AVX, 5% RN3 RN10
91 RNA4A8E472JT rna4a 14 rnpullup_3.3v.rna4a, 4.7K, AVX, 5% RN2 RN11 RN12 RN13
RN14 RN15 RN16
RN18 RN19 RN20
RN21 RN22 RN23
RN24
92 RNA4A8E472JT rna4a 3 rnet8.bussed.rna4a, 4.7K, AVX, 5% RN4 RN6 RN8
93 RNA4A8E472JT rna4a 1 rnpullup_vcc5.rna4a, 4.7K, AVX, 5% RN1
94 RTL8139D pqfp100 1 rtl8139d.pqfp100, REALTEK U7
95 SG615P-14.318 osc_smd-sg8002ja 1 osc.smd-sg8002ja, 14.318MHz, EPSON Y4
96 SG615P-48.000 osc_smd-sg8002ja 1 osc.smd-sg8002ja, 48.000MHz, EPSON Y2
97 SMD100 sm_case_c 1 ptc_smd100, RAYCHEM F3
98 SN74CBTD16211CDGGR tssop56 3 74cbt16211dggr.ssop56, TI U16 U17 U18
99 SN74CBTLV1G125DBVR sop5 6 74cbtlv1g125dbv.so5, TI U5 U8 U9 U10 U19
U23
100 SN74LVC1G125DCKR sc70 5 74lvc1g125.sc70, TI U12 U15 U21 U33
U34
101 T510X337M010AS cct_casee 6 cap_tant, 330uF, Kemet, 20% C283 C288 C289
C292 C297 C299
102 TP-105-01-00 tp025 3 tp.black, Components Corporation G1 G2 G3
103 TP12SH9ABE sw_th_spdt 2 sw.1spdt, C&K SW4 SW5
104 TSI310A-133CE pbga304 1 tsi310.1of4.pci_p.pbga304, Tundra U22
105 UWX1C470MCR lytic_case250_smd 26 cap_lytic, 47uF, Nichicon, 20% C37 C38 C39 C41
C47 C48 C58 C59
C67 C68 C73 C74
C77 C106 C112 C113
C115 C137 C138
C140 C141 C182
C184 C186 C188
C191
106 VT82C686B pbga352 1 vt82c686b.1of3.pbga352, VIA U29
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor L-1
Appendix LCDS Arcadia X3 SchematicsThis appendix provides Arcadia X3 schematics for Rev. 3.1.
6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
Austin, Texas 787297700 W. Parmer Ln
C
8765
A
B
D
C
freescaleFreescale Semiconductor
semiconductor
TM Gary MilliornV3.1
01Arcadia
Cover StoryThursday, October 20, 2005
2:49:23 pm
freescalesemiconductor
TM
4321
1 2 3 4 5
07
65
C123
the most-significant bit), except where industry standards
Cover Page
2.
Unless otherwise specified:
Initial version
All rights reserved. No warranty is made, express or implied.
PrPMC Connector
24
All information is subject to change without notice.
South Bridge: IDESouth Bridge: IDE ports
All resistors are SMD0603, in ohms, 0.08W, +/-5%
D
Date Changed:
apply (i.e. PCI). Little-endian numbering is noted at the
Slot2/HIP1 - RapidIO Connectors + Power
Sheet "-" VertZoneLetter HorizZoneNumber
28
10
South Bridge: USB, PS2
D
C
freescaleFreescale Semiconductor
2
Arcadia System Logic
16
The sheet-to-sheet cross reference format is:
11
01DEC04
1918
PCI bridge replaced.
A
B
15APR02
3.0
21
All ferrites are Z=50 ohms at 100 MHz.
PCIB Isolator (PCIB3:PCIB4)
5.
6.
7.
REV
1533pF
Part numbers used are for reference only; compatible
22
Page
VCC_5
3
4.trademarks of Motorola. PowerPC is a trademark of
parts may be used; refer to the bill of materials.
Motorola and the Motorola logo are registered
IBM. Other trademarks are the respective property of theirrespective copyright holders. Under the sycamore trees.
Bypass Capacitors
Slot2/HIP1 - PCI-X Connectors
Board impedance is 55 +/- 5 ohms.
null
General Information
LEDs, Configuration
Revision:Page:
Schematic Notes
08
VCC_2.5
3 41
Project:
Austin, Texas 787297700 W. Parmer Ln
26
Ethernet Controller
All fuses are self-resetting polyswitch (PTC) devices.
Integrated circuits have default connections to powerand ground unless explicitly shown otherwise. Global power
04Main Power, Reset
03Routing and Layout Information
02
Contents
Engineer:
No
_Stu
ff
C
8
B
1.
V3.1 11OCT05 Updates
09 More Clocks
4
Time Changed:
32
20
01
Ethernet IO
connections are:
X2 30JUL02
5 6 7 8
A
06
CHANGES
X1
Slot 6: PCI 33 MHz
source component.
All capacitors are SMD0603, in microfarads (uF), +/-20%.
Clocks
Arcadia System Logic
Freescale Sale/FAEs to obtain the latest information on
Block Diagram
3.
Updates.
33
null1
All buses follow big-endian bit numbering order (bit 0 is
Slot5/HIP2 - PCI-X ConnectorsSlot5/HIP2 - RapidIO Connectors + Power
GNDVCC_3.3
05
13
30
17 South Bridge: Serial Ports
This schematic is provided for reference purposes only.
Information, PleaseThursday, October 20, 2005
2:49:55 pm
this product.
No warranty, expressed or applied, is made as to theaccuracy of the information contained herein. Contact
Components with the label "No_Stuff" are not to be installed bydefault; they are for test or manufacturing purposes only.
semiconductor
TM
27 PCI3-PCI4 Isolator
31Slot 7: PCI 33 MHz
Title:
14
South Bridge: Miscellany
7
Slot 4
PCI-X Bridge: Primary PortPCI-X Bridge: Secondary Port
29
21
PCI-X Bridge: Power23
All inductances are in microhenries (uH).
DATE
PrPMC Connector
25
PCI-X Bridge: Control Logic
12
Gary MilliornV3.1
02Arcadia
1
1 2
semiconductor
TM
PCI Config
System Clocks
<09>
RapidIO
66 MHz 3V BUS
76
33 MHz 5V BUS
System Control
Slot #333-66 MHz
<18-19>
3 4
PCI/PCI-X
<25-26>
1GHz
Slot #233-66 MHzPCI/PCI-X
<27>
1GHz
<29-30>
PCI Bridge
PCI33 MHz
Slot #5
<32>
PCI
432
<10-11><31>
7700 W. Parmer LnAustin, Texas 78729
C
8
33 MHz
Slot #6
PCI / PCI-X
5
PCI/PCI-X
CPU, Mem & PCI
<06-07>
IOUSB/IDE/PS2/SER/FloppyVIA South Bridge
<13-16>
RapidIO
freescaleFreescale Semiconductor
System Power Supply
Realtek
<20>
A
B
D
Date Changed:
Bu
ffer
Ethernet33-66 MHz
PrPMC33 MHz
ArcadiaBlock Diagram
Thursday, October 20, 2005
2:50:26 pm
<21-24>
A
B
D
C
<24>
OmniBus
<28>
Slot #4/HIP #233-66 MHzPCI/PCI-X
33 MHz 3V BUS
Slot #1/HIP #133-66 MHz
5 6 7 8
Revision:Page:Title:
Project:
Iso
lati
on
2.5V @ 2 A
Time Changed:Engineer:
33 MHzPCI
Gary Milliorn 03V3.1
7700 W. Parmer Ln
PC
I 5V
32b
PC
IX 3
V 6
4b
8
VIA
Rapid
HIPSLOT HIPSLOT
TSI310
DIN6
12
PC
I-X
Rapid
654321
RTK8139
AT
X
3 4 5 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
MP
MC
PlacementThursday, October 20, 2005
2:52:01 pm
IOIO
USB
Dual
1 2
Austin, Texas 78729
C
A
B
D
C
freescaleFreescale Semiconductor
semiconductor
TM
PC
I-X
PC
I-X
AT
X
Project:
over
CPLD
PC
IX 3
V 6
4b
MP
MC
Exp
ansio
n
PC
I 5V
32b
ENET
7
Align per Gasket #4, #21 or #40
Gary MilliornV3.1
04Arcadia
AT
X P
OW
ER
Local Power Switch
765
7700 W. Parmer LnProject:
Standby Power LED
ATX Chassis Header
Austin, Texas 78729
C
Page:
D
Force PSU On Always
A
B
5
ATX Chassis HeaderPower LED Cable
8
ATX Chassis PowerRoute VCC and VCC3.3 on
4
Freescale Semiconductor
semiconductor
TM
1 2
3
6 7 8
A
Title:
Debug Mode
GROUND TEST POINTS
System Reset Switch
ATX Chassis Header
Chassis Mounting Holes
1
C
freescale
D
Gary MilliornV3.1
05Arcadia
Power Entry, ResetThursday, October 20, 2005
2:52:52 pm
(3V)
Local Reset Switch
ATX Chassis Header
System Power Switch
B
separate planes.
Optional
Date Changed:
Time Changed:Engineer:
3 4
2
Revision:
sw.1spdtSW4
12
3
2
3
VCC_3.3
10uFC296
+
VCC_HOT_5
MH4
6B8
POWER
header.1x3
J221
VCC_5
sw.1spdtSW5
12
3
MH8
RESET
J191
2
VCC_5
MH2
POWER
J211
2
4.7K
R230
+
VCC_12N
C291330uF
25V
+
J10atxpwr_12v_2x2vert
1GND1
2GND2 P12V3
3P12V4
4
VCC_12 VCC_3.3
25V
330uFC292
Q1
sot23
MMBT390413D8
G5tp.black
0.1uFC297
R281
22
R277
100
C196330uF
25V
+
MH5tp.black
G2
C274
330uF
25V+
10B1,13D1
tp.blackG3 MH10
25V
330uFC300
+
MH6
R276
470
C298330uF
25V
+
4.7K
R90
470
R228
VCC_12
G4tp.black
MH3G7tp.black
VCC_5
C26010uF
+
16B1
VCC_P4
6VCC_P6
9VSTDBY
1K
R227
MH9
15GND_P15
16GND_P16
GND_P1717
3GND_P3
5GND_P5
7GND_P7
14PS_ON
8PWRGOOD
19VCC_P19
20VCC_P20
4
J15atxpwr_2x10vert_nopeg
10+12V_P10
1+3.3V_P1
11+3.3V_P11
2+3.3V_P2
12-12V_P12
18-5V_P18
13GND_P13
2B
4
GND3
OE1
VCC5
VCC_3.3
VCC_3.3
R280
6.8K
sop5
U24
74cbtlv1g125dbv.so5
A
3.3K
R282
MH1
STDBY
J131
2
R283
4.7K
J14
ON
1
2
VCC_5
MH7
2CM_MAX
<,,,annot_deleted,>
G6tp.black tp.black
G1
SUSC*
RESTART*
NC
2CM_MAX
PWRSW*
NC
1CM_MAX
2CM_MAX
2CM_MAXPWRGD
See MapFile
GND
Project:
B
D
C
6
7700 W. Parmer LnAustin, Texas 78729
C
A
8765432
TM
1
1 2
freescaleFreescale Semiconductor
semiconductor
ACTEL PROGRAMMING HEADERLocate within 3" of device.
3 4 5
Gary MilliornV3.1
06Arcadia
System Logic, part 1Friday, October 21, 2005
4:00:31 pm
7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
C1040.1uF
0.1uFC46
VCC_3.3
10C8
24
25 26
3 4
5 6
7 8
9
15 16
17 18
19
2
20
21 22
23
R15
P14VPP
J6conn.2x13
1
10
11 12
13 14
L10VDD_15
J11VDD_16
F8VDD_2
VDD_3F9
F10VDD_4
G6VDD_5
G11VDD_6
H6VDD_7
H11VDD_8
VDD_9J6
VPN
F5
F12VDDP_6
G5VDDP_7
VDDP_8G12
VDDP_9K5
F7VDD_1
K6VDD_10
VDD_11K11
VDD_12L7
L8VDD_13
L9VDD_14
VDDP_1
K12VDDP_10
VDDP_11L5
L12VDDP_12
VDDP_13M6
VDDP_14M7
VDDP_15M10
VDDP_16M11
VDDP_2E7
E10VDDP_3
VDDP_4E11
VDDP_5
IO_F16F16
F2IO_F2
IO_F3F3
F4IO_F4
RCKN14
P13TCK
R14TDI
R16TDO
T15TMS
TRSTP15
E6
IO_E16
IO_E2E2
IO_E3E3
E4IO_E4
IO_E5E5
E8IO_E8
IO_E9E9
IO_F1F1
IO_F13F13
F14IO_F14
F15IO_F15
D4
D5IO_D5
IO_D6D6
D7IO_D7
IO_D8D8
D9IO_D9
IO_E1E1
E12IO_E12
IO_E13E13
E14IO_E14
IO_E15E15
E16
D1IO_D1
IO_D10D10
D11IO_D11
IO_D12D12
D13IO_D13
IO_D14D14
IO_D15D15
D16IO_D16
IO_D2D2
D3IO_D3
IO_D4
C14
IO_C15C15
C16IO_C16
C2IO_C2
IO_C3C3
C4IO_C4
IO_C5C5
C6IO_C6
IO_C7C7
C8IO_C8
IO_C9C9
B5IO_B5
IO_B6B6
B7IO_B7
IO_B8B8
B9IO_B9
IO_C1C1
C10IO_C10
IO_C11C11
C12IO_C12
IO_C13C13
IO_C14
IO_B1
IO_B10B10
B11IO_B11
IO_B12B12
B13IO_B13
IO_B14B14
B15IO_B15
IO_B16B16
B2IO_B2
B3IO_B3
IO_B4B4
IO_A13
IO_A14A14
A15IO_A15
A2IO_A2
IO_A3A3
A4IO_A4
IO_A5A5
IO_A6A6
A7IO_A7
IO_A8A8
A9IO_A9
B1
U14
apa150.1of2.fbga256
H4AGND_1
AGND_2H15
AVDD_1J3
AVDD_2J15
IO_A10A10
A11IO_A11
IO_A12A12
A13
0.1uFC103
0.1uFC116
15A1
9B8,20D7
16V
C5
0.1uF
11C1,18D1,31A1,32A1
0
1
2
22D1
0.1uFC91
14C1
0.1uF
10uFC2
+
10C8
3
10C8
10C8
0.1uF
C3
16V
C92
3
1
2
11A1
11A1,23C1,26A8,27A8,28A8,30A8,31A8,32A8
32A8
11C8
C1090.1uF
1
0
0.1uFC118
25V
DD
1
VD
D2
32
VS
S1
16 28V
SS
2
(A5)WP7
3
2
1
10C8
22NC2
NC326
27NC4
18RES1(DQ4)
(DQ5) RES219
20RES3(DQ6)
(DQ7) RES421
RST2
8TBL A4)
INIT (OE)
13LAD0(DQ0)
(DQ1) LAD114
15LAD2(DQ2)
(DQ3) LAD317
31LCLK (R_C*)
(WE)LFRAME23
MODE29
NC11
5(A8)GPI2
4(A9)GPI3
3
30GPI4 (A10)
12ID0 (A0)
11ID1 (A1)
10ID2 (A2)
9ID3 (A3)
24
C1010.1uF
13B8
13D8
lpc_flash
U4
SST49LF004B-33-4C-NHE
plcc32_skt
(A6)GPI06
(A7)GPI15
0.1uFC102
3
11B8,23C1,26A8,27A8,28A8,30A8,31A8,32A8
C860.1uF
C90.1uF
0
R47
No_Stuff
10.0K
R49VCC_3.3
3
10D8
11A1,23C1,26A8,27A8,28A8,30A8,31A8,32A8
R44
10.0K
4
8C1
21D1,26A1,27A1,28A1,30A1
10C8
5D1
C1210.1uF
2
9D8
26B1,27B1,28B1,30B1
21B1
0.1uFC108
5
10D1
0
10C1
0
C106.22uF
VCC_2.5
R35
C120
13D8
15C1
0.1uFC100
13B8
C1050.1uF
VCC_2.5
VCC_2.5
0.1uF
10B1
0
1
VCC_3.3
5
23B8
0.1uFC85 C84
0.1uF
1K
R38
7
6
10C1
4
10C1
9D8
0R37
2
10C1
R43 0
10D8
10A1
LCLK
PCIB3_INT*(0:3)
SW_SPARE2SW_SPARE1
.22uFC111
PC_B3
LEDS(7:0)
LFRAME*LINIT*
PCIA_FRC0PCIA_FRC1
PCIA_CLKSET(0:5)
10CM_MAX
TMS
10CM_MAX
10CM_MAX
TCK
10CM_MAX
SLOT7_TDO
<,,,annot_deleted,>
10CM_MAX
10CM_MAX
ARC_TDO
PCIA_PCIXS_1PCIA_PCIXS_0PCIA_M66EN PCI_A1
NC
LRST*
LAD(3:0)LAD(3:0)
PCIA_REQ64_DRV* PCI_A1
SCLKRDYCPURST*
VSTATSUSB*
NC
LPCWP*
NC
NC
NC
NC
NC
NC
NC
NC
SIOINT
PCIA_PCIRST* PCI_A1
PCIB_PCIRST* PCI_B4
NC
RSTDRVIDERST*
PRPMC_SYSRST*
PC_B3
10CM_MAX
TRST*
NC
RESTART*
ARC2ARC1ARC0
NC
NC
NC
NC
NC
NC
PC_B3
NC
NC
NC
NC
VIARST*
TSI310_PCIRST_OUT*
PC_B3
NC
NC
NC
ARC_LED
NC
NC
NC
NC
2CM_MAX
NC
10CM_MAX
NC
NC
NC
freescalesemiconductor
TM
5 6 8
Freescale Semiconductor
743
ArcadiaSystem Logic, part 2
Friday, October 21, 2005
3:21:54 pm
21
1 2 3 4 7 85
Page:
6
A
Revision:
D
Time Changed:
B
Project: Date Changed:Engineer: Title:
B
7700 W. Parmer LnAustin, Texas 78729
C
A
D
C
J13
Gary MilliornV3.1
07
IO_T3T3
T4IO_T4
T5IO_T5
IO_T6T6
IO_T7T7
T8IO_T8
IO_T9T9
NPECL1H2
NPECL2H14
J2PPECL1
PPECL2
R5
R6IO_R6
R7IO_R7
IO_R8R8
R9IO_R9
T10IO_T10
IO_T11T11
T12IO_T12
IO_T13T13
T14IO_T14
T2IO_T2
P7
P8IO_P8
IO_P9P9
R1IO_R1
IO_R10R10
R11IO_R11
IO_R12R12
R13IO_R13
IO_R2R2
R3IO_R3
IO_R4R4
IO_R5
P1IO_P1
P10IO_P10
IO_P11P11
IO_P12P12
IO_P16P16
IO_P2P2
P3IO_P3
P4IO_P4
IO_P5P5
P6IO_P6
IO_P7
N13
IO_N15N15
N16IO_N16
N2IO_N2
IO_N3N3
N4IO_N4
N5IO_N5
IO_N6N6
IO_N7N7
N8IO_N8
IO_N9N9
IO_M16
M2IO_M2
M3IO_M3
M4IO_M4
M5IO_M5
M8IO_M8
M9IO_M9
IO_N1N1
N10IO_N10
IO_N11N11
N12IO_N12
IO_N13
L15IO_L15
IO_L16L16
L2IO_L2
L3IO_L3
IO_L4L4
M1IO_M1
M12IO_M12
M13IO_M13
M14IO_M14
M15IO_M15
M16
IO_K1
K13IO_K13
IO_K14K14
K15IO_K15
IO_K16K16
IO_K2K2
K3IO_K3
IO_K4K4
IO_L1L1
L13IO_L13
IO_L14L14
IO_G2
IO_G3G3
G4IO_G4
IO_H12H12
H13IO_H13_GLMX2
IO_H3_GLMX1H3
IO_H5H5
J12IO_J12
IO_J14J14
J4IO_J4
IO_J5J5
K1
GL1H1
GL2J1
GL3J16
H16GL4
IO_G1G1
IO_G13G13
IO_G14G14
IO_G15G15
IO_G16G16
G2
7
1
10
8
20B7,22B1
apa150.2of2.fbga256
U14
2
1
21A1,26B8,27B8,28B8,30B8
0
18
9A8,11B1,13D1,18D1,22D1,31A1,32A1
1
3
21C8
7
6
4
5
3
5
R23
TP2
TP8
24
23
22
20B7,22B1
21C1,26B1,27B1,28B1,30B1
TP4
8B8,21D1,26A1,27A1,28A1,30A16
21A1,26A1,27A1,28A1,30A1
TP3
19
18
4
16
15
2
2
1
20B7,22A1
20B7,22A1
20B7,22B1
TP6
2 33 R48
31
20B7,22B1
21C1,26B1,27B1,28B1,30B1
4
3
TP5
10B1
20B7,22B1
21B1,26A1,27A1,28A1,30A1
21B1,26A1,27A1,28A1,30A1
8D1
R34
22
20D7,22D8
26
3
17
12
11
21D8,26D1,27D1,28D1,30D1
1OE
OUT 3V3.3V4
0
21
20
2
1
TP9
28
U11133.33MHz
GND2
C87+
R36 33
20D7,22A1
21A1,26A1,27A1,28A1,30A1
30
28
0
27
22uF
4
0
2
0
1
21B1,26B8,27B8,28B8,30B8
13
25
3
4
21B1,26A1,27A1,28A1,30A1
9
5
29
C930.1uF
VCC_3.3
1
8C8
TP1
0
320D7,22B1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
NC
PCIA_PAR PCI_A1
14
TP
7
PCI_A1
1CM_MAX
PCI_A1PCIA_DEVSEL*
PCIB_CLK(0:6)
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCIA_AD(31:0)
PCIA_CBE*(7:0)
PCI_A1
PCI_A1PCIA_TRDY*
SHORT_POWER
<,,,annot_deleted,>
MPC9855_RST*
NC
NC
NC
NC
NC
NC
TSIPGM_EN*
2CM_MAXPWR
PCIB3_PERR*
PCIA_REQ*(0:4)
PCIA_GNT*(0:4)
CLKSTATNC
PCIA_FRAME* PCI_A1
PCIA_STOP* PCI_A1
REFCLK
PCIA_CLK(0:5)
PCI_A1PCIA_IRDY*
2CM_MAX
<,,,annot_deleted,> NC
PCIB3_CBE*(3:0)
PCIB3_DEVSEL*PCIB3_TRDY*PCIB3_IRDY*
PCIB3_FRAME*
PCIB3_PARPCIB3_STOP*
PCIB3_SERR*
NC
NC
NC
NC
NC
NC
NC
NC
NC
PCIB3_AD(31:0)
(pu)
(pu)
(pu)
(pu)
(pu)
(pu)
(pu)
(pu)
(pu)
(pu)
(pu)
(pu)
(pu)
(pu)
(pd)
01
(pd)
OSC
2 GHz
PLL
0
1
1
MHz
250
to
0
15.87
(pu/d)
15.87to
250
MHz
(pd)
(pd)
(pd)
(pd)
1
1 2 3
Freescale Semiconductor
6
semiconductor
TM
4 5
D
7 8
A
B
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
3
A
B
D
7700 W. Parmer LnAustin, Texas 78729
PWR
Gary MilliornV3.1
08Arcadia
ClocksWednesday, October 19, 2005
5:53:52 pm
CC
freescale876542
VCC_3.3
0.1uFC218
7B1
4.7KR191
VCC_3.3
10pF
10pF
C249
No_Stuff
4
0.1uFC236
No_Stuff
C248
C2380.1uF
0.1uFC211
H2XTAL_OUT
XTAL_SELE1
TP12
C2340.1uF
J1VDDOB1VDDOB2
J2
VDDOB3J7
J9VDDOB4VDDOB5
J10
K1VDDOB6
K2VDDOB7VDDOB8
K9
K10VDDOB9
H1XTAL_IN
VD
DA
2D
2
VDDOA1A1
A2VDDOA2
A9VDDOA3VDDOA4
A10
B1VDDOA5VDDOA6
B2
VDDOA7B7
B9VDDOA8
B10VDDOA9
H7
VD
D23
H8
VD
D24
K6
C4
VD
D3
C5
VD
D4
C6
VD
D5
C7
VD
D6
C8
VD
D7
VD
D8
C9
VD
D9
D3
VD
DA
1D
1
E8
VD
D13
E9
VD
D14
F3
F8
VD
D15
G3
VD
D16
G8
VD
D17
H3
VD
D18
H4
VD
D19
C3
VD
D2
H5
VD
D20
VD
D21
H6
VD
D22
K7QB1
K8QB2
J8QB3
G2REF_33MHz
REF_OUT0C10
D10REF_OUT1
REF_OUT1_EH10
A6
VD
D1
VD
D10
D8
E3
VD
D11
VD
D12
GN
D8
E10
GN
D9
MRG10
F1PCLKPCLK_N
F2
G9PLL_BYPASS
QA0B6
QA1A7
QA2A8
QA3B8
J6QB0
GN
D13
GN
D14
G4
G5
GN
D15
GN
D16
G6
G7
GN
D17
D5
GN
D2
D6
GN
D3
D7
GN
D4
GN
D5
E4
E5
GN
D6
GN
D7
E6
E7
K3CLK_B1CLK_B2
J4
K4CLK_B3
J5CLK_B4
K5CLK_B5
G1CLK_SEL
GN
D1
D4
F4
GN
D10
F5
GN
D11
GN
D12
F6
F7
U27
CLKE2
B3CLK_A0CLK_A1
A3
CLK_A2B4
CLK_A3A4
B5CLK_A4CLK_A5
A5
J3CLK_B0
R155
33
mpc9855.bga_10x10
R190
1
33
R198
C2450.1uF
220
C217.22uF
C224.22uF
TP15
C2460.1uF
C2080.1uF 0.1uF
C207
R157
33
R199
33
C2090.1uF
C2350.1uF
R194
5
C2130.1uF
C2260.1uF
33
33
rc0603
R161 15
1
33
R156
R184
5
4
5
0
3
2
22uFC230+
R193
R1601
7A1
0.1uFC243
4.7KR187
2
3
0.1uFC221
TP
14
C2120.1uF
0.1uFC228
9A1
0.1uFC233
0.1uFC223
2
3
1
C2100.1uF
No_Stuff
P11conn.sma
VCC_3.3VCC_3.3
0.1uFC241
R154
R188
33
C2390.1uF
TP16
33
C227
4
5
6C1
0
0
C2440.1uF
VCC_3.3
0.1uF
R192 220
crystal.2pin.smd
Y3
HC49SD33.333
C2400.1uF
TP13
TP17
7B1,21D1,26A1,27A1,28A1,30A1
SHORT_POWER
PWR SHORT_POWER SHORT_POWER
SHORT_POWER
MPC9855_RST*
1CM_MAX
33
R186
1CM_MAX DEFAULT_NET_TYPE PCIB_CLKSRC
PCICLK_A $PPCICLK_A
1CM_MAX
PCICLK_A$P PCICLK_A
PCIA_CLK(0:5)1CM_MAX
SHORT_POWER
1CM_MAX REFCLK
<,,,annot_deleted,>
1CM_MAX
PCICLK_A
$P PCICLK_A
PCICLK_A
$P PCICLK_A
1CM_MAX
SHORT_POWER
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAXPCIA_CLKSET(0:5)
Title:Project:
2
7700 W. Parmer LnAustin, Texas 78729
PWR
C
A
B
D
C
freescaleFreescale Semiconductor
semiconductor
TM
87654321
1 3 4 5 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Gary Milliorn 09
V3.1
ArcadiaPCI2 Clocks, Misc Clocks, Interrupt Bridge
Wednesday, October 19, 2005
5:59:51 pm
74cbtlv1g125dbv.so5
U8
A2
B4
GND3
OE1
VCC5
5
14C1
R32
10K
C2190.1uF
R183 33
22
20Q9
7VCCI_1
VCCI_221
8VCCO_1
16VCCO_2
VCCO_329
0.1uFC220
13Q14
Q1511
10Q16
Q179
Q230
28Q3
Q427
26Q5
Q624
23Q7
Q8
GN
DO
_4
LVCMOS_CLK3
4LVCMOS_CLK_SEL
6PECL_N
PECL_P5
Q032
31Q1
19Q10
Q1118
15Q12
Q1314
C231
mpc9109fa.lqfp32U26
2G
ND
I
GN
DO
_11 12
GN
DO
_2
GN
DO
_317 25
Y414.318MHz
GND2
1OE1 OUT 3
4VCC
0.1uF
33
R25
5.6K
Y248.000MHz
GND2
1OE1 OUT 3
4VCC
0
13D1
R189
2
1
R182 4.7K
VCC_3.3
1
VCC_3.3
R1585
2.7K
R24
3
6C8,20D70
4
R153 33
3
8C8
0.1uF
R26
2.7K
0
33R159
C259
+C2320.1uF
VCC_3.3
4
GND
VCC
8
VCC_3.3 VCC_3.3
6C1
7A1,11B1,13D1,18D1,22D1,31A1,32A1
C21522uF
26B1,27B1,28B1,30B1
LM393M
U13
2AN
1AO
3AP
BN6
BO7
BP5
74cbtlv1g125dbv.so5
U7
A2
B4
GND3
OE1
VCC5
6
10K
R30
6C1
2
33R152
C2250.1uF
R181 33
26B8,27B8,28B8,30B8
22
R201
33R185
0.1uF
C237
VCC_5 VCC_5
2A
4B
3GND
1OE
5VCC
2.2K
R33
2
3
TP11
10D8
U6
74cbtlv1g125dbv.so5
2A
4B
3GND
1OE
5VCC
VCC_3.3
1
33R180
U9
74cbtlv1g125dbv.so5
SHORT_POWER
PWR
10K
R31
22
R195
PCI_A1
PCI_A1
PCIA_INT*(0:3)
PCI_INT_BRIDGE*
PCI_A1PCIA_PCIXCAP
1CM_MAX
1CM_MAX
PCIA_PCIXS_1PCIA_PCIXS_0
PCIB_CLK(0:6)
NC
<,,,annot_deleted,>
SHORT_POWERNC
NC
1CM_MAX
NC
NC
1CM_MAX
NC
PC_B3
PC_B3
PCIB3_INT*(0:3)PCI_A1
PCI_A1
1CM_MAX
1CM_MAX
$PPCICLK_B
$PPCICLK_B
1CM_MAX
NC
NC
1CM_MAX
NC
NC
1CM_MAX
NC
1CM_MAX
NC
1CM_MAX
1CM_MAXCLK14P318MHZ
USBCLK
PCIB_CLKSRC
PCICLK_B
PCICLK_B
PCICLK_B
PCICLK_B
PCICLK_BPCICLK_B
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
Austin, Texas 78729
C
3
7700 W. Parmer Ln
4
87
A
B
6543
Freescale Semiconductor
D
freescale2
C
semiconductor
TM
1
Gary MilliornV3.1
10Arcadia
Options, LEDsThursday, October 20, 2005
2:39:10 pm
1 2 5 6 7 8
1
R269
220
D3 1
7
6 D11
GreenL3_ARB
2
R57
220
ARCGreen
4 13
5 12
6 11
7 10
8 9
6C8
11C8
2
1
4
0
sw.8spst.ctsSW3
1 16
2 15
3 14
D13
GreenCLK
1
74lvc1g125.sc70
U35220
R266
220
R237
L7_PCIAGreen
D71
6C1
VCC_3.3
220R238
220
L5_PSPD0Green
D51
6C1
6C1
R5
GreenL6_PSPD1
1
VCC_HOT_3.3
R268
220
1
6C8
220
R235
D8
8
9D1
Green2.5V
1
HOT_3VGreen
D15
44
4546
4748
495
506
7
34
3536
3738
39
4 40
4142
43
24
2526
2728
293
30
3132
331516
1718
19
2 20
2122
23
VCC_3.3
J5
header_2x25_05sp
1
10
1112
1314
8
3
4
6B8
2 3
6B8
RN10
2.7K
1 2 3 4
567
12
345
67
8
220
R267
330
RN9
Green
D10
L2_ARC
1
6C1
2 3 4
5678
1
R236
220
4
5678
RN6
2.7K
1
R298
2.7K
RN7
1 2 3
12
345
67
8
220
23
456
78
RN12
3303 4
5678
330
RN13
1
GreenL8_PCIB
1
2.7K
RN11
1 2
115D1
VCC_3.3
R203
220
D6
92Y1
72Y2
52Y3
32Y4
EN11
19EN2
9C1
IDEGreen
D16
1A2
1A36
1A48
181Y1
161Y2
1Y314
1Y412
112A1
132A2
152A3
172A4
22A1
U33
74lvt244.tssop20
21A1
4
15C1
6B8
6B8
D9
GreenL1_VIA
1R239
220
1
U15
74lvc1g125.sc70
2
1
4
7B1
HOT_5VGreen
D17 1
L4_BOOTGreen
D12
0
6D8
6C8
6C8
6B8
1
15C1
5
6C1
VCC_2.5
220
R242
VCC_3.3
14
4 13
5 12
6 11
7 10
8 9
VCC_HOT_5
18D1
21A1
R240
SW2sw.8spst.cts
1 16
2 15
3
330
12
345
67
8
220
74lvc1g125.sc70
U342
1
45B8,13D1
RN8
D14
GreenPWRGD
1
11C1
VCC_3.3
D4
Green3.3V
1
R241
220
NC
NC
NC
NC
NC
NC
LFRAME*
LINIT*
LRST*LAD(3:0)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
LCLK
NC
NC
NC
PCIA_FRC1
PCI_INT_BRIDGE*
MONARCH*
ARC_LED
SBRIDGE_EN*
PCIA_FRC0ENETDIS*
PRPMC_IDSELEN*
NC
1CM_MAX
CLKSTAT
ARC0ARC1ARC2
G0
SW_SPARE2SW_SPARE1
LPCWP*G1
PBRIDGE_EN*
1CM_MAX1CM_MAX
1CM_MAX 1CM_MAX
1CM_MAXIDELED*
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
LEDS(7:0)
1CM_MAX1CM_MAXPWRGD
6
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:7700 W. Parmer LnAustin, Texas 78729
C
A
B
D
C
freescale Gary Milliorn 11V3.1
ArcadiaPrPMC Connectors
Thursday, October 20, 2005
3:35:30 pm
Freescale Semiconductor
semiconductor
TM
B
7
A
8
87654321
1 2 3 4 5
2
4
31
21
15
5
1
0
20B1,31B1,32B1
20B1,31B1,32B1
6B1,23C1,26A8,27A8,28A8,30A8,31A8,32A8
6B1
6B1,23C1,26A8,27A8,28A8,30A8,31A8,32A8
23C1
13C1,18C1,20B1,31A1,32A1
2
VCC_5
4.7KR27
VCC_5
VCC_5
33R28
R29 1K
4
U12
74lvc1g125.sc70
2
1
4
10D8
R21 100
23
6B1,23C1,26A8,27A8,28A8,30A8,31A8,32A8
7A1,9A8,13D1,18D1,22D1,31A1,32A1
VCC_HOT_3.3
13
100R20
20
7
10D8
VCC_3.3
R22
33
10
4
16
VCC_12N
14
13C1,18C1,20B1,31B8,32B8
8
16
13C1,18C1,20B1,31B8,32B8
13D1,18C1,20C1,31B1,32B1
30
4
24
13D1,18C1,20C1,31B1,32B1
18
22
19
28
25
3
1
13C1,18C1,20B1,31A1,32A1
3
3
VCC_12
0
6
12
9
9
13C1,18C1,20B1,31B8,32B8
0
27
17
11
58
59
6
60
61 62
63 64
7 8
48
49
5
50
51 52
53 54
55 56
57
38
39
4
40
41 42
43 44
45 46
47
29
3
30
31 32
33 34
35 36
37
19
2
20
21 22
23 24
25 26
27 28
1
10
11 12
13 14
15 16
17 18
62
63 64
7 8
9
120521-1conn.2x32.ieee1386
J8
51 52
53 54
55 56
57 58
59
6
60
61
43 44
45 46
47M66EN
48
49
5
50
33 34
35 36
37 38
39
4
40
41 42
23 24
25IDSEL
26
27 28
29
3
30
31 32
14
15 16
17 18
19
2
20
21 22
31B1,32B1
6D1
120521-1conn.2x32.ieee1386
J7
1
10
11 12
13
VCC_3.3
1
13A1,18A1,20B1,31D1,32D1
13C1,18C1,20B1,31A1,32A1
18C1,20B1,31B1,32B1
6D1,18D1,31A1,32A1
13C1,18C1,20B1,31A1,32A1
20B1,31A1,32A1
PRPMC_IDSELEN*
23
26
29
13C1,18C1,20B1,31B1,32B1
13C1,18C1,20B1,31A1,32A1
2
PCIB4_REQ64* PCI_B4
PCIB4_GNT*(1:5)
PCI_B4
NC
NC
PCIB4_REQ*(1:5) PCI_B4
1CM_MAX1CM_MAX
PCI_B4
PCI_B4
TRST*
PCIB_CLK(0:5)
PCI_B4 PCIB4_SERR*
ARC_TDO
NC
NC
NCPRPMC_SYSRST*
MONARCH*
NC
NC
TCK
NC
NC NC
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCIB4_TRDY* PCI_B4
PCIB4_PERR* PCI_B4
NC
NC
TMS
PCI_B4 PCIB4_STOP*
PRPMC_TDO
PCIB_PCIRST* PCI_B4
PCI_B4
PCIB4_M66EN PCI_B4
PCIB4_ACK64* PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4PCIB4_DEVSEL*
PCI_B4PCIB4_PAR
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCIB4_LOCK*
PCI_B4
PCI_B4
PCI_B4
PCIB4_FRAME* PCI_B4
PCIB4_CBE*(3:0)
NC
PCI_B4
PCIB4_IRDY*
PCI_B4
PCI_B4
PCIB4_INT*(0:3)PCIB4_AD(31:0)
PCI_B4
PCI_B4
875
A
B
D
C
freescaleFreescale Semiconductor
semiconductor
TM
4321
1 2 3 4 5 6 7 8
A
B
Gary MilliornV3.1
12Arcadia
PrPMC connectorsWednesday, October 19, 2005
6:38:33 pm
D
Date Changed:
Time Changed:Engineer:
Revision:Page:
64-bit PrPMC connectorused for additional 5Vpower only - 64bit PCI notsupported.
Title:Project:
6
7700 W. Parmer LnAustin, Texas 78729
C
7 8
9
VCC_5
56
57 58
59
6
60
61 62
63 64
46
47 48
49
5
50
51 52
53 54
55
36
37 38
39
4
40
41 42
43 44
45
27 28
29
3
30
31 32
33 34
35
17 18
19
2
20
21 22
23 24
25 26
120521-1
1
10
11 12
13 14
15 16
NC NC
NC
NC
J9
conn.2x32.ieee1386
<,,,annot_deleted,>NC
3.3
VC
C_
K9 K10 K11 K12L6 L9 L10 L11L12 M9 M10 M11M12 P6 R6
PCI SuperIO
H15 J15 K15 M15
F15 G15 L15 P15
GND
R15 F6 F11 G6
3.3V
N15 R7 R8 R11
R14 F7 F10 F12
K6 M6 N6
J9 J10 J11 J12
F13 F14 H6 J6
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3VCC_
3.3
VC
C_
3.3VCC_
3.3
VC
C_
3.3VCC_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
A
7700 W. Parmer LnAustin, Texas 78729
B
D
C
freescale
PWR
3:36:12 pm
Freescale Semiconductor
semiconductor
TM
87654321
1 2 3 4 5 6 7 8
A
Date Changed:
Time Changed:
B
D
Engineer:Revision:
Page:Title:Project:
_
C
Gary MilliornV3.1
13Arcadia
System IO: PCI, USB and PS/2Thursday, October 20, 2005
0.1uFC95C273
0.1uF
RN17 4.7K7
6C1
VCC_HOT_3.3
9
0
FB15
VCC_2.5
4.7KRN176
R10
VC
CS
2
F9VCCUSB
VREFT13
VSSHWMR12
T5XDIR_GPO12
37A1,9A8,11B1,18D1,22D1,31A1,32A1
VCC_5
3
USBCLK
B3USBP0N
USBP0PA3
USBP1ND4
C4USBP1P
USBP2NB4
A4USBP2P
E6USBP3N
USBP3PB5
Y6
VB
AT
R9
VC
CS
1
SMI
SOE_GPO13U5
STOPG17
STPCLKW7
SU
SA
_GP
O1
V9
W9
SU
SB
_GP
O2
SU
SC
Y9
TRDYF20
TSEN1W13
Y13TSEN2
V13UN2B
C3
Y11
PW
RB
TN
PW
RG
DW
6
L18REQ
V6
RS
MR
ST
RT
CX
1Y
5
RT
CX
2W
5
SERRG18
T7SLP_GPO7
U9SMBCLK
SMBDATAT9
U6
W8
IRDYF19
V14IRQ0_CHAS_GPIO10
E5KBCK
A5KBDT_KBRC
MSCK_IRQ1D5
C5MSDT_IRQ12
U7NMI
G19PAR
PCICLKE16
PCIRSTB16
IDSELC20
Y8IGNNE
IN12Y14
IN2AU13
W14IN5
T6INIT
A16INTA
INTBD17
C17INTC
B17INTD
INTR
G20C_BE2
F17C_BE3
C19
DEVSELG16
FAN1T12
U12FAN2_GPIO9
V7FERR
FRAMEF18
R13GNDHWM
GNDUSBF8
L19GNT
AD3
AD30C18
AD31A17
K18AD4
K17AD5
AD6K16
AD7J20
J18AD8
AD9J17
V8CPURST
C_BE0J19
C_BE1
E17AD21
D20
D19AD22
D18AD23
AD24B20
A20AD25
AD26A19
AD27B19
AD28A18
AD29B18
K19
J16
H20AD11
AD12H19
AD13H18
H17AD14
H16AD15
F16AD16
AD17E20
E19AD18
AD19E18
K20AD2
AD20
4.7KRN221
vt82c686b.1of3.pbga352
U30
Y7A20M
L17AD0
AD1L16
AD10
1
R200 10K
13
12
R219
4.7K
20
smdxtal_32kHzY5
4
RN22 4.7K6
11D8,18C1,20B1,31B8,32B8
11B1,18C1,20C1,31B1,32B1
11D8,18C1,20B1,31B8,32B8
19D1
19B1
11D8,18A1,20B1,31D1,32D1
VCC_HOT_3.3
8
7
RN17 4.7K4
VCC_3.3
+
C27010pF
11B1,18C1,20B1,31A1,32A1
0
VCC_HOT_3.3
FB14
exccl4532.smd
6D1
10uFC264
11A8,18C1,20C1,31B1,32B1
0
3
2
28
6C8
9B8
FB16
10pFC263
0R205
1
RN22 4.7K3
11C1,18C1,20B1,31B8,32B8 J12
29
R251
16K
exccl4532.smd
FB13
19
4.7K
R207
VCC_5
0.1uFC281
10KR210
24.
7KR
N20
1
C2800.1uF
4.7K
R216
16B8
11B1,18C1,20B1,31A1,32A1
11A8,18C1,20B1,31A1,32A1
22
C254
RN17 4.7K8
3
16C8,26B1,27B1,28B1,30B1,31B1,32B1
16C8,26B1,27B1,28B1,30B1,31B1,32B1
23
31
5C1
5B8,10B1
0.1uF
4.7K
2
30
4.7K
R233
R258
0
RN
20
0.1uFC272
0
R257
18
VCC_3.3
14
R224
4.7K
0.1uFC279
0.1uFC99
3
RN204
R259
10K
25
R196 33
4.7K
27
19C1
19D1
16B8
5
19B1
19B126
19B1
19C1
20
VOE16
VCC_3.3
4.7K3
4.7K
RN
17
5
11
10
11D1,18C1,20B1,31A1,32A1
VCC_HBR_I
16A8
21
16
15
RN20
4.7K
R232
11C8,18C1,20B1,31B1,32B1
J11
6B8
VXD1
17
VCC_3.3
C27510uF
+C2820.1uF
C265
RN22 4.7K2
4.7KRN224
1
FB12
1
0.1uF
R225
4.7K
3
2
0R208
24
16A1
16A1
11B8,18C1,20B1,31A1,32A1
10K
R209
4
PCIB4_REQ*(1:5)PCI_B4
PCIB_CLK(0:5)
FB11
4.7K
R206
PCIB4_PAR
PCIB4_INT*(0:3)
DIFF_PAIR USB_P2NUSB_DP1USB
MCLK
KCLK
USB_DP0USB DIFF_PAIR USB_P1P
USB_DP1USB DIFF_PAIR USB_P2P
DIFF_PAIR USB_P1NUSB_DP0USB
PCI_B4
2CM_MAX
2CM_MAX
2CM_MAX
2CM_MAX
<,,,annot_deleted,>
PCI_B4 SMBCLK
PCI_B4 SMBDAT
CPURST*
2CM
_MA
X
2CM
_MA
X
FANSPD1FANSPD2
2CM_MAX
2CM_MAX
2CM_MAX
PCIB4_DEVSEL*
PCIB4_FRAME*
VIARST*
PCIB4_STOP*
PCIB4_TRDY*
PCIB4_AD(31:0)
PCIB4_CBE*(3:0)
PCIB4_IRDY*
PCIB4_SERR*
PCIB4_GNT*(1:5)
SIOINT
USBCLK
VBAT_3V 2CM_MAX
2CM_MAXPWRBTN*PWRGD 2CM_MAX
2CM_MAXRSMRST*SUSB*SUSC*
KDAT
MDAT
3.3
VC
C_
3.3VCC_
3.3
VC
C_
3.3
VC
C_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3
VC
C_
3.3
VC
C_
3.3VCC_
3.3
VC
C_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3
VC
C_
3.3VCC_
3.3
VC
C_
3.3
VC
C_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3
VC
C_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
3.3VCC_
freescalesemiconductor
TM
87654321
1 2 3 4
PWR
Gary Milliorn 14V3.1
ArcadiaSystem IO: Floppy, IDE
Wednesday, October 19, 2005
6:37:59 pm
5 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729
C
A
B
D
C
3
14
4.7K
3
10
12
6
33 34
4
5 6
7 8
9
1
RN
25
23 24
25 26
27 28
29
3
30
31 32
14
15 16
17 18
19
2
20
21 22
RN284
17C1
J20header.2x171
10
11 12
13
0.1uFC267
10
4.7K
RN23 1
VMW1
VME1
0.1uF
VCC_3.3
4
17C1
15
4.7K
+
19A8
4.7K
RN
26
1
C261
RN28 4.7K7
VCC_5
11
9A8
330uFC283
1K
R265
8
13
10
11
0
VCC_3.3
7
17C1
15
9
C2550.1uF
6
8
9
17C1
C2580.1uF
4.7K
3
R26
333
0
330
R25
4
RN
24
8
RN
154.
7K
1
RN
26
R252
4.7K
VMR1
4.7K
5
0
1
2
15D1
VCC_5
RN
25
4
1
9
12
17B1
TP
204.7K
R226
4.7K
9
2
15D1
4.7K
R24
8
WGATE
A6WRTPRT
RN28 4.7K3
4.7KRN282
SPKR
E8STEP
T10SUSCLK
SUSST1_GPO3V10
H1TC
TRAK00E7
TXD1A11
D10TXD2
US
BIR
QA
_DA
CK
6M
3
N2
US
BIR
QB
_DA
CK
7
WDATAA7
B7
SD2
SD3Y3
W3SD4
SD5V3
SD6Y4
W4SD7
SD8L5
SD9M2
SMEMRA1
SMEMWB1
V5
T1
F2SBHE
SD0Y1
Y2SD1
M4SD10
SD11N1
N3SD12
N5SD13
SD14P1
P2SD15
W2
SA19K1
V1SA2
U3SA3
U2SA4
U1SA5
SA6T4
SA7T3
T2SA8
SA9
R5
R4SA11
SA12R3
SA13R2
R1SA14
P5SA15
P4SA16
P3SA17
SA18K2
C9
V11RING_GPI7
ROMCSC1
RSTDRVJ1
B11RTS1
RTS2E10
B12RXD1
RXD2B10
W1SA0
SA1V2
SA10
LA23
MEMCS16F1
U4MEMR
V4MEMW
MTR0E9
C8MTR1
OSCE4 V12
PCISTP_GPO5
RDATAB6
E3REFRESH
E11RI1
RI2
G2
IRQ
5
IRQ
6_S
LP
BT
NG
1
F5
IRQ
7W
11IR
Q8_
GP
I1H
4IR
Q9
D12IRRX_GPO15
IRTX_GPO14E12
LA20J5
LA21J4
J3LA22
J2
F4
A2IOCHRDY
F3IOCS16
IORD1
IOWC2
K3
IRQ
10K
4IR
Q11
IRQ
14L
1
IRQ
15K
5
IRQ
3G
4
G3
IRQ
4
B8
A8DS1
C6DSKCHG
C12DSR1
DSR2C10
DTR1D11
B9DTR2
HDSELC7
IDE
IRQ
A_D
AC
K0
L2
E1
IDE
IRQ
B_D
AC
K1
D7INDEX
IOCHK_GPI0
DIRD8
DR
Q0
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DR
Q1
E2
H3
DR
Q2_
OC
1_G
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E
D3
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DR
Q5
M1
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N4
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D6DRVDEN1
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CTS1C11
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IOF
DA
CK
3D
2
L4
DA
CK
5
DCD1A12
A10DCD2
0.1uF
13
vt82c686b.2of3.pbga352
U30
PCI Super IO
AENB2
BALE
RN234.7K 2
4.7K
RN
23
3
17C1
C262
19A8
4.7K
RN
26
6
4.7K
RN
26
7
VCC_3.3
RN
264.
7K
2
4.7K
RN
26
4
RN
25
6
RN
254.
7K
7
R223
4.7K
14
RN28 4.7K5
12
4.7K
4.7K1
4.7KRN288
4.7K
RN
27
4
6
1KR
245
RN27
RN21
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3241
8 5 7
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6
13
RN
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8
8
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0T
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8
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4
RN
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RN
244.
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7
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2
15A1
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7
VEN1
11
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55 2
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17A1
17A1
RN
23
R26
24.
7K
17B1
7
RN
274.
7K
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7
R25
34.
7K
R211
330
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RN
23
6
330
R25
5
6D1
12
RN
264.
7K
5
17B1
17B1
17C1
2
6
4.7K
R213
CKS1
2
11
RN
254.
7K
5
TP19
4
RN
274.
7K
5
0
4.7K
RN
27
17A1
R26
41K
RN
234.
7K
R24
94.
7K
J18
2
4
4.7K
R25
0
15
13
4.7K
RN
23
5
4.7K
RN
24
C278
4.7K
R229
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244.
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4.7K
RN
23
8
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3
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8
RN
274.
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7
4.7K
1
14
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284.
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7
1
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17B1
17C1
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RN
244.
7K
3
VCC_5
R220
4.7K
6
15
3
4.7K
R26
1
4.7K
R221
4.7K
RN
24
SDD(15:0)
SD(15:0)
DCD1DSR1
RTS1DTR1TXD1
CTS1
RXD2RI2
DCD2DSR2
RTS2DTR2TXD2
CTS2
RXD1RI1
NC
OC1*OC0*
NC
NC
NC
P_80PIRQ15IRQ14
NC
NC
RSTDRVCLK14P318MHZ
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
shrouded
3.3
VC
C_
3.3
VC
C_
Super IO
shrouded
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
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C_
3.3
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C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
3.3
VC
C_
EXT SMI
7700 W. Parmer LnAustin, Texas 78729
C
A
87654
B
D
C
freescaleFreescale Semiconductor
semiconductor
TM
SECONDARY
PRIMARY
3
PWR
Gary MilliornV3.1
15Arcadia
IDE InterfaceWednesday, October 19, 2005
6:36:51 pm
21
1 2 3 4 5 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
10K
R204
R217
4.7K
1
4.7K
R275
14
VCC_3.3
R214
4.7K
7
0
VCC_3.3
VCC_5
VCC_5
RN194.7K 6
0.1uFC256
R292 33
4.7K RN18 6
VCC_5
8
R290
1K
RN194.7K 8
1
11
54 3 2 1
14
0
bas16lt1.sot23
CR4
8
9
7
33R
N32
876
3536
3738
39
440
56
72526
2728
29 3
30
3132
3334
1516
1718
19
220
2122
2324
J23header_2x20_shrouded
1
10
1112
1314
33
75R270
4 5
CR5
bas16lt1.sot23
1
R274
3
RN184.7K 5
11
15
7
4.7K 1
4.7K RN18 2
4.7K RN18
33R
N30
87654 3 2 1
RN18
7 6 54321
321
2
RN
4033 8
33R
N34
8 7 6 54
0.1uFC268
470
R284
0.1uFC269C266
0.1uF
8
9
10K
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34
3536
3738
39
440
56
7
24
2526
2728
29 3
30
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33 1516
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220
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23
0
J28header_2x20_shrouded
1
10
1112
1314
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470
11
14D8
10C8
4.7K
R215
2
VCC_HOT_3.3
U18
SDDACKV19
SDDREQY20
SDIORW19
SDIORDYV20
W20SDIOW
SLCTE13
E15SLCTIN
SMBALT_GPI6W10
STROBED16
15
A14PRD2
PRD3B14
C14PRD4
PRD5D14
E14PRD6
PRD7A13
U19SDA0
SDA1V18
U20SDA2
SDCS1U17
SDCS3
T17
M20PDDACK
N19PDDREQ
N17PDIOR
N16PDIORDY
PDIOWN18
D13PE
C15PINIT
PME_GPI5T11
B15PRD0
PRD1D15
PDD15
PDD2P20
R17PDD3
R19PDD4
T16PDD5
PDD6T18
PDD7T20
PDD8T19
PDD9
M16
P16PDD0
PDD1P18
PDD10R20
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PDD12R16
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JBYW15
LID_GPI3U10
MSIY19
MSOY18
PDA0M17
M19PDA1
PDA2M18
L20PDCS1
PDCS3
BUSYC13
A15ERROR
Y10EXTSMI
T14GPIOA_GPIO8
GPIODU8
GPO0T8
W16JAB1
JAB2T15
JAXV15
Y15JAY
JBB1
U30W18
ACBTCK
ACKB13
ACRSTU15
ACSDIV17
Y17ACSDI2
ACSDOY16
V16ACSYNC
AUTOFDC16
U11BATLOW_GPI2
RN35
1
2
3
45
6
7
8
vt82c686b.3of3.pbga352
R272
1K
1
33
4.7K 3
13
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10K
4
2
0
13 12
RN19
0
6
14D8
VCC_5
3
J16
1K
R212
4
1
4.7K
R202
4.7K
8765
915
R293
10
7
RN
3133 4 3 2 1
R2711
21
1
2
9
6
4.7K RN16 1
10K
2
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12
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4.7K RN19 5
0
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470
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1
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0.1uFC257
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4.7K
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313
33R
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4.7K 4
10
5
8
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RN164.7K 7
4.7K RN16 8
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4.7K 34.7K RN16 5
4.7K RN16
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5
10B1
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VCC_5
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1
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9
4.7K 3
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6D1
6
1
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R289
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5
6
7
8
R273 33
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1
2
3
4
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G1
IDELED*
2
1
33R291
IDERST*
SDA(2:0)
SDCS(1:0)
NC
NC
VSTAT
NC
NC
P_80P
NCNC
S_80P
PDD(15:0)
NC
PDCS(1:0)
PDA(2:0)
IRQ14
IRQ15
SDD(15:0)
8
GND4
256 x 8 serial EEPROM
VCC_3.3
3.3VCC_
8
GND4
256 x 8 serial EEPROM
VCC_3.3
- +
65
MAC INFO EEPROM
432
6 73 4
A
B
Date Changed:
8
Time Changed:
D
Title:Project:
Page:Engineer:Revision:
B
7700 W. Parmer LnAustin, Texas 78729
C
A
D
C
freescaleFreescale Semiconductor
semiconductor
TM
I2C ADDR=7
I2C ADDR=4
SYSTEM ID EEPROM
81 7
Gary Milliorn 16V3.1
ArcadiaSystem IO: Power and Support Logic
Wednesday, October 19, 2005
6:36:12 pm
521
header.1x3
J291
2
313D8 100
R295
4.7K
R285
TP18
2
3
is24c02-3g.so8
U29
1A
0
A1
2 3A
2
CLK6
5DATA
7WC
14
22uFC277+
J271
41PRE
51Q
1QB6
11
132CLR
2D12
2PRE10
2Q9
82QB
7
GND
VCC
VCC_HOT_3.3
U31
74AHCT74DBso14
3
1CLR1
21D
C2840.1uF
0.1uFC276
R243
4.7K
13D1
13D1
C2711.0uF
CR6
R246
3.3K
13D8
VCC_HOT_5
J251
2
3
BAS16LT1
VCC_12
C30110uF
+
DATA5
WC7
conn.batteryJ26
1 2
VCC_HOT_3.3
CR7 BAS16LT1
R247
U28
is24c02-3g.so8
A0
1 2A
1
A2
3
6CLK
J17
13B8,26B1,27B1,28B1,30B1,31B1,32B1
VCC_3.3
1K
13B8,26B1,27B1,28B1,30B1,31B1,32B1
R296
4.7K
4.7K
R260
No_Stuff
47
R244
VCC_HOT_3.3
R234
10K
13D1
0.1uFC299
VCC_3.3
VCC_HOT_5
5C8
VCC_3.3
22uFC287+
U32
lt1117cst_3.3.sot223
1GND
3IN OUT
2
10K
RN
14
1
C3020.1uF
1CM_MAX
PWRSW*
NC
NC
NC
VCC_HOT_3.3
R299 100
2CM_MAXRSMRST*
SHORT_POWER
SMBDATSMBCLK
1CM_MAX
VBAT_3V
1CM_MAX 1CM_MAX1CM_MAX
PWRBTN*
FANSPD1FANSPD2
SYS LINE
SYS LINE
COM1: Leftmost (rear view)Serial Port #1
3 4 5 6
A
B
COM2: Rightmost (rear view)Serial Port #2
7 8
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
C
7700 W. Parmer Ln
PWR
Gary MilliornV3.1
17Arcadia
Serial Transceivers and ConnectorsWednesday, October 19, 2005
6:34:55 pmAustin, Texas 78729freescale
Freescale Semiconductor
semiconductor
TM
8
A
B
D
C
7654321
1 2
14C8
0.1uFC26
0.1uFC14
R5IN18
R5OUT
1V+
V-28
VCC2
14VL
VCC_5
0.1uFC22
13
6R1IN
24R1OUT
R2IN8
R2OUT22
9R3INR3OUT
21
R4IN10
R4OUT20
12
D1IN25
D1OUT5
D2IN23
D2OUT7
D3IN19 11
D3OUT16
DRVDIS
17
GND NC
15
ON
14C8
U1
lt1331cg.ssop28
3C1+
4C1-
C2+26
C2-27
VCC_5
14C8
14D8
C120.1uF
C150.1uF
VCC_3.3
0.1uFC19
14C8
14C8
14C8
14D8
14D8
14C8
0.1uFC13
C300.1uF
VCC_3.3
14C8
14C8
789
VCC_5
C290.1uF
J1
12345
6
2345
6789
conn.db9.plug.rta14C8
C180.1uF
J2conn.db9.plug.rta
1
R4OUT
R5IN12
R5OUT18
V+1
28V-
2VCC
14VL
14C8
14C8
14C8
15
ON13
R1IN6
R1OUT24
8R2IN
22R2OUT
R3IN921
R3OUT10
R4IN20
C2+
27C2-
D1IN25
D1OUT5
D2IN23
D2OUT7
D3IN19 11
D3OUT16
DRVDIS
GND
17
NC
0.1uF
lt1331cg.ssop28
U2
C1+3
C1-4
26
<,,,annot_deleted,>
VCC_5
0.1uFC21C20
1CM_MAX
1CM_MAX
1CM_MAX
NC
NC
1CM_MAX
1CM_MAX1CM_MAX
1CM_MAX
1CM_MAX
1CM_MAX
2CM_MAX
2CM_MAX
2CM_MAX
2CM_MAX
2CM_MAX
NC
NC
1CM_MAX
1CM_MAX
2CM_MAX
2CM_MAX
2CM_MAX
2CM_MAX
1CM_MAX
2CM_MAX
2CM_MAX
2CM_MAX
TXD1DTR1RTS1
DCD1RXD1
DSR1CTS1RI1
TXD2DTR2RTS2
DCD2RXD2
DSR2CTS2RI2
2CM_MAX
2CM_MAX
2CM_MAX
2CM_MAX
3.3
VC
C_
3.3VCC_
7654
D
C
freescaleFreescale Semiconductor
semiconductor
TM
21
1 2 3 4 5 6 7
Gary MilliornV3.1
18Arcadia
Ethernet InterfaceWednesday, October 19, 2005
6:33:47 pm
8
A
B
D
Engineer:Revision:
Date Changed:
Time Changed:Title:
Project:Page:
Austin, Texas 78729
3
7700 W. Parmer Ln
8
C
A
B
11A8,13D1,20C1,31B1,32B1
VCC_3.3
VCC_3.3
26
25
0.1uFC43
R14
330330
R15
330
R16
19A1
RN410K 2
C690.1uF 0.1uF
C72
10D8
27
EXCCL4532U1
F1
19B1
2
22
21
19A1
19B1
VCC_2.5
F2
EXCCL4532U1
7
6 0.1uFC60
14
1
21
11B1,13C1,20B1,31A1,32A1
11
10
9
8
19B1
27pF
C16
2
11D8,13C1,20B1,31B8,32B8
VD
D25
_151 96
VD
D25
_2
6V
DD
_1V
DD
_222 34
VD
D_3
VD
D_4
39 90V
DD
_5V
DD
_697
61X1
X260
RST
65RTSET
RTT363
RXINN67
RXINP68
SERR19
STOP17
14TRDY
71TXDN
72TXDP
VCNTRL55
64
NC17
40NC2NC3
69
76NC4
20PAR
18PERR
PME57
REQ85
REQ253
ROMCS_OE35
82
GNT
54GNT2
IDSEL99 78
IDSEL2
INTA81
IRDY13
74ISOLATE
LED080
79LED1LED2
77
LWAKE
11CBE2
98CBE3
CLK83
52CLKRUN
15DEVSEL
EECS49
EEDI47
46EEDO
48EESK
FRAME12
84
36
33AD7AD8
30
29AD9
AUX50
AV
DD
2558
59A
VD
D_1
AV
DD
_270 75
AV
DD
_332
CBE0
21CBE1
95
94AD25AD26
93
92AD27AD28
91
89AD29
41AD3
AD3087
86AD31
AD438
37AD5AD6
AD15AD16
10
9AD17AD18
8
5AD19
AD242
AD204
3AD21AD22
1
100AD23AD24
U5
rtl8139d.pqfp100
GROUND
2 16 31
43 56 62
66 73 88
AD045
44AD1
AD1028
27AD11AD12
26
25AD13AD14
24
23
20
19
C310.1uF
CS
DI3
DO4
GND 5
7NC6ORG_N
VCC 8
C17
27pF
2
18
24
23
93lc56c
U10
dip8_skt
CLK2
1
0
11C8,13C1,20B1,31B1,32B1
11D1,20B1,31B1,32B1
6D1,11C1,31A1,32A1
0.1uFC164
10K
RN
4
1
3
2
1
13
12
15
30
3111D8,13A1,20B1,31D1,32D1
NC
1N
C2
19A1
11C1,13C1,20B1,31B8,32B8
C550.1uF
R197 33
Y1
25MHZ
7A1,9A8,11B1,13D1,22D1,31A1,32A1
C410.1uF
2
VCC_3.3
0.1uFC63C37
0.1uF
11B1,13D1,20C1,31B1,32B1
R19 1K
29
28
5
4
17
16
1
D2
0
3
11A8,13C1,20B1,31A1,32A1
11D1,13C1,20B1,31A1,32A1
11B1,13C1,20B1,31A1,32A1
11B8,13C1,20B1,31A1,32A1
F4
EXCCL4532U1
Green
0.1uFC71
VCC_3.3
1K
R17
ENET_TXDNENET_TXENET_DIFF
ENET_TXDPDIFF_PAIRENET_TXENET_DIFF
R18
1K
<,,,annot_deleted,>
PCI_B4
PCI_B4
PCIB4_REQ*(1:5)PCIB4_GNT*(1:5)
PCIB_CLK(0:5)
2CM_MAX
2CM_MAX
2CM_MAX
2CM_MAX
NC
NC
ENET_LED_LINKENET_LED_TXRX
ENET_RXENET_DIFF DIFF_PAIR ENET_RXDNDIFF_PAIR ENET_RXDPENET_RXENET_DIFF
DIFF_PAIR
PCIB_PCIRST*
PCIB4_PERR*PCIB4_SERR*
NC
NC
NC
ENETDIS*
NC
SHORT_POWER
SHORT_POWER
11C8,13C1,20A1,31B1,32B1PCIB4_INT*(0:3)
1CM_MAX
SHORT_POWER
NC
NC
NC
NC
NC
NC
NC
NC
1CM_MAX
PCIB4_AD(31:0)
PCIB4_CBE*(3:0)
PCIB4_FRAME*PCIB4_IRDY*PCIB4_TRDY*PCIB4_DEVSEL*PCIB4_STOP*PCIB4_PAR
1CM_MAX
BOTTOM
TOP
_5VVCC
_5VVCC
A+
A-
B+
B-
C+
C-
D+
D-
RJ-1
RJ-2
RJ-3
RJ-6
RJ-4
RJ-5
RJ-7
RJ-8
HVCap
Amber
Yellow
POLYSW
A
Time Changed:Engineer:
Date Changed:
Revision:Page:Title:
Project:7700 W. Parmer Ln
8
Austin, Texas 78729
C
A
B
D
C
freescaleFreescale Semiconductor
semiconductor
TM
7654321
1 2 3 4 5 6 7 8
Gary MilliornV3.1
19Arcadia
USB and Ethernet ConnectorsWednesday, October 19, 2005
6:31:38 pm
B
D
0.1uFC33
R2
15K
49.9
R12
C447pF
14A1
R1 27
FB3
R9 27
R4 27
18pF
FB4
VCC_5
CGND
CGND1
T1 T2
T3 T4
T5 T6
C24
C25
J3
conn.din6.dual.stacked.ra
B1 B2
B3 B4
B5 B6
C450.1uF
18A8
0.1uF
18C7
18A8
C1
27pF
15K
R7R8
15K
C11
27pFC2827pF
4.7K
RN
1
2
27pF
C27
FB1
FB5
13A8
15K
R3
FB7
27pF
C34
18C7
13A8
0.1uFC44
13A8
13A8
FB2
exccl4532.smd
FB9
F3ptc_smd100
13B8
13B8
13C8
49.9
R11
mic2526_2.so8U3
ENA1
4ENB
2FLGA
FLGB3
GND
6
7IN
8OUTA
OUTB5
B4TG
B2TN
TPB3
TVB1
14A1
C8047uF
+
P9
P1
P2
P3
P4
P5
P6
S1
S2
S3
S4
J4
conn.rj45led_over_dualusb.ra
TOP
BOTTOM
BGA4
BNA2
A3BP
A1BV
P8
P7
P10
4.7K
3
47uFC66+
VCC_5
C320.1uF
RN
1
0.1uFC7
R10
49.9
47pFC10
R13
49.9
C6C847pF
FB8
18A8
18A8
47pF
FB6
R6 27
C23
FB10
VCC_3.3
13B8MCLK
USB
USB_DP1T
USB
USB_DP1T
USB
USB_DP0T
USB
USB_DP0T
SH
OR
T_P
OW
ER
18pF
ENET_RXDPENET_RXDN
ENET_TXDPENET_TXDN
SHORT_POWER
MDAT
KCLK
KDAT
SHORT_POWER
USB_P1NUSB_P1P
USB_P2NUSB_P2P
2CM_MAX
2CM_MAX
2CM_MAX
2CM_MAX
NC
NC
NC
NC
ENET_LED_TXRXENET_LED_LINK
SH
OR
T_P
OW
ER
SHORT_POWER
OC0*OC1*
SHORT_POWER
SHORT_POWER SHORT_POWER
2CM_MAX
SHORT_POWER
17
GROUND
8
19
38
49
NC
1
VCC
17
GROUND
8
19
38
49
NC
1
VCC
17
GROUND
8
19
38
49
NC
1
VCC
freescale 7700 W. Parmer LnAustin, Texas 78729
C
B
D
C
8
Freescale Semiconductor
semiconductor
TM
4 765
2
3
1 63
21
5 84 7
Time Changed:
A
B
D
Date Changed:Engineer:
Revision:Page:Gary Milliorn
V3.120
ArcadiaPCI1-PCI2 Bus Isolator
Wednesday, October 19, 2005
6:05:28 pmTitle:
Project:
A
2B932
2OE55
NC1
VCC17
27
0
11D8,13C1,18C1,31B8,32B8
41
2B1031
2B1130
2B1229
2B240
2B339
2B437
2B536
2B635
2B734
2B833
26
2A1127
2A1228
2A216
2A318
2A420
2A521
2A622
2A723
2A824
2A925
2B1
1B253
1B352
1B451
1B550
1B648
1B747
1B846
1B945
1OE56
2A115
2A10
4
1A45
1A56
1A67
1A79
1A810
1A911
1B154
1B1044
1B1143
1B1242
1
U16SN74CBTD16211CDGGR
tssop56
1A12
1A1012
1A1113
1A1214
1A23
1A3
1
0
31
30
22B1
19
18
C1310.1uF
3
2
10
11
10
11D1,18C1,31B1,32B1
15
7
VCC_5
2B436
2B535
2B634
2B733
2B832
2B9
552OE
1NC
17VCC
11
2A522
2A623
2A724
2A825
2A9
412B1
312B10
302B11
292B12
402B2
392B3
37
461B8
451B9
561OE
152A1
262A10
272A11
282A12
162A2
182A3
202A4
21
1A9
541B1
441B10
431B11
421B12
531B2
521B3
511B4
501B5
481B6
471B7
1A1
121A10
131A11
141A12
31A2
41A3
51A4
61A5
71A6
91A7
101A8
11
0.1uF
27
26
tssop56
SN74CBTD16211CDGGR
U17
2
11A8,31A1,32A1
9
11C1,31B1,32B1
11D1,31B1,32B1
2
C132
29
28
29
23
0.1uFC133
5
4
3
2
1
0
2
1
3
30
8
9
11C1,13C1,18C1,31B8,32B8
22B1
2
6
7
11B1,13C1,18C1,31A1,32A1
3
0
17
16
7C8,22A1
11B1,13C1,18C1,31A1,32A1
3
24
11A8,13C1,18C1,31A1,32A1
22B1
22
21
20
21
20
19
1
11B8,13C1,18C1,31A1,32A1
4
5
4
7C8,22A1
7C8,22A1
7C8,22B1
17
16
2
1
18
25
3
4
0
14
7C8,22B1
28
4
3
5
3
22B1
11D8,13C1,18C1,31B8,32B8
31
7C8,22B1
25
2
7C8,22B1
6C8,9B8
4
3
5
14
13
26
5
22
3
2
37
2B536
2B635
2B734
2B833
2B932
2OE55
NC1
VCC17
15
2A622
2A723
2A824
2A925
2B141
2B1031
2B1130
2B1229
2B240
2B339
2B4
46
1B945
1OE56
2A115
2A1026
2A1127
2A1228
2A216
2A318
2A420
2A521
11
1B154
1B1044
1B1143
1B1242
1B253
1B352
1B451
1B550
1B648
1B747
1B8
1A1012
1A1113
1A1214
1A23
1A34
1A45
1A56
1A67
1A79
1A810
1A9
12
13
12
24
U18SN74CBTD16211CDGGR
tssop56
1A12
11D8,13A1,18A1,31D1,32D1
6
5
0
1
VCC_5
11D1,13C1,18C1,31A1,32A1
122C1
2
1
11B1,13D1,18C1,31B1,32B1
11A8,13D1,18C1,31B1,32B1
8
7A8,22D8
PCI_B4
PCIB4_GNT*(1:5)
PCI_B4
7C8,22B1
7C8,22B1
1
11C8,13C1,18C1,31B1,32B1
23
2
NC NC
NC NC
NC NC
PCIB3_REQ*(1:5)
PCIB3_GNT*(1:5)
PCIB4_REQ*(1:5)
NC
NC
PCIB3_AD(31:0)
NC
NC
NC
NC
PCIB3_CBE*(3:0)
PCIB3_INT*(0:3)
PCIB3_REQ64*PCIB3_ACK64*
PCIB4_AD(31:0)
NC
NC
PCIB4_PAR
PCIB3_PAR
NC
PCIB4_CBE*(3:0)PCIB4_INT*(0:3)
PCIB3_DEVSEL*PCIB3_IRDY*
PCIB3_TRDY*PCIB3_STOP*PCIB3_LOCK*PCIB3_PERR*PCIB3_SERR*
NC
NC
NC
NC
NC
PCIB4_FRAME*PCIB4_DEVSEL*PCIB4_IRDY*PCIB4_TRDY*PCIB4_STOP*PCIB4_LOCK*PCIB4_PERR*PCIB4_SERR*
PCIB4_REQ64*PCIB4_ACK64*
PCIB3_FRAME*NC
NC
NC
NC
NC
17
GROUND
8
19
38
49
NC
1
VCC
B
Engineer:
D
Page:Date Changed:
Time Changed:Title:
Friday, October 21, 2005
4:01:00 pm
Project:
Revision:7700 W. Parmer LnAustin, Texas 78729
C
A
4
B
D
C
freescaleFreescale Semiconductor
semiconductor
TM
87654321
1 2 3 5 7 86
A
Gary Milliorn 21V3.1
ArcadiaPCIBridge Primary Interface
42
41
40
39
38
37
5
4
50 R106 8.2K
47
17
26B1,27B1,28B1,30B1
36
35
32
16
63
33
0
50
49
48
R50
8.2K
7B1,8B8,26A1,27A1,28A1,30A1
R59 28
8.2K
R91
7C1,26A1,27A1,28A1,30A1
8.2KR135
7B1,26B1,27B1,28B1,30B1
26A1,27A1,28A1,30A1
33
R84
R82 8.2K
R162 8.2K
8.2K
36
07C1,26B1,27B1,28B1,30B1
29
28
8.2KR115
10D8
26B1,27B1,28B1,30B1
7C1,26B8,27B8,28B8,30B8
37
8.2KR134
R168 8.2K
32
VCC_3.3
R86 8.2K
VCC_3.3
49
48
R97
8.2K
R81
8.2K
R137 8.2K
R12
78.
2K
8.2K
R83
12
74lvc1g125.sc70
U22
NEAR_SLOT
2
1
4
6D1
0
3
62
61
13
8.2KR167
R131 8.2K
GND1
OE
5VCC
VCC_3.3
54
53
3
2
9
8
U20
74cbtlv1g125dbv.so5
2A
4B
3
8.2K
R80
R11
88.
2K
R11
98.
2K
26B1,27B1,28B1,30B1
26B1,27B1,28B1,30B1
25
24
46
45
8.2K
R77
8.2KR98
7C1,26A1,27A1,28A1,30A1
7C1,26A1,27A1,28A1,30A1
R93 8.2K
8.2KR125
8.2KR88
8.2KR101
4.7K
R60
5
4
27
26
R163 8.2K
P_RST
P_SERRB4
P_STOPC4
B15P_TRDY
1
35
34
B19
P_IRDYA16
C14P_LOCK
C18P_PAR
A9P_PAR64
C8P_PERR
P_REQB21
C12P_REQ64
E22
P_CBE4A5
P_CBE5C11
P_CBE6B12
A7P_CBE7
P_CLKE21
D21P_DEVSELP_FRAME
A17
C20P_GNT
P_IDSEL P_AD63
P_AD7A20
P_AD8B17
C17P_AD9
A13P_CBE0
B18P_CBE1
D14P_CBE2
A15P_CBE3
A3
B9P_AD57P_AD58
C9
B10P_AD59
P_AD6C16
P_AD60A4
C10P_AD61P_AD62
D10
B11
P_AD49
B16P_AD5
P_AD50B6
D6P_AD51P_AD52
B7
C7P_AD53
B3P_AD54
B8P_AD55P_AD56
P_AD41P_AD42
F2
B1P_AD43P_AD44
F3
E3P_AD45P_AD46
F4
D2P_AD47P_AD48
C2
B5
J2P_AD35
H1P_AD36
G1
J3P_AD37P_AD38
E1
H2P_AD39
P_AD4A19
P_AD40H3
G3
P_AD27P_AD28
L21
M22P_AD29
C15P_AD3
P_AD30M21
J23P_AD31P_AD32
L1
J1P_AD33P_AD34
B14
P_AD20J21
K22P_AD21P_AD22
D23
K21P_AD23P_AD24
E23P_AD25
K20P_AD26
G23
L22
F22
F20P_AD13P_AD14
G22
B20P_AD15P_AD16
G21
H22P_AD17P_AD18
H21
J22P_AD19
P_AD2
U23
TSI310A-133CE
tsi310.1of4.pci_p.pbga304
PRIMARY PCI
P_ACK64A2
P_AD0B13
C13P_AD1
P_AD10C19
D18P_AD11P_AD12
R75
8.2K
45
44 44
43
41
40
8.2K
R64
58
57
R133 8.2K
6D1,26A1,27A1,28A1,30A1
8.2KR99
19
18
57
56
55
R103 8.2K
8.2KR108
26B8,27B8,28B8,30B8
5
58
R166
R123 8.2K
R165 8.2K
8.2K
R128 8.2K
8.2KR164
31
30
7
6
7D1
52
51
15
14
21
20
11
10
8.2KR132
54
38
0
7C1,26B8,27B8,28B8,30B87
6
R113 8.2K
8.2K59
39
39
38
37
8.2KR121
R87
45
44
43
42
41
40
8.2K
R11
6
46
43
42
56
55
8.2KR136
49
48
47
47
46
2
1
55
54
53
52
51
50
2B733
2B832
2B9
552OE
1NC
17VCC
60
59
32
252A9
412B1
312B10
302B11
292B12
402B2
392B3
372B4
362B5
352B6
34
2A1
262A10
272A11
282A12
162A2
182A3
202A4
212A5
222A6
232A7
242A8
1B1142
1B12
531B2
521B3
511B4
501B5
481B6
471B7
461B8
451B9
561OE
15
31A2
41A3
51A4
61A5
71A6
91A7
101A8
111A9
541B1
441B10
43
34
33
tssop56
SN74CBTD16211CDGGR
U25
21A1
121A10
131A11
141A12
53
52
51
23
22
7C1,26A1,27A1,28A1,30A1
7C1,26A1,27A1,28A1,30A1
R76
8.2K
62
61
60
VCC_5
7C1,26D1,27D1,28D1,30D1
63
8.2K
R10
2
36
35
34
33
PCI_A1PCIA_SERR*
PBRIDGE_EN*
TSIPGM_EN*
NC
<,,,annot_deleted,>
PCI_A1
PCI_A1PCIA_PERR*
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCIA_REQ64_DRV* PCI_A1
PCI_A1PCIA_REQ64*
PCIA_PAR64 PCI_A1
PCI_A1PCIA_FRAME*PCI_A1PCIA_DEVSEL*PCI_A1PCIA_IRDY*PCI_A1PCIA_TRDY*PCI_A1PCIA_STOP*
PCIA_LOCK*
PCIA_AD(63:0)
PCIA_CBE*(7:0)
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCIA_ACK64* PCI_A1
PCIA_PAR PCI_A1
PCIA_REQ*(0:4)PCIA_GNT*(0:4)
PCIA_CLK(0:5)
PCIA_PCIRST*
PCI_A1
21
1 2 3 4 5 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:Freescale Semiconductor7700 W. Parmer LnAustin, Texas 78729
C
A
B
D
C
freescale
PWR
Gary Milliorn 22V3.1
FreeServe IPCIBridge Secondary Interface
Tuesday, March 8, 2005
4:26:59 pmsemiconductor
TM
Secondary PCI SpeedFixed 33 MHz
876543
5
41
42
R149 1K
56K
R150
R56
8.2K
R176 8.2K
8.2K
R12
4
GND1
OE
5VCC
VCC_3.3
10D8
R107 8.2K
12
11
10
U19
74cbtlv1g125dbv.so5
2A
4B
3
R96
8.2K
8.2K
R92
49
0
3
2
7C8,20B7
8.2K
R55
8.2KR117
8.2K
8.2KR138
8.2KR172
R142
59
58
57
R171 8.2K
37
36
1
VCC_3.3
8.2KR174
AB20
Y14S_TRDY
R67
8.2K
38
AA2S_REQ3
W2
AB3S_REQ4
AB5S_REQ5
AC3S_REQ6
S_REQ64AB13
U23S_RST
S_SERRAB19
S_STOP
AC19
AC20S_LOCK
AA17S_PAR
AA10S_PAR64
R23S_PCIXCAP
AA1S_PCIXCAP_PU
AB17S_PERR
S_REQ1GNTAA23
S_REQ2
AA14
AA19S_GNT1REQS_GNT2
AB1
Y2S_GNT3S_GNT4
AC5
AB4S_GNT5S_GNT6
AC4
S_IDSELAA22
S_IRDY
AA15S_CBE3S_CBE4
AC8S_CBE5
AA11S_CBE6
AB10
Y10S_CBE7
AB23S_CLK
AC21S_DEVSELS_FRAME
S_AD61S_AD62
AB7
AB8S_AD63
AA13S_AD7S_AD8
AC17S_AD9
AB15
AB12S_CBE0
AB16S_CBE1
AB14S_CBE2
V4S_AD55
V2S_AD56
Y3
Y6S_AD57S_AD58
AA5S_AD59
AA6
S_AD6AA12
S_AD60AB6
AA7
S_AD47S_AD48
R3S_AD49
R2
AC15S_AD5
S_AD50T3
S_AD51T2
S_AD52U3
U2S_AD53S_AD54
S_AD40N3
N2S_AD41S_AD42
U1
P4S_AD43
W1S_AD44S_AD45
P3S_AD46
Y1
P2
K3S_AD33S_AD34
K2
L3S_AD35S_AD36
L2S_AD37
R1S_AD38
M3
M2S_AD39
S_AD4AB11
P20S_AD26
M23S_AD27S_AD28
P21
P22S_AD29
AC11S_AD3
S_AD30N21
N22S_AD31S_AD32
K4
U22S_AD19
AC9S_AD2
S_AD20T22
W23S_AD21
R21S_AD22
T23S_AD23S_AD24
R22
N23S_AD25
Y18S_AD11S_AD12
AB18
AA20S_AD13S_AD14
V20S_AD15
W21
V21S_AD16
V22S_AD17S_AD18
U21
TSI310A-133CE
tsi310.2of4.pci_s.pbga304
SECONDARY PCI
U23
S_ACK64AA8
S_AD0AA9
AB9S_AD1
S_AD10AA16
4.7K
R58
10R63
R53
8.2K
44
43
R17
98.
2K
8.2K
R54
44
43
42
17
8.2KR140
R173 8.2K
8.2KR110
R144 8.2K
8.2KR145
5
60
R114
R178 8.2K
3
R147 8.2K
8.2K
R85
8.2K
7C8,20D7
61
19
3
20C7
0
20
6D1
40
38
37
36
41
8.2K
R10
0
46
45
8.2K
R52
39
7A8,20D7
63
62
61
48
47
2
18
4
7C8,20B7
54
7A1,9A8,11B1,13D1,18D1,31A1,32A1
20D749
8.2KR9563
62
7C8,20B7
60 R111 8.2K
0.1uFC206
VCC_3.3
8.2KR104
46
45
VCC_3.3
0R151
54
537C8,20B7
7C8,20B7
7C8,20B7
7C8,20B7
48
47
32
31
30
29
56
55
8.2K
R146 8.2K
8.2KR105
R126
17
4
3
2 R120 8.2K
8.2KR143
8.2KR141
R175 8.2K
16
15
14
13
8.2KR177
8.2K
8.2KR109
8.2KR169
R170
20D7
1
0
7C8,20D7
40
R139 8.2K
58
57
56
55
52
51
50
33
32
9
8
7
6
39
2
1
35
34
8.2K
R74
R148 8.2K
R72
8.2K
25
R51
8.2K
8.2K
R89
35
34
33
20B7
28
27
266
5
24
23
22
21
R65
8.2K
1
20C7
R79
8.2K
8.2K
R69
52
51
50
8.2K
R71
6
4
59
53
PCI_B3
PCI_B3
PCIB3_AD(31:0)
SBRIDGE_EN*
<,,,annot_deleted,>
8.2K
R78
PCIB3_GNT*(1:6)
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCIB_CLK(0:5)
TSI310_PCIRST_OUT*
PCI_B3PCIB3_REQ64*
PCI_B3PCIB3_LOCK*
PCI_B3
PCI_B3
PCI_B3
PCIB3_REQ*(1:6)
PCI_B3
PCI_B3
PCI_B3
PCI_B3PCIB3_SERR*
PCIB3_ACK64* PCI_B3
PCI_B3PCIB3_PAR
PCI_B3
PCI_B3
PCI_B3
1CM_MAX
PCI_B3
PCI_B3
PCIB3_CBE*(3:0) PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3PCIB3_FRAME*PCI_B3PCIB3_DEVSEL*PCI_B3PCIB3_IRDY*PCI_B3PCIB3_TRDY*PCI_B3PCIB3_STOP*
PCIB3_PERR* PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
1CM_MAX
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
PCI_B3
7 8
A
D
Date Changed:
Time Changed:Engineer:
Revision:
B
Title:
PWR
PCI Bridge Control/OptionsWednesday, October 19, 2005
6:10:37 pm
Project:Page:7700 W. Parmer Ln
C
B
D
semiconductor
A
Austin, Texas 78729freescale
Freescale SemiconductorTM
C
8
PCI Bridge Options
65 732 4
3 4
1
1 2 5 6
Gary MilliornV3.1
23Arcadia
1K
R130
6D1
6B1,11A1,26A8,27A8,28A8,30A8,31A8,32A8
8.2K
R68
R129
1K
11
7 10
8 9
1K
R112
6B1,11A1,26A8,27A8,28A8,30A8,31A8,32A8
sw.8spst.ctsSW1
1 16
2 15
3 14
4 13
5 12
6 S_SEL100V3
Y23TEST_CE0T_DI1
Y21
T_DI2AA4
C1T_MODECTLT_RI
W22
XCLK_OUTD3
JTG_TRSTC23
OPAQUE_ENAA18
C6P_CFG_BUSYP_DRVR_MODE
E2
RESERVEDD1
W3S_CLK_STABLE
AC7S_DRVR_MODE
T21S_INT_ARB_EN
tsi310.3of4.control.pbga304
Y2264_BIT_DEVICE
G2BAR_EN
AC22IDSEL_REROUTE_EN
JTG_TCKF21
C22JTG_TDI
B23JTG_TDOJTG_TMS
D22
26A8
R12
28.
2K
11B8
CONTROL
U23
9
VCC_3.3
VCC_3.3
6B1,11B8,26A8,27A8,28A8,30A8,31A8,32A88.
2KR
62
RN5
330
110
23
45
67
8
TP10
8
9
R94
1K 1K
R61
RN32.7k
1
10
234567
2CM_MAX
2CM_MAX
SCLKRDY
2CM_MAX
2CM_MAX
2CM_MAX
2CM_MAX
PRPMC_TDOTMS
TRST*TCK
TSI310_TDO
2CM_MAX
<,,,annot_deleted,>
Y20 AA3 AA21 AB2
A1 A6 A10 A11
AC10 AC13 AC14
AC18 AC23
VSS
A14 A18 A23 B2
AB22 AC1 AC6
B22 C3 C21 D4
D8 D12 D16 D20
F1 F23 H4 H20
K1 K23 L23 M4
M20 N1 P1 P23
T4 T20 V1 V23
Y4 Y8 Y12 Y16
TM
654321
1 2 3 4 5 6
PWR
PWR
Gary Milliorn 24V3.1
ArcadiaPCI Bridge: Power
Wednesday, October 19, 2005
6:14:42 pm
7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:Freescale Semiconductor7700 W. Parmer Ln
87
Austin, Texas 78729
C
A
B
D
C
freescalesemiconductor
VCC_3.3
R70
470
D7VDDIO6VDDIO7
D17
VDDIO8D19
VDDIO9E4
16V
C15322uF
+
Y17VDDIO22VDDIO23
Y19
AC2VDDIO24VDDIO25
AC12
AC16VDDIO26
VDDIO3A22
C5VDDIO4VDDIO5
D5
VDDIO15T1
U4VDDIO16VDDIO17
U20
W4VDDIO18VDDIO19
W20
A12VDDIO2
Y5VDDIO20VDDIO21
Y7
VDDCORE8L20
N4VDDCORE9
VDDIO1A8
E20VDDIO10VDDIO11
G4
VDDIO12G20
VDDIO13H23
M1VDDIO14
Y13VDDCORE15VDDCORE16
Y15
D11VDDCORE2
D13VDDCORE3VDDCORE4
D15
J4VDDCORE5VDDCORE6
J20
L4VDDCORE7
P_AVDDA21
AB21S_AVDD
D9VDDCORE1
VDDCORE10N20
R4VDDCORE11VDDCORE12
R20
Y9VDDCORE13VDDCORE14
Y11
VCC_5
U21mic29152bu.to263_5
GN
D1
3
GN
D2
6
1IN1
IN22
OUT14
5OUT2
tsi310.4of4.power.pbga304
TSI310A-133CE
U23
POWER
0.1uF
0.1uFC155
0.1uFC157 C178
22uFC154
16V
+
VCC_2.5
C1690.1uF
0.1uF 0.1uFC192
0.1uFC195 C184
C1790.1uF
C2010.1uF
21
C1610.1uF 0.1uF
C170
21
rc1210
10R66
CR3
MBRS360T3
smc_403
C163
CR1
MBRS360T3
smc_403
21
smc_403
MBRS360T3
CR2
300mA
70 ohms
HF30ACB453215-T
F5
0.1uF
C1520.1uF
F6
HF30ACB453215-T
70 ohms
300mA
C1730.1uF 0.1uF
C162
0.1uFC199
0.1uFC200C166
0.1uF<,,,annot_deleted,>
1CM_MAX
2CM_MAX
2CM_MAX
SHORT_POWER
R73
470
A
D
C
freescaleFreescale Semiconductor
87654321
Gary MilliornV3.1
25Arcadia
Slot 2/HIP 1 : LVDS Connection and PowerWednesday, October 19, 2005
6:15:10 pm
1 2
semiconductor
TM
3 4 7 85 6
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
B
7700 W. Parmer LnAustin, Texas 78729
C
12
29B1
29C1
29A1
28
30
2
9
16
16
1320
17
10
4
0
6
7
29D1
29D1
29D1
14
29D1
31
29D1
29D1
27
3
29D1
19
guide_pin
guide_pin.keyedP2
20
0
29B1
31
21
25
22
26
23
27
H3
H4
H5
H6
H7
H8
H9
GHG5
GHG6
GHG7
GHG8
GHG9
H1
H10
H2
G7
G8
G9
GHG1
GHG10
GHG2
GHG3
GHG4
F9
G1
G10
G2
G3
G4
G5
G6
F10
F2
F3
F4
F5
F6
F7
F8
EFG3
EFG4
EFG5
EFG6
EFG7
EFG8
EFG9
F1
E5
E6
E7
E8
E9
EFG1
EFG10
EFG2
D7
D8
D9
E1
E10
E2
E3
E4
CDG9
D1
D10
D2
D3
D4
D5
D6
CDG10
CDG2
CDG3
CDG4
CDG5
CDG6
CDG7
CDG8
C3
C4
C5
C6
C7
C8
C9
CDG1
B5
B6
B7
B8
B9
C1
C10
C2
ABG7
ABG8
ABG9
B1
B10
B2
B3
B4
A9
ABG1
ABG10
ABG2
ABG3
ABG4
ABG5
ABG6
A10
A2
A3
A4
A5
A6
A7
A8
18
29
19
30
P4conn.amp.HM-Zd.40pr.plug.vert
A1
B1
B2
B3
B4
C1
C2
C3
C4
13
guide_pin.keyed
guide_pin
P8conn.pwr.3pos.vert
A1
A2
A3
A4
15
15
17
12
14
18
P10
8
10
5
29C1
29C1
29C1
29C1
11
11
28
29C1
29B1
29C1
29
1
5
8
9
22
VCC_3.3
23
VCC_5
26
3
6
4
7
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
24
25
21
24
P6conn.pwr.3pos.vert
A1
RB1_RFRM1
RAPIDIO_RDRB1_RFRM1N
S1RFM-2
S1TFM-2
RB1_TFRM1N
<,,,annot_deleted,>
1
2
RB1_TCLK0N
RAPIDIO_TD S1TCLK-1
RB1_TCLK1
S1TCLK-2RAPIDIO_TD
RB1_TCLK1N
S1TCLK-2RAPIDIO_TD
RAPIDIO_RD S1RFM-2
RAPIDIO_TD S1TD-13
RAPIDIO_TD S1TD-14
RAPIDIO_TD S1TD-14
S1TD-15RAPIDIO_TD
S1TD-15RAPIDIO_TD
RAPIDIO_TD S1TCLK-1
RB1_TCLK0
RAPIDIO_TD S1TD-10
S1TD-11RAPIDIO_TD
S1TD-11RAPIDIO_TD
S1TD-12RAPIDIO_TD
S1TD-12RAPIDIO_TD
RAPIDIO_TD S1TD-13
S1TD-7RAPIDIO_TD
S1TD-7RAPIDIO_TD
S1TD-8RAPIDIO_TD
S1TD-8RAPIDIO_TD
RAPIDIO_TD S1TD-9
RAPIDIO_TD S1TD-9
RAPIDIO_TD S1TD-10
RAPIDIO_TD
S1TD-4RAPIDIO_TD
S1TD-4RAPIDIO_TD
RAPIDIO_TD S1TD-5
RAPIDIO_TD S1TD-5
RAPIDIO_TD S1TD-6
RAPIDIO_TD S1TD-6
RAPIDIO_TD
RAPIDIO_TD S1TD-1
RAPIDIO_TD S1TD-1
RAPIDIO_TD S1TD-2
RAPIDIO_TD S1TD-2
S1TD-3RAPIDIO_TD
S1TD-3
S1RD-14RAPIDIO_RD
RAPIDIO_RD S1RD-15
RAPIDIO_RD S1RD-15
RAPIDIO_RD S1RCLK-2RB1_RCLK1RB1_RCLK1N
S1RCLK-2RAPIDIO_RD
RB1_TD(0:31)
S1TD-0RAPIDIO_TD
S1TD-0
RAPIDIO_RD S1RD-11
RAPIDIO_RD S1RD-12
RAPIDIO_RD S1RD-12
S1RD-13RAPIDIO_RD
S1RD-13RAPIDIO_RD
S1RD-14RAPIDIO_RD
S1RD-8
RAPIDIO_RD S1RD-8
S1RD-9RAPIDIO_RD
S1RD-9RAPIDIO_RD
S1RD-10RAPIDIO_RD
S1RD-10RAPIDIO_RD
RAPIDIO_RD S1RD-11
RAPIDIO_RD
S1RD-6RAPIDIO_RD
S1RD-7RAPIDIO_RD
S1RD-7RAPIDIO_RDRB1_RFRMS1RFM-1RAPIDIO_RD
S1RFM-1RB1_RFRMN
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
S1RD-3RAPIDIO_RD
S1RD-4RAPIDIO_RD
S1RD-4RAPIDIO_RD
S1RD-5RAPIDIO_RD
S1RD-5RAPIDIO_RD
S1RD-6
RB1_RD(0:31)
S1RD-0RAPIDIO_RD
S1RD-0RAPIDIO_RD
S1RD-1RAPIDIO_RD
S1RD-1RAPIDIO_RD
S1RD-2RAPIDIO_RD
S1RD-2RAPIDIO_RD
S1RD-3
S1RCLK-1RB1_RCLK0
RAPIDIO_RDRB1_RCLK0NS1RCLK-1RAPIDIO_RD
RB1_TFRM1
S1TFM-2
RAPIDIO_TD S1TFM
RB1_TFRMNRB1_TFRM
S1TFMRAPIDIO_TD
A2
GND
A18
A24 A30 A35 A37 A42
A48 A56 A63 A69 A72
A78 A81 A87 A90 B3
B15 B17 B22 B28 B34
B46 B57 B64 B67
B73 B76 B82 B85 B91
A93 B94
VIO: 3.3V or 5V
-12V
B1
+5V
A53 B25 B31 B36 B41
B43 B54
NC
A94 B10 B14 B92 B93
B63
B6 B61 B62
A5 A8 A61 A62 B5
A9 A11 A14 A19 A92
A21 A27 A33 A39 A45
+3.3V
+12V
C
TM
87654321
1 2 3 4 5 6 7 8
A
D
Date Changed:
Time Changed:Engineer:
Revision:Title:
Project:
B
Page:Austin, Texas 78729
C
7700 W. Parmer Ln
B
D
Gary Milliorn 26V3.1
ArcadiaSlot 2 / HIP 1 : PCI-X Connections
Friday, October 21, 2005
4:13:00 pm
A
freescaleFreescale Semiconductor
semiconductor
7
6
7C1,21B1,27A1,28A1,30A1
7C1,21B1,27A1,28A1,30A1
63
9D1,27B1,28B1,30B1
14
21B1,27B1,28B1,30B1
7C1,21A1,27B8,28B8,30B8
21A1,27B8,28B8,30B8
12
22
20
6B1,11B8,23C1,27A8,28A8,30A8,31A8,32A8
13B8,16C8,27B1,28B1,30B1,31B1,32B1
20
7C1,21A1,27A1,28A1,30A1
3
2
7B1,21C1,27B1,28B1,30B1
6B1,11A1,23C1,27A8,28A8,30A8,31A8,32A8
15
34
41
32
33
39
38
21B1,27B1,28B1,30B1
VCC_3.3
10
6
7
9B1,27B8,28B8,30B8
7C1,21B1,27B8,28B8,30B8
36
35
45
52
53
1
0
11
3
30
29
49
46
51
1
17
16
21
6C1,27B1,28B1,30B1
2
4
23
26
25
3
1
18
54
55
23C1
27A8
59
60
10
28
27
6D1,21D1,27A1,28A1,30A1
3
7C1,21B1,27A1,28A1,30A1
57
58
40
61
7B1,8B8,21D1,27A1,28A1,30A1
R45
1
9
8
42
5
24
6B1,11A1,23C1,27A8,28A8,30A8,31A8,32A8
50
44
43
47
0
7C1,21D8,27D1,28D1,30D1
0
2
48
5
56
7C1,21A1,27A1,28A1,30A1
31
19
4
13B8,16C8,27B1,28B1,30B1,31B1,32B1
VCC_HOT_3.3
62
21B1,27B1,28B1,30B1
21B1,27A1,28A1,30A1
21B1,27B1,28B1,30B1
A75
A84
B19
B59
B70
7C1,21C1,27B1,28B1,30B1
37
1
A36
TRSTA1
A10
B79
B88A16
A59
A66
B42
A40SMBCLK
A41SMBDAT
STOPA38
TCKB2
TDIA4
TDOB4
TMSA3
TRDY
PAR64
B38PCIXCAP
PERRB40
PRSNT1B9
PRSNT2B11
REQB18
A60REQ64
RSTA15
SERRB7
INTCA7
INTDB8
IRDYB35
LOCKB39
M66ENB49
P3.3V_AUXA14
PARA43
A67
C_BE5
B65C_BE6
A64C_BE7
B37DEVSEL
FRAMEA34
GNTA17
IDSELA26
INTAA6
INTB
AD8
AD9A49
CLKB16
C_BE0A52
C_BE1B44
C_BE2B33
C_BE3B26
B66C_BE4
A65
AD58
B71AD59
AD6A54
A70AD60
B69AD61
A68AD62
B68AD63
AD7B53
B52
AD50
B77AD51
A76AD52
B75AD53
A74AD54
B74AD55
A73AD56
B72AD57
A71
AD43
A82AD44
B81AD45
AD46A80
B80AD47
A79AD48
B78AD49
AD5B55
A77
A88
B87AD37
A86AD38
B86AD39
AD4A55
A85AD40
B84AD41
A83AD42
B83
B21
AD3B56
AD30A20
AD31B20
A91AD32
B90AD33
A89AD34
B89AD35
AD36
B29AD22
A28AD23
B27AD24
A25AD25
B24AD26
A23AD27
B23AD28
A22AD29
B45AD15
A44AD16
A32
B32AD17
AD18A31
AD19B30
AD2A57
AD20A29
AD21
B60ACK64
AD0A58
AD1B58
AD10B48
AD11A47
AD12B47
AD13A46
AD14
PCIA_GNT*(0:4)
PCIA_PCIXCAP
TRST*
SMBCLKSMBDAT
TCK
TSI310_TDOSLOT2_TDO
13
pcix_conn_univ_64bit_block
SLOT2
PCIA_PCIRST*
PCIA_AD(63:0)
1CM_MAX
PCIA_CLK(0:5)
PCIA_REQ*(0:4)
PCIA_ACK64*
NC
NC
PCIA_PAR64
PCIA_CBE*(7:0)
PCIA_INT*(0:3)
PCIA_FRAME*PCIA_DEVSEL*PCIA_IRDY*PCIA_TRDY*PCIA_STOP*PCIA_LOCK*PCIA_PERR*PCIA_SERR*
PCIA_M66EN
PCIA_REQ64*
PCIA_PAR
TMS
A2
GND
A18
A24 A30 A35 A37 A42
A48 A56 A63 A69 A72
A78 A81 A87 A90 B3
B15 B17 B22 B28 B34
B46 B57 B64 B67
B73 B76 B82 B85 B91
A93 B94
VIO: 3.3V or 5V
-12V
B1
+5V
A53 B25 B31 B36 B41
B43 B54
NC
A94 B10 B14 B92 B93
B63
B6 B61 B62
A5 A8 A61 A62 B5
A9 A11 A14 A19 A92
A21 A27 A33 A39 A45
+3.3V
+12V
7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:
PWR
Slot 3Friday, October 21, 2005
4:15:17 pmPage:Title:
Project:
8
7700 W. Parmer LnAustin, Texas 78729
C
A
B
D
C
freescaleFreescale Semiconductor
semiconductor
TM
43 76521
1 2 3 4 5 6
Gary MilliornV3.1
27Arcadia
11
10
59
58
21
20
21A1,26B8,28B8,30B8
21B1,26B1,28B1,30B1
39
38
29
28
35
34
24
1
0
7C1,21B1,26A1,28A1,30A1
21B1,26A1,28A1,30A1
55
54B
70
3
0
63
62
25
B79
B88A16
A59
A66 A75
A84
B19
B59
A38
TCKB2
TDIA4
TDOB4
TMSA3
TRDYA36
TRSTA1
A10
B9
PRSNT2B11
REQB18
A60REQ64
RSTA15
SERRB42
A40SMBCLK
A41SMBDAT
STOP
B35
LOCKB39
M66ENB49
P3.3V_AUXA14
PARA43
A67PAR64
B38PCIXCAP
PERRB40
PRSNT1
FRAMEA34
GNTA17
IDSELA26
INTAA6
INTBB7
INTCA7
INTDB8
IRDY
A52C_BE1
B44C_BE2
B33C_BE3
B26
B66C_BE4
A65C_BE5
B65C_BE6
A64C_BE7
B37DEVSEL
AD60
B69AD61
A68AD62
B68AD63
AD7B53
B52AD8
AD9A49
CLKB16
C_BE0
AD53
A74AD54
B74AD55
A73AD56
B72AD57
A71AD58
B71AD59
AD6A54
A70
B80AD47
A79AD48
B78AD49
AD5B55
A77AD50
B77AD51
A76AD52
B75
AD39
AD4A55
A85AD40
B84AD41
A83AD42
B83AD43
A82AD44
B81AD45
AD46A80
B20
A91AD32
B90AD33
A89AD34
B89AD35
AD36A88
B87AD37
A86AD38
B86
AD25B24
AD26A23
AD27B23
AD28A22
AD29B21
AD3B56
AD30A20
AD31
AD18A31
AD19B30
AD2A57
AD20A29
AD21B29
AD22A28
AD23B27
AD24A25
B58
AD10B48
AD11A47
AD12B47
AD13A46
AD14B45
AD15A44
AD16A32
B32AD17
1
0
7C1,21A1,26B8,28B8,30B8
pcix_conn_univ_64bit_block
SLOT3
B60ACK64
AD0A58
AD1
9D1,26B1,28B1,30B1
6B1,11B8,23C1,26A8,28A8,30A8,31A8,32A8
3
2
VCC_HOT_3.3
VCC_3.3
13
12
7C1,21C1,26B1,28B1,30B1
6C1,26B1,28B1,30B1
21B1,26B1,28B1,30B1
21B1,26B1,28B1,30B1
7
6
7
6
42
5
4
7C1,21A1,26A1,28A1,30A1
7C1,21A1,26A1,28A1,30A1
15
14
27
26
47
46
9
8
43
5
4
26A8
28A8
17
16
6D1,21D1,26A1,28A1,30A1
7B1,21C1,26B1,28B1,30B1
49
48
61
60
45
44
19
18
21
2
50
9B1,26B8,28B8,30B8
7C1,21B1,26B8,28B8,30B8
13B8,16C8,26B1,28B1,30B1,31B1,32B1
13B8,16C8,26B1,28B1,30B1,31B1,32B1
23
22
6B1,11A1,23C1,26A8,28A8,30A8,31A8,32A8
6B1,11A1,23C1,26A8,28A8,30A8,31A8,32A8
10
31
30
51
40
21B1,26B1,28B1,30B1
7B1,8B8,21D1,26A1,28A1,30A1
7C1,21B1,26A1,28A1,30A1
7C1,21B1,26A1,28A1,30A1
57
56
7C1,21D8,26D1,28D1,30D1
R46
32
1
2
2
2
41
52
37
36
3
2
33
PCIA_ACK64*
PCIA_CLK(0:5) ML-3NC
NC
SLOT3_TDO
PCIA_PAR64
PCIA_PCIXCAP
PCIA_GNT*(0:4)PCIA_REQ*(0:4)
53
PCIA_AD(63:0)
1CM_MAXPCIA_PAR
TRST*
TCKTMS
SLOT2_TDO
PCIA_CBE*(7:0)
PCIA_INT*(0:3)
PCIA_PCIRST*
PCIA_FRAME*PCIA_DEVSEL*PCIA_IRDY*PCIA_TRDY*PCIA_STOP*PCIA_LOCK*PCIA_PERR*PCIA_SERR*
SMBCLKSMBDAT
PCIA_M66EN
PCIA_REQ64*
A2
GND
A18
A24 A30 A35 A37 A42
A48 A56 A63 A69 A72
A78 A81 A87 A90 B3
B15 B17 B22 B28 B34
B46 B57 B64 B67
B73 B76 B82 B85 B91
A93 B94
VIO: 3.3V or 5V
-12V
B1
+5V
A53 B25 B31 B36 B41
B43 B54
NC
A94 B10 B14 B92 B93
B63
B6 B61 B62
A5 A8 A61 A62 B5
A9 A11 A14 A19 A92
A21 A27 A33 A39 A45
+3.3V
+12V
7700 W. Parmer LnAustin, Texas 78729
C
A
87654
B
D
C
freescalesemiconductor
TM
32
PWR
Gary Milliorn 28V3.1
ArcadiaSlot 4: PCI-X, 3V, 64bit, 100 MHz.
Friday, October 21, 2005
4:15:51 pm
1
1 2 3 4 5 6 7 8
A
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:Freescale Semiconductor
B59
B70
B79
B88A16
A59
A66 A75
A84
B19
STOPA38
TCKB2
TDIA4
TDOB4
TMSA3
TRDYA36
TRSTA1
A10
PRSNT1B9
PRSNT2B11
REQB18
A60REQ64
RSTA15
SERRB42
SMBCLKA40
SMBDATA41
IRDYB35
LOCKB39
M66ENB49
A14P3.3V_AUX
PARA43
A67PAR64
B38PCIXCAP
PERRB40
B37DEVSEL
FRAMEA34
GNTA17
IDSELA26
INTAA6
INTBB7
INTCA7
INTDB8
C_BE0A52
C_BE1B44
C_BE2B33
C_BE3B26
B66C_BE4
A65C_BE5
B65C_BE6
A64C_BE7
A70AD60
B69AD61
A68AD62
B68AD63
AD7B53
B52AD8
AD9A49
CLKB16
B75AD53
A74AD54
B74AD55
A73AD56
B72AD57
A71AD58
B71AD59
AD6A54
AD46A80
B80AD47
A79AD48
B78AD49
AD5B55
A77AD50
B77AD51
A76AD52
B86AD39
AD4A55
A85AD40
B84AD41
A83AD42
B83AD43
A82AD44
B81AD45
AD31B20
A91AD32
B90AD33
A89AD34
B89AD35
AD36A88
B87AD37
A86AD38
AD24A25
AD25B24
AD26A23
AD27B23
AD28A22
AD29B21
AD3B56
AD30A20
B32AD17
AD18A31
AD19B30
AD2A57
AD20A29
AD21B29
AD22A28
AD23B27
AD1B58
AD10B48
AD11A47
AD12B47
AD13A46
AD14B45
AD15A44
AD16A32
58
7
6
7C1,21A1,26B8,27B8,30B8
pcix_conn_univ_64bit_block
SLOT4
B60ACK64
AD0A58
5
4
7C1,21A1,26A1,27A1,30A1
7C1,21A1,26A1,27A1,30A1
1
0
59
12
7C1,21B1,26A1,27A1,30A1
21B1,26A1,27A1,30A1
21
20
0
1
54
21A1,26B8,27B8,30B8
21B1,26B1,27B1,30B1
17
16
7C1,21C1,26B1,27B1,30B1
6C1,26B1,27B1,30B1
13
34
25
24
1
0
55
7
6
39
38
29
28
35
0.1uFC123
1
3
63
62
47
46
C1500.1uF
42
0.1uFC253
VCC_3.3
51
50
0.1uFC97
43
0.1uFC90
VCC_3.3
33
R42
0.1uF 0.1uFC64
6B1,11B8,23C1,26A8,27A8,30A8,31A8,32A8
VCC_HOT_3.3
7C1,21D8,26D1,27D1,30D1
22
9
8
6B1,11A1,23C1,26A8,27A8,30A8,31A8,32A8
6B1,11A1,23C1,26A8,27A8,30A8,31A8,32A8
C135
C2220.1uF 0.1uF
C183
C2500.1uF
21B1,26B1,27B1,30B1
7B1,21C1,26B1,27B1,30B1
C2290.1uF
3
7B1,8B8,21D1,26A1,27A1,30A1
0.1uFC128
0.1uF
45
44
C1100.1uF
3
2
37
36
VCC_5
C620.1uF 0.1uF
C145
41
40
48
11
10
30A8
27A8
C198
19
18
53
52
15
14
49
27
26
13B8,16C8,26B1,27B1,30B1,31B1,32B1
13B8,16C8,26B1,27B1,30B1,31B1,32B1
33
32
21B1,26B1,27B1,30B1
21B1,26B1,27B1,30B1
22
2
3
31
30
6D1,21D1,26A1,27A1,30A1
9D1,26B1,27B1,30B1
9B1,26B8,27B8,30B8
7C1,21B1,26B8,27B8,30B8
61
60
7C1,21B1,26A1,27A1,30A1
7C1,21B1,26A1,27A1,30A1
23
2
57
56
5
4
TRST*TMSTCK
SLOT4_TDOSLOT3_TDO
PCIA_PAR64PCI_A1
PCIA_INT*(0:3)
PCIA_CBE*(7:0)
PCIA_PARPCI_A1
<,,,annot_deleted,>
3
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCIA_PCIXCAP PCI_A1
PCIA_GNT*(0:4) PCI_A1
PCIA_REQ*(0:4) PCI_A1
PCI_A1
PCIA_M66EN PCI_A1
PCIA_REQ64* PCI_A1
PCI_A1PCIA_ACK64*
PCIA_CLK(0:5)NC
NC
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCIA_PCIRST* PCI_A1
PCIA_FRAME* PCI_A1
PCIA_DEVSEL* PCI_A1
PCIA_IRDY* PCI_A1
PCIA_TRDY* PCI_A1
PCIA_STOP* PCI_A1
PCIA_LOCK* PCI_A1
PCIA_PERR* PCI_A1
PCIA_SERR* PCI_A1
SMBCLK PCI_A1
SMBDAT
PCIA_AD(63:0)
PCI_A1
1CM_MAX
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
PCI_A1
8
7700 W. Parmer LnAustin, Texas 78729
C
A
B
D
C
freescaleFreescale Semiconductor
semiconductor
65
TM
743
1 2
21
3 4 5 7 8
A
Gary Milliorn 29V3.1
ArcadiaSlot 5 / HIP 2 : LVDS Connector and Power
Wednesday, October 19, 2005
6:19:26 pm
B
D
Date Changed:
Time Changed:Engineer:
Revision:Page:Title:
Project:
6
25B1
25C1
31
25D1
25D1
13
27
VCC_5
guide_pin
guide_pin.keyedP9
14
30
H9
1
10
12
7
9
H10
H2
H3
H4
H5
H6
H7
H8
GHG3
GHG4
GHG5
GHG6
GHG7
GHG8
GHG9
H1
G5
G6
G7
G8
G9
GHG1
GHG10
GHG2
F7
F8
F9
G1
G10
G2
G3
G4
F1
F10
F2
F3
F4
F5
F6
EFG10
EFG2
EFG3
EFG4
EFG5
EFG6
EFG7
EFG8
EFG9
E3
E4
E5
E6
E7
E8
E9
EFG1
D5
D6
D7
D8
D9
E1
E10
E2
CDG7
CDG8
CDG9
D1
D10
D2
D3
D4
C9
CDG1
CDG10
CDG2
CDG3
CDG4
CDG5
CDG6
C10
C2
C3
C4
C5
C6
C7
C8
B3
B4
B5
B6
B7
B8
B9
C1
ABG5
ABG6
ABG7
ABG8
ABG9
B1
B10
B2
A7
A8
A9
ABG1
ABG10
ABG2
ABG3
ABG4
A1
A10
A2
A3
A4
A5
A6
15
16
25C1
25C1
25C1
25C1
P3conn.amp.HM-Zd.40pr.plug.vert
3
25D1
12
13
19
20
21
B4
C1
C2
C3
C4
23
5
2
conn.pwr.3pos.vertP5
A1
A2
A3
A4
B1
B2
B3
25D1
0
P1guide_pin.keyed
guide_pin
25
26
23
20
24
25D131
4
B3
B4
C1
C2
C3
C4
22
19
21
conn.pwr.3pos.vertP7
A1
A2
A3
A4
B1
B2
17
28
25B1
29
25C1
30
25C1
18
25A1
25B1
15
25D1
25D1
16
27
22
24
26
28
VCC_3.3
29
5
0
2
11
6
8
25
10
11
17
18
3
4
<,,,annot_deleted,>
6
7
1
14
8
9
RAPIDIO_TDRB1_TFRM1RB1_TFRM1N RAPIDIO_TD
RAPIDIO_RD
RB1_RFRM1N
RAPIDIO_TDRB1_TFRMNRB1_TFRM RAPIDIO_TD
RB1_TCLK0N RAPIDIO_TD
RAPIDIO_TDRB1_TCLK0RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RB1_RCLK0RB1_RCLK0N
RAPIDIO_RD
RB1_RCLK1
RAPIDIO_RD
RB1_RCLK1N
RAPIDIO_RD
RAPIDIO_TDRB1_TCLK1RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RB1_TCLK1N RAPIDIO_TD
RB1_RD(0:31)
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_RD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RB1_RFRM1
RAPIDIO_RD
RAPIDIO_RD
RB1_RFRMNRB1_RFRM
RAPIDIO_RD
RB1_TD(0:31)
RAPIDIO_TDRAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
RAPIDIO_TD
A2
GND
A18
A24 A30 A35 A37 A42
A48 A56 A63 A69 A72
A78 A81 A87 A90 B3
B15 B17 B22 B28 B34
B46 B57 B64 B67
B73 B76 B82 B85 B91
A93 B94
VIO: 3.3V or 5V
-12V
B1
+5V
A53 B25 B31 B36 B41
B43 B54
NC
A94 B10 B14 B92 B93
B63
B6 B61 B62
A5 A8 A61 A62 B5
A9 A11 A14 A19 A92
A21 A27 A33 A39 A45
+3.3V
+12V
321
1 2 5 63 4 7 8
A
B
Time Changed:Engineer:
D
Date Changed:
Revision:Page:
PWR
Gary Milliorn 30V3.1
ArcadiaSlot 5 / HIP 2 : PCI-X Connections
Friday, October 21, 2005
4:16:32 pmTitle:
Project:7700 W. Parmer LnAustin, Texas 78729
C
A
87654
B
D
C
freescaleFreescale Semiconductor
semiconductor
TM
19
49
11
41
40
21B1,26B1,27B1,28B1
7B1,8B8,21D1,26A1,27A1,28A1
53
3
48
27
26
7C1,21D8,26D1,27D1,28D1
45
7C1,21B1,26A1,27A1,28A1
7C1,21B1,26A1,27A1,28A1
6
5
16
3
6C1,26B1,27B1,28B1
8
7
37
24
9B1,26B8,27B8,28B8
7C1,21B1,26B8,27B8,28B8
56
4
VCC_3.3
46
6
5
28
52
21B1,26A1,27A1,28A1
60
6B1,11B8,23C1,26A8,27A8,28A8,31A8,32A8
VCC_HOT_3.3
0
43
51
C940.1uF 0.1uF
C204
34
0.1uFC251
VCC_3.3
13B8,16C8,26B1,27B1,28B1,31B1,32B1
13B8,16C8,26B1,27B1,28B1,31B1,32B1
7B1,21C1,26B1,27B1,28B1
21B1,26B1,27B1,28B11
0.1uFC172
35
25
24
0.1uFC187
0
C760.1uF 0.1uF
C205
B59
B70
7C1,21B1,26A1,27A1,28A1
30
29
32
7
B79
B88A16
A59
A66 A75
A84
B19
A38STOP
B2TCK
A4TDI
B4TDO
A3TMS
A36TRDY
TRSTA1
A10
B9PRSNT1
B11PRSNT2
B18REQ
REQ64A60
A15RST
B42SERR
A40SMBCLK
A41SMBDAT
B35IRDY
B39LOCK
B49M66EN
P3.3V_AUXA14
A43PAR
PAR64A67
PCIXCAPB38
B40PERR
DEVSELB37
FRAMEA34
A17GNT
A26IDSEL
A6INTA
B7INTB
A7INTC
B8INTD
A52C_BE0
B44C_BE1
B33C_BE2
B26C_BE3
C_BE4B66
C_BE5A65
C_BE6B65
C_BE7A64
AD60A70
AD61B69
AD62A68
AD63B68
B53AD7
AD8B52
AD9A49
B16CLK
AD53B75
AD54A74
AD55B74
AD56A73
AD57B72
AD58A71
AD59B71
A54AD6
A80AD46
B80AD47
AD48A79
AD49B78
B55AD5
AD50A77
AD51B77
AD52A76
AD39B86
A55AD4
AD40A85
AD41B84
AD42A83
AD43B83
AD44A82
AD45B81
B20AD31
AD32A91
AD33B90
AD34A89
AD35B89
A88AD36
B87AD37
AD38A86
A25AD24
B24AD25
A23AD26
B23AD27
A22AD28
B21AD29
B56AD3
A20AD30
AD17B32
A31AD18
B30AD19
A57AD2
A29AD20
B29AD21
A28AD22
B27AD23
B58AD1
B48AD10
A47AD11
B47AD12
A46AD13
B45AD14
A44AD15
A32AD16
C129
pcix_conn_univ_64bit_block
SLOT5
B60ACK64
A58AD0
0.1uF
7C1,21A1,26A1,27A1,28A1
7C1,21A1,26A1,27A1,28A1
C1590.1uF 0.1uF
59
21A1,26B8,27B8,28B8
0.1uFC242 C252
C2160.1uF
C2470.1uF
31
VCC_5
C1970.1uF50
36
33
31A8
2
1
4
2
3
C3030.1uF 0.1uF
C124
22
6B1,11A1,23C1,26A8,27A8,28A8,31A8,32A8
6B1,11A1,23C1,26A8,27A8,28A8,31A8,32A8
61
44
15
14
4
4
2
1
54
55
28A8
0
23
21B1,26B1,27B1,28B1
21B1,26B1,27B1,28B1
58
57
09D1,26B1,27B1,28B1
21
13
12
47
7C1,21C1,26B1,27B1,28B1
7C1,21A1,26B8,27B8,28B8
42
18
17
R39
33
9
39
38
6D1,21D1,26A1,27A1,28A1
20
63
62
SMBCLKSMBDAT
1CM_MAX
TMSTCK
SLOT5_TDOSLOT4_TDO
NC
NC
<,,,annot_deleted,>
10
PCIA_PAR
PCIA_CBE*(7:0)
PCIA_INT*(0:3)
PCIA_M66EN
PCIA_PAR64
PCIA_GNT*(0:4)PCIA_REQ*(0:4)
PCIA_AD(63:0)
PCIA_CLK(0:5)PCIA_PCIRST*
PCIA_ACK64*PCIA_REQ64*
PCIA_SERR*PCIA_PERR*PCIA_LOCK*PCIA_STOP*PCIA_TRDY*PCIA_IRDY*PCIA_DEVSEL*PCIA_FRAME*
PCIA_PCIXCAP
TRST*
+12V
A2
-12V
B1
A5 A8 A61 A62 B5
+5V
A9 A11 A14 A19
A53 B25 B31 B36 B41
B43 B54
NC
B10 B14
B6 B61 B62
A12 A13 B12 B13 A18
GND
A24 A30 A35 A37 A42
A48 A56 B3 B15 B17
B22 B28 B34 B38 B46
B57
VIO: 3.3V or 5V
A21 A27 A33 A39 A45
+3.3V
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A
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Date Changed:
17
16
23
22
21
20
19
18
29
28
27
26
25
24
1
1
30A8
6B1,11B8,23C1,26A8,27A8,28A8,30A8,32A8
13B8,16C8,26B1,27B1,28B1,30B1,32B1
6B1,11A1,23C1,26A8,27A8,28A8,30A8,32A8
31
30
C490.1uF 0.1uF
C191
VCC_3.3
11D8,13A1,18A1,20B1,32D1
11D1,20B1,32B1
11C1,20B1,32B1
0.1uFC117
0
0.1uFC160
C1490.1uF
C770.1uF
C1850.1uF
1
0.1uFC35
3
2
5
4
C790.1uF
6
C1300.1uF 0.1uF
C98
9
8
0.1uFC127
7
B19
B59
11
10
VCC_5
TDIA4
TDOB4
TMSA3
TRDYA36
A1TRST
A10
A16
A59
B18
A60REQ64
RSTA15
SBOA41
SDONEA40
SERRB42
STOPA38
TCKB2
B8
IRDYB35
LOCKB39
M66ENB49
PARA43
PERRB40
PRSNT1B9
PRSNT2B11
REQ
B26
B37DEVSEL
A34FRAME
GNTA17
IDSELA26
INTAA6
INTBB7
INTCA7
INTD
AD7B53
B52AD8
A49AD9
CLKB16
C_BE0A52
C_BE1B44
C_BE2B33
C_BE3
AD28A22
AD29B21
AD3B56
AD30A20
AD31B20
AD4A55
AD5B55
AD6A54
AD20A29
AD21B29
AD22A28
AD23B27
AD24A25
AD25B24
AD26A23
AD27B23
AD13A46
AD14B45
AD15A44
AD16A32
B32AD17
AD18A31
AD19B30
AD2A57
5V: 145154-1
3V: 145154-1
ACK64B60
AD0A58
AD1B58
AD10B48
AD11A47
AD12B47
15
14
11D1,18C1,20B1,32B1
11C8,13C1,18C1,20B1,32B1
13
12
11C1,13C1,18C1,20B1,32B8
SLOT6
0
1
11D8,13C1,18C1,20B1,32B8
11D8,13C1,18C1,20B1,32B8
11B1,13C1,18C1,20B1,32A1
11B1,13C1,18C1,20B1,32A1
11A8,13C1,18C1,20B1,32A1
11D1,13C1,18C1,20B1,32A1
11B8,13C1,18C1,20B1,32A1
11A8,20B1,32A1
3
2
1
0
2
3
6D1,11C1,18D1,32A1
6B1,11A1,23C1,26A8,27A8,28A8,30A8,32A8
13B8,16C8,26B1,27B1,28B1,30B1,32B1
33
R40
32A8
C1440.1uF
22
57A1,9A8,11B1,13D1,18D1,22D1,32A1
0.1uF 0.1uFC50
0.1uFC167
<,,,annot_deleted,>
SLOT6_TDOSLOT5_TDO
11A8,13D1,18C1,20C1,32B1
11B1,13D1,18C1,20C1,32B1
11D1,32B1
VCC_5
C88
PCIB4_M66EN PCI_B4
PCIB4_REQ64* PCI_B4
PCI_B4PCIB4_ACK64*
PCIB_CLK(0:6) PCI_B4NC
NC
PCIB4_GNT*(1:5) PCI_B4
PCIB4_REQ*(1:5) PCI_B4
TRST*TMSTCK
PCIB4_AD(31:0)
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCIB4_CBE*(3:0)PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCIB4_INT*(0:3)
PCIB_PCIRST* PCI_B4
PCIB4_FRAME* PCI_B4
PCIB4_DEVSEL* PCI_B4
PCIB4_IRDY* PCI_B4
PCIB4_TRDY* PCI_B4
PCIB4_STOP* PCI_B4
PCIB4_LOCK* PCI_B4
PCIB4_PERR* PCI_B4
PCIB4_SERR* PCI_B4
SMBCLK PCI_B4
SMBDAT PCI_B4
PCI_B4
PCIB4_PARPCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
PCI_B4
+12V
A2
-12V
B1
A5 A8 A61 A62 B5
+5V
A9 A11 A14 A19
A53 B25 B31 B36 B41
B43 B54
NC
B10 B14
B6 B61 B62
A12 A13 B12 B13 A18
GND
A24 A30 A35 A37 A42
A48 A56 B3 B15 B17
B22 B28 B34 B38 B46
B57
VIO: 3.3V or 5V
A21 A27 A33 A39 A45
+3.3V
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ArcadiaSlot 7: PCI1, 5V, 33 MHz
Wednesday, October 19, 2005
6:22:10 pm
54321
1 2 3 4 5 6 7 8
A
B
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Date Changed:
Time Changed:Engineer:
Revision:
17
16
23
22
21
20
19
18
VCC_3.3
29
28
27
26
25
24
C780.1uF
C1510.1uF
C1680.1uF 0.1uF
C56
C54 C1340.1uF
6B1
6B1,11A1,23C1,26A8,27A8,28A8,30A8,31A8
VCC_5
C1760.1uF 0.1uF
31
30
6D1,11C1,18D1,31A1
R41
33
3
2
5
5
1
0
7A1,9A8,11B1,13D1,18D1,22D1,31A1
6
11D1,31B1
11D8,13A1,18A1,20B1,31D1
5
4
23
6
10
11C1,20B1,31B1
11D1,20B1,31B1
9
8
11B1,13D1,18C1,20C1,31B1
11A8,13D1,18C1,20C1,31B1
7
14
11C8,13C1,18C1,20B1,31B1
11C1,13C1,18C1,20B1,31B8
13
12
6B1,11B8,23C1,26A8,27A8,28A8,30A8,31A8
11
11D8,13C1,18C1,20B1,31B8
11B1,13C1,18C1,20B1,31A1
11B1,13C1,18C1,20B1,31A1
11A8,13C1,18C1,20B1,31A1
11D1,13C1,18C1,20B1,31A1
11B8,13C1,18C1,20B1,31A1
11A8,20B1,31A1
11D1,18C1,20B1,31B1
15
B19
B59
3
0
1
2
11D8,13C1,18C1,20B1,31B8
TDI
B4TDO
A3TMS
A36TRDY
TRSTA1
A10
A16
A59
REQ
REQ64A60
A15RST
A41SBO
A40SDONE
B42SERR
A38STOP
B2TCK
A4
INTD
B35IRDY
LOCKB39
B49M66EN
A43PAR
B40PERR
B9PRSNT1
B11PRSNT2
B18
C_BE3
DEVSELB37
FRAMEA34
A17GNT
A26IDSEL
A6INTA
B7INTB
A7INTC
B8
B53AD7
AD8B52
AD9A49
B16CLK
A52C_BE0
B44C_BE1
B33C_BE2
B26
A22AD28
B21AD29
B56AD3
A20AD30
AD31B20
A55AD4
B55AD5
A54AD6
A29AD20
AD21B29
A28AD22
B27AD23
A25AD24
B24AD25
A23AD26
B23AD27
A46AD13
B45AD14
A44AD15
A32AD16
AD17B32
A31AD18
B30AD19
A57AD2
SLOT7
5V: 145154-1
3V: 145154-1
B60ACK64
A58AD0
B58AD1
B48AD10
A47AD11
B47AD12
0.1uFC165
3
6B1,11A1,23C1,26A8,27A8,28A8,30A8,31A8
C1250.1uF 0.1uF
C147
0.1uF 0.1uFC83
0.1uFC141
C960.1uF
C74
2
VCC_5
0.1uFC181
0.1uFC119
<,,,annot_deleted,>
NC
NC
1
0
13B8,16C8,26B1,27B1,28B1,30B1,31B1
13B8,16C8,26B1,27B1,28B1,30B1,31B1
31A8
PCIB4_SERR*
SMBCLKSMBDATPCIB4_M66EN
PCIB4_REQ64*PCIB4_ACK64*
PCIB_CLK(0:6)
PCIB4_GNT*(1:5)PCIB4_REQ*(1:5)
TRST*TMSTCK
SLOT7_TDOSLOT6_TDO
PCIB4_CBE*(3:0)
PCIB4_INT*(0:3)
PCIB_PCIRST*
PCIB4_FRAME*PCIB4_DEVSEL*PCIB4_IRDY*PCIB4_TRDY*PCIB4_STOP*PCIB4_LOCK*PCIB4_PERR*
PCIB4_AD(31:0)
1CM_MAXPCIB4_PAR
Date Changed:
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0.1uF
C68 C48
0.1uF
0.1uF
C156
C114
0.1uF
47uF
C107
+
C40
+
C188
47uF
+
C137
47uF
+
C73
47uF
+
47uF47uF
C52
+
C51
0.1uF 0.1uF
C36
C158
0.1uF
0.1uF
C122C65
0.1uF
0.1uF
C136C189
0.1uF
0.1uF
C214
+
VCC_5 VCC_12NVCC_12VCC_3.3
47uF
C190
+
C115
47uF
C70
+
C39
47uF
+
47uF
+
47uF
C139
+
47uF
0.1uF
C293
47uF
+
C186
VCC_5
0.1uF
C286
C290
0.1uF
C203
C146
0.1uF0.1uF
C177
C81
0.1uF
+
VCC_5 VCC_12NVCC_12VCC_3.3
47uF
C180
+
C112
47uF
C67
+
C38
47uF
+
C57
47uF
+
47uF
C138
+
47uF
C47
0.1uF
C143
0.1uF
0.1uF
C59
C126
0.1uF
0.1uF
C171C82
0.1uF
0.1uF
C202
VCC_3.3VCC_12VCC_3.3
0.1uF
C175
+
VCC_5 VCC_12N
C288
0.1uF
+
C182
47uF
+
47uF
C140
C75
47uF
+
47uF
C42
47uF
C58
+
C113
47uF
+
C61
0.1uF 0.1uF
C53
C174
0.1uF
0.1uF
C148C89
0.1uF
0.1uF
C142
0.1uF
0.1uF
C194
VCC_5 VCC_12NVCC_12VCC_3.3
C193
0.1uF
C285
47uF
C289
+
C295
C294
0.1uF
0.1uF
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor Glossary-1
GlossaryThe glossary contains an alphabetical list of terms, phrases, and abbreviations used in this reference manual.
A Architecture. A detailed specification of requirements for a processor or computer system. It does not specify details of how the processor or computer system must be implemented; instead it provides a template for a family of compatible most-significant byte.
Atomic access. A bus access that attempts to be part of a read-write operation to the same address uninterrupted by any other access to that address (the term refers to the fact that the transactions are indivisible). The Power Architecture technology implements atomic accesses through the lwarx/stwcx. instruction pair.
Autobaud. The process of determining a serial data rate by timing the width of a single bit.
B Beat. A single state on the MPC603e bus interface that may extend across multiple bus cycles. A MPC603e transaction can be composed of multiple address or data beats.
Big-endian. A byte-ordering method in memory where the address n of a word corresponds to the most-significant byte. In an addressed memory word, the bytes are ordered (left to right) 0, 1, 2, 3, with 0 being the most-significant byte. See Secondary cache.
Boundedly undefined. A characteristic of certain operation results that are not rigidly prescribed by the Power Architecture technology. Boundedly-undefined results for a given operation may vary among implementations and between execution attempts in the same implementation.
Although the architecture does not prescribe the exact behavior for when results are allowed to be boundedly undefined, the results of executing instructions in contexts where results are allowed to be boundedly undefined are constrained to ones that could have been achieved by executing an arbitrary sequence of defined instructions, in valid form, starting in the state the machine was in before attempting to execute the given instruction.
Breakpoint. A programmable event that forces the core to take a breakpoint exception.
Burst. A multiple-beat data transfer whose total size is typically equal to a cache block.
MPC8555E Configurable Development System Reference Manual, Rev. 1
Glossary-2 Freescale Semiconductor
Glossary
Bus clock. Clock that causes the bus state transitions.
Bus master. The owner of the address or data bus; the device that initiates or requests the transaction.
C Cache. High-speed memory containing recently accessed data or instructions (subset of main memory).
Cache block. A small region of contiguous memory that is copied from memory into a cache. The size of a cache block may vary among processors; the maximum block size is one page. In Power Architecture processors, cache coherency is maintained on a cache-block basis. Note that the term ‘cache block’ is often used interchangeably with ‘cache line.’
Cache coherency. An attribute wherein an accurate and common view of memory is provided to all devices that share the same memory system. Caches are coherent if a processor performing a read from its cache is supplied with data corresponding to the most recent value written to memory or to another processor’s cache.
Cache flush. An operation that removes from a cache any data from a specified address range. This operation ensures that any modified data within the specified address range is written back to main memory. This operation is generated typically by a Data Cache Block Flush (dcbf) instruction.
Caching-inhibited. A memory update policy in which the cache is bypassed and the load or store is performed to or from main memory.
Cast out. A cache block that must be written to memory when a cache miss causes a cache block to be replaced.
Changed bit. One of two page history bits found in each page table entry (PTE). The processor sets the changed bit if any store is performed into the page. See also page access history bits and referenced bit.
Clean. An operation that causes a cache block to be written to memory, if modified, and then left in a valid, unmodified state in the cache.
Clear. To cause a bit or bit field to register a value of zero. See also set.
Completer. In PCI-X, a completer is the device addressed by a transaction (other than a split completion transaction). If a target terminates a transaction with a split response, the completer becomes the initiator of the subsequent split completion.
Glossary
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor Glossary-3
Context synchronization. An operation that ensures that all instructions in execution complete past the point where they can produce an exception, that all instructions in execution complete in the context in which they began execution, and that all subsequent instructions are fetched and executed in the new context. Context synchronization may result from executing specific instructions (such as isync or rfi) or when certain events occur (such as an exception).
Copy-back operation. A cache operation in which a cache line is copied back to memory to enforce cache coherency. Copy-back operations consist of snoop push-out operations and cache cast-out operations.
D Denormalized number. A nonzero floating-point number whose exponent has a reserved value, usually the format's minimum, and whose explicit or implicit leading significand bit is zero.
Direct-mapped cache. A cache in which each main memory address can appear in only one location within the cache, operates more quickly when the memory request is a cache hit.
Double data rate. Memory that allows data transfers at the start and end of a clock cycle, thereby, doubling the data rate.
E Effective address (EA). The 32-bit address specified for a load, store, or an instruction fetch. This address is then submitted to the MMU for translation to either a physical memory address or an I/O address.
Exception. A condition encountered by the processor that requires special, supervisor-level processing.
Exception handler. A software routine that executes when an exception is taken. Normally, the exception handler corrects the condition that caused the exception, or performs some other meaningful task (that may include aborting the program that caused the exception). The address for each exception handler is identified by an exception vector offset defined by the architecture and a prefix selected via the MSR.
Exclusive state. MEI state (E) in which only one caching device contains data that is also in system memory.
F Frame-check sequence (FCS). Specifies the standard 32-bit cyclic redundancy check (CRC) obtained using the standard CCITT-CRC polynomial on all fields except the preamble, SFD, and CRC.
Fetch. Retrieving instructions from either the cache or main memory and placing them into the instruction queue.
MPC8555E Configurable Development System Reference Manual, Rev. 1
Glossary-4 Freescale Semiconductor
Glossary
Flush. An operation that causes a cache block to be invalidated and the data, if modified, to be written to memory.
G General-purpose register (GPR). Any of the 32 registers in the general-purpose register file. These registers provide the source operands and destination results for all integer data manipulation instructions. Integer load instructions move data from memory to GPRs and store instructions move data from GPRs to memory.
Gigabit media-independent interface (GMII) sublayer. Sublayer that provides a standard interface between the MAC layer and the physical layer for 1000-Mbps operation. It isolates the MAC layer and the physical layer, enabling the MAC layer to be used with various implementations of the physical layer.
Guarded. The guarded attribute pertains to out-of-order execution. When a page is designated as guarded, instructions and data cannot be accessed out-of-order.
H Harvard architecture. An architectural model featuring separate caches and other memory management resources for instructions and data.
I IEEE 754. A standard written by the Institute of Electrical and Electronics Engineers that defines operations and representations of binary floating-point numbers.
Illegal instructions. A class of instructions that are not implemented for a particular processor. These include instructions not defined by the architecture. In addition, for 32-bit implementations, instructions that are defined only for 64-bit implementations are considered to be illegal instructions. For 64-bit implementations instructions that are defined only for 32-bit implementations are considered to be illegal instructions.
Implementation. A particular processor that conforms to the architecture, but may differ from other architecture-compliant implementations (for example, in design, feature set, and implementation of optional features).
Inbound ATMU windows. Mappings that perform address translation from the external address space to the local address space, attach attributes and transaction types to the transaction, and map the transaction to its target interface.
Inter-packet gap. The gap between the end of one Ethernet packet and the beginning of the next transmitted packet.
Integer unit. An execution unit in the core responsible for executing integer instructions.
In-order. An aspect of an operation that adheres to a sequential model. An operation is said to be performed in-order if, at the time that it is performed, it is known to be required by the sequential execution model. See Out-of-order.
Glossary
MPC8555E Configurable Development System Reference Manual, Rev. 1
Freescale Semiconductor Glossary-5
Instruction latency. The total number of clock cycles necessary to execute an instruction and make ready the results of that instruction.
K Kill. An operation that causes a cache block to be invalidated without writing any modified data to memory.
L Latency. The number of clock cycles necessary to execute an instruction and make ready the results of that execution for a subsequent instruction.
L2 cache. Level-2 cache. See Secondary cache.
Least-significant bit (lsb). The bit of least value in an address, register, field, data element, or instruction encoding.
Least-significant byte (LSB). The byte of least value in an address, register, data element, or instruction encoding.
Little-endian. A byte-ordering method in memory where the address n of a word corresponds to the least-significant byte. In an addressed memory word, the bytes are ordered (left to right) 3, 2, 1, 0, with 3 being the most-significant byte. See Big-endian.
Local access window. Mapping used to translate a region of memory to a particular target interface, such as the DDR SDRAM controller or the PCI controller. The local memory map is defined by a set of eight local access windows. The size of each window can be configured from 4 Kbytes to 2 Gbytes.
M Media access control (MAC) sublayer. Sublayer that provides a logical connection between the MAC and its peer station. Its primary responsibility is to initialize, control, and manage the connection with the peer station.
Medium-dependent interface (MDI) sublayer. Sublayer that defines different connector types for different physical media and PMD devices.
Media-independent interface (MII) sublayer. Sublayer that provides a standard interface between the MAC layer and the physical layer for 10/100-Mbps operations. It isolates the MAC layer and the physical layer, enabling the MAC layer to be used with various implementations of the physical layer.
Memory access ordering. The specific order in which the processor performs load and store memory accesses and the order in which those accesses complete.
Memory-mapped accesses. Accesses whose addresses use the page or block address translation mechanisms provided by the MMU and that occur externally with the bus protocol defined for memory.
MPC8555E Configurable Development System Reference Manual, Rev. 1
Glossary-6 Freescale Semiconductor
Glossary
Memory coherency. An aspect of caching in which it is ensured that an accurate view of memory is provided to all devices that share system memory.
Memory consistency. Refers to agreement of levels of memory with respect to a single processor and system memory (for example, on-chip cache, secondary cache, and system memory).
Memory management unit (MMU). The functional unit that is capable of translating an effective address (logical address) to a physical address, providing protection mechanisms, and defining caching methods.
Modified/exclusive/invalid (MEI). Cache coherency protocol used to manage caches on different devices that share a memory system. Note that the architecture does not specify the implementation of a MEI protocol to ensure cache coherency.
Modified state. MEI state (M) in which one, and only one, caching device has the valid data for that address. The data at this address in external memory is not valid.
Most-significant bit (msb). The highest-order bit in an address, registers, data element, or instruction encoding.
Most-significant byte (MSB). The highest-order byte in an address, registers, data element, or instruction encoding.
N NaN. An abbreviation for not a number; a symbolic entity encoded in floating-point format. There are two types of NaNs—signaling NaNs and quiet NaNs.
No-op. No-operation. A single-cycle operation that does not affect registers or generate bus activity.
O OCeaN. On-chip network. Non-blocking crossbar switch fabric. Enables full duplex port connections at 128 Gb/s concurrent throughput and independent per port transaction queuing and flow control. Permits high bandwidth, high performance, as well as the execution of multiple data transactions.
Out-of-order. Operation is said to be out-of-order when it is not guaranteed to be required by the sequential execution model, such as the execution of an instruction that follows another instruction that may alter the instruction flow. For example, execution of instructions in an unresolved branch is said to be out-of-order, as is the execution of an instruction behind another instruction that may yet cause an exception. The results of operations that are performed out-of-order are not committed to architected resources until it can be ensured that these results adhere to the in-order, or sequential execution model.
Glossary
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Outbound ATMU windows. Mappings that perform address translations from local 32-bit address space to the address spaces of RapidIO or PCI/PCI-X, which may be much larger than the local space. Outbound ATMU windows also map attributes such as transaction type or priority level.
P Packet. A unit of binary data that can be routed through a network. Sometimes packet is used to refer to the frame plus the preamble and start frame delimiter (SFD).
Page. A region in memory. The OEA defines a page as a 4-Kbyte area of memory, aligned on a 4-Kbyte boundary.
Page access history bits. The changed bits and referenced bits in the PTE keep track of the access history within the page. The referenced bit is set by the MMU whenever the page is accessed for a read or write operation. The changed bit is set when the page is stored into. See changed bit and referenced bit.
Page fault. A page fault is a condition that occurs when the processor attempts to access a memory location that does not reside within a page not currently resident in physical memory. On PowerPC processors, a page fault exception condition occurs when a matching, valid page table entry (PTE[V] = 1) cannot be located.
Page table. A table in memory is comprised of page table entrys, or PTEs. It is further organized into eight PTEs per PTEG (page table entry group). The number of PTEGs in the page table depends on the size of the page table (as specified in the SDR1 register).
Page table entry (PTE). Data structures containing information used to translate effective address to physical address on a 4-Kbyte page basis. A PTE consists of 8 bytes of information in a 32-bit processor and 16 bytes of information in a 64-bit processor.
Physical coding sublayer (PCS). Sublayer responsible for encoding and decoding data stream to and from the MAC sublayer. Medium (1000BASEX) 8B/10B coding is used for fiber. Medium (1000BASET) 8B1Q coding is used for unshielded twisted pair (UTP).
Physical medium attachment (PMA) sublayer. Sublayer responsible for serializing code groups into a bit stream suitable for serial bit-oriented physical devices (SerDes) and vice versa. Synchronization is also performed for proper data decoding in this sublayer. The PMA sits between the PCS and the PMD sublayers. For fiber medium (1000BASEX) the interface on the PMD side of the PMA is a 1-bit 1250-MHz signal, while on the PMA PCS side the interface is a 10-bit interface (TBI) at 125 MHz. The TBI is an alternative to the GMII interface. If the TBI is used, the gigabit Ethernet controller must be capable of performing the PCS function. For UTP medium, the PMD interface side of the PMA consists of 4 pair of 62.5-MHz PAM5 encoded signals, while the PCS side provides the 1250-Mbps input to a 8B1Q4 PCS.
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Glossary
Physical medium dependent (PMD) sublayer. Sublayer responsible for signal transmission. The typical PMD functionality includes amplifier, modulation, and wave shaping. Different PMD devices may support different media.
Physical memory. The actual memory that can be accessed through the system’s memory bus.
Pipelining. A technique that breaks operations, such as instruction processing or bus transactions, into smaller distinct stages or tenures (respectively) so that a subsequent operation can begin before the previous one has completed.
Precise exceptions. A category of exception for which the pipeline can be stopped so instructions that preceded the faulting instruction can complete and subsequent instructions can be flushed and redispatched after exception handling has completed.
Primary opcode. The most-significant 6 bits (bits 0–5) of the instruction encoding that identifies the type of instruction.
Program order. The order of instructions in an executing program. More specifically, this term is used to refer to the original order in which program instructions are fetched into the instruction queue from the cache.
Protection boundary. A boundary between protection domains.
Protection domain. A protection domain is a segment, a virtual page, a BAT area, or a range of unmapped effective addresses. It is defined only when the appropriate relocate bit in the MSR (IR or DR) is 1.
Q Quad word. A group of 16 contiguous locations starting at an address divisible by 16.
Quiesce. To come to rest. The processor is said to quiesce when an exception is taken or a sync instruction is executed. The instruction stream is stopped at the decode stage and executing instructions are allowed to complete to create a controlled context for instructions that may be affected by out-of-order, parallel execution. See Context synchronizations.
R rA. The rA instruction field is used to specify a GPR to be used as a source or destination.
rB. The rB instruction field is used to specify a GPR to be used as a source.
rD. The rD instruction field is used to specify a GPR to be used as a destination.
rS. The rS instruction field is used to specify a GPR to be used as a source.
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RapidIO. High-performance, packet-switched, interconnect architecture that provides reliability, increased bandwidth, and faster bus speeds in an intra-system interconnect. Designed to be compatible with integrated communications processors, host processors, and networking digital signal processors,
Record bit. Bit 31 (or the Rc bit) in the instruction encoding. When it is set, updates the condition register (CR) to reflect the result of the operation.
Reconciliation sublayer. Sublayer that maps the terminology and commands used in the MAC layer into electrical formats appropriate for the physical layer entities.
Reduced instruction set computing (RISC). An architecture characterized by fixed-length instructions with nonoverlapping functionality and by a separate set of load and store instructions that perform memory accesses.
Referenced bit. One of two page history bits found in each page table entry. The processor sets the referenced bit whenever the page is accessed for a read or write. See also page access history bits.
Requester. In PCI-X, a requester is an initiator that first introduces a transaction into the PCI-X domain.If a transaction is terminated with a split response, the requester becomes the target of the subsequent split completion.
Reservation. The processor establishes a reservation on a cache block of memory space when it executes an lwarx instruction to read a memory semaphore into a GPR.
Reservation station. A buffer between the dispatch and execute stages that allows instructions to be dispatched even though the results of instructions on which the dispatched instruction may depend are not available.
S Secondary cache. A cache memory that is typically larger and has a longer access time than the primary cache. A secondary cache may be shared by multiple devices. Also referred to as L2, or level-2, cache.
Sequence. In PCI-X, a sequence is one or more transactions associated with carrying out a single logical transfer by a requester. Each transaction in the same sequence carries the same unique sequence ID.
Set (v). To write a nonzero value to a bit or bit field; the opposite of clear. The term ‘set’ may also be used to generally describe the updating of a bit or bit field.
Set (n). A subdivision of a cache. Cacheable data can be stored in a given location in one of the sets, typically corresponding to its lower-order address bits. Because several memory locations can map to the same location, cached data is typically placed in the set whose cache block corresponding to that address was used least recently. See Set-associative.
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Glossary
Set-associative. Aspect of cache organization in which the cache space is divided into sections, called sets. The cache controller associates a particular main memory address with the contents of a particular set, or region, within the cache.
Slave. The device addressed by a master device. The slave is identified in the address tenure and is responsible for supplying or latching the requested data for the master during the data tenure.
Snooping. Monitoring addresses driven by a bus master to detect the need for coherency actions.
Snoop push. Response to a snooped transaction that hits a modified cache block. The cache block is written to memory and made available to the snooping device.
Stall. An occurrence when an instruction cannot proceed to the next stage.
Sticky bit. A bit that when set must be cleared explicitly.
Superscalar machine. A machine that can issue multiple instructions concurrently from a conventional linear instruction stream.
Supervisor mode. The privileged operation state of a processor. In supervisor mode, software, typically the operating system, can access all control registers and can access the supervisor memory space, among other privileged operations.
Synchronization. A process to ensure that operations occur strictly in order. See Context synchronizations.
Synchronous exception. An exception that is generated by the execution of a particular instruction or instruction sequence. There are two types of synchronous exceptions, precise exceptions and imprecise.
System memory. The physical memory available to a processor.
T Time-division multiplex (TDM). A single serial channel used by several channels taking turns.
Tenure. The period of bus mastership. For the 603e, there can be separate address bus tenures and data bus tenures. A tenure consists of three phases: arbitration, transfer, and termination.
Throughput. The measure of the number of instructions that are processed per clock cycle.
Transaction. A complete exchange between two bus devices. A transaction is typically comprised of an address tenure and one or more data tenures, which may overlap or occur separately from the address tenure. A transaction may be minimally comprised of an address tenure only.
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Transfer termination. Signal that refers to both signals that acknowledge the transfer of individual beats (of both single-beat transfer and individual beats of a burst transfer) and to signals that mark the end of the tenure.
Translation lookaside buffer (TLB). A cache that holds recently-used page table entry.
U User mode. The operating state of a processor used typically by application software. In user mode, software can access only certain control registers and can access only user memory space. No privileged operations can be performed. Also referred to as problem state.
V Virtual address. An intermediate address used in the translation of an effective address to a physical address.
Virtual memory. The address space created using the memory management facilities of the processor. Program access to virtual memory is possible only when it coincides with physical memory.
W Way. A location in the cache that holds a cache block, its tags, and status bits.
Word. A 32-bit data element.
Write-back. A cache memory update policy in which processor write cycles are directly written only to the cache. External memory is updated only indirectly, for example, when a modified cache block is cast out to make room for newer data.
Write-through. A cache memory update policy in which all processor write cycles are written to both the cache and memory.
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Glossary
PN 924-75516, Rev. BDocument Number: MPC8555CDSx3RMRev. 1, 11/2006
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