MPC5200B User’s Manual - NXP Semiconductors · 2016-11-23 · arising out of the application or...

MPC5200B User’s Manual

MPC5200BUMRev. 35/2010

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RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative.

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MPC5200BUMRev. 35/2010

http://www.freescale.comhttp://www.freescale.com/epp

Freescale Semiconductor Table of Contents-iii

Table of Contents

Chapter 1

Introduction1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.2.1 Embedded e300 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51.2.2 BestComm I/O Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-71.2.3 Controller Area Network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-81.2.4 Byte Data Link Controller - Digital BDLC-D . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-81.2.5 System Level Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-91.2.6 SDRAM Controller and Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-101.2.7 Multi-Function External LocalPlus Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-101.2.8 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-111.2.9 Systems Debug and Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-111.2.10 Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

Chapter 2

Signal Descriptions2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12.2 Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Chapter 3

Memory Map3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13.2 Internal Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23.3 MPC5200B Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.3.1 MPC5200B Internal Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33.3.2 External Busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43.3.3 Memory Map Space Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

Chapter 4

Resets and Reset Configuration4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14.2 Hard and Soft Reset Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2.1 Power-On Reset—PORRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

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4.2.2 Hard Reset—HRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24.2.3 Soft Reset—SRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.3 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34.4 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44.5 Other Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54.6 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Chapter 5

Clocks and Power Management5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15.2 Clock Distribution Module (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15.3 MPC5200B Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.3.1 MPC5200B Top Level Clock Relations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45.3.2 e300 Core Clock Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-75.3.3 Processor Bus (XLB) Clock Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-95.3.4 SDRAM Memory Controller Clock Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-95.3.5 IPB Clock Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-105.3.6 PCI Clock Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-105.4.1 Full-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115.4.2 Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115.4.3 e300 Core Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115.4.4 Deep-Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

5.5 CDM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-155.5.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

Chapter 6

e300 Processor Core6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16.2 MPC5200B e300 Processor Core Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . 6-16.3 e300 Core Reference Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26.4 Not Supported e300 Core Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.4.1 Not Supported Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36.4.2 Not Supported XLB Parity Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Chapter 7

System Integration Unit (SIU)7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17.2 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2.1 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17.2.2 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

Freescale Semiconductor Table of Contents-v

7.2.3 Programming Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-57.2.4 Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.3 General Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-257.3.1 GPIO Pin Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-287.3.2 GPIO Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32

7.4 General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-657.4.1 Timer Configuration Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-657.4.2 Mode Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-657.4.3 Programming Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-667.4.4 GPT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-66

7.5 Slice Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-737.5.1 SLT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-73

7.6 Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-777.6.1 Real-Time Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-787.6.2 Programming Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-787.6.3 RTC Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-79

Chapter 8

SDRAM Memory Controller8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18.2 Terminology and Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.2.1 “Endian”-ness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.3.1 Devices Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-58.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17

8.4.1 External Signals (SDRAM Side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-178.4.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-188.4.3 Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-198.4.4 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19

8.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-248.5.1 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-248.5.2 Read Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25

8.6 Programming the SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-258.6.1 Memory Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26

8.7 Address Bus Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-368.7.1 Example—Physical Address Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38

Chapter 9

LocalPlus Bus (External Bus Interface)9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29.3 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

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9.3.1 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39.3.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-59.4.1 Non-MUXed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-69.4.2 MUXed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10

9.5 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-129.5.1 Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-129.5.2 Chip Selects Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-149.5.3 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15

9.6 DMA (BestComm) Interface (SCLPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-169.7 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16

9.7.1 Chip Select/LPC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-169.7.2 SCLPC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-279.7.3 SCLPC FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33

Chapter 10

PCI Controller10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-210.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

10.2 PCI External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-410.2.1 PCI_AD[31:0] — Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-410.2.2 PCI_CBE[3:0] — Command/Byte Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-410.2.3 PCI_DEVSEL — Device Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-410.2.4 PCI_FRAME — Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-410.2.5 PCI_IDSEL — Initialization Device Select . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-510.2.6 PCI_IRDY — Initiator Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-510.2.7 PCI_CLK — PCI Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-510.2.8 PCI_PERR — Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-510.2.9 PCI_RST — Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-510.2.10PCI_SERR — System Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-510.2.11PCI_STOP — Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-510.2.12PCI_TRDY — Target Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-610.3.1 PCI Controller Type 0 Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . 10-910.3.2 General Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1810.3.3 Communication Sub-System Interface Registers . . . . . . . . . . . . . . . . . . . . . 10-30

10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5610.4.1 PCI Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5610.4.2 Initiator Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6410.4.3 Configuration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6510.4.4 XL bus Initiator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6510.4.5 XL bus Target Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7310.4.6 Communication Sub-System Initiator Interface . . . . . . . . . . . . . . . . . . . . . . 10-76

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10.4.7 PCI - Supported Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8010.4.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-80

10.5 PCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8010.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-81

10.6.1 XL bus Initiated Transaction Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8110.6.2 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8210.6.3 XL bus Arbitration Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-85

Chapter 11

ATA Controller11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-111.2 BestComm Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.2.1 BestComm Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-211.2.2 BestComm Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.3 ATA Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-311.3.1 ATA Host Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-311.3.2 ATA FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1411.3.3 ATA Drive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19

11.4 ATA Host Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3111.4.1 PIO State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3211.4.2 DMA State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33

11.5 Signals and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3411.6 ATA Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3611.7 ATA Bus Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-38

11.7.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3811.7.2 ATA Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3911.7.3 ATA Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3911.7.4 ATA Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42

11.8 ATA RESET/Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5111.8.1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5111.8.2 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-51

11.9 ATA I/O Cable Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-52

Chapter 12

Universal Serial Bus (USB)12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-112.2 Data Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-212.3 Host Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.3.1 Communication Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-212.3.2 Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

12.4 Host Control (HC) Operational Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-612.4.1 Programming Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7

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12.4.2 Control and Status Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-712.4.3 Memory Pointer Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1612.4.4 Frame Counter Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2112.4.5 Root Hub Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27

Chapter 13

BestComm13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-113.2 BestComm Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-213.3 Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-313.4 Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-313.5 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-413.6 Memory Map/ Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-413.7 Task Table (Entry Table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-413.8 Task Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-413.9 Variable Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-413.10Function Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-513.11Context Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-513.12External DMA Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-513.13External DMA Breakpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-513.14BestComm XLB Address Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-613.15BestComm DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6

13.15.1Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-613.16On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3413.17Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-34

13.17.1Task Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3413.17.2Variable Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-36

Chapter 14

Fast Ethernet Controller (FEC)14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-314.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

14.2.1 Full- and Half-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-314.2.2 10Mbps and 100Mbps MII Interface Operation . . . . . . . . . . . . . . . . . . . . . . . 14-314.2.3 10Mbps 7-Wire Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-414.2.4 Address Recognition Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-414.2.5 Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

14.3 I/O Signal Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-414.3.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5

14.4 FEC Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-814.4.1 Control and Status (CSR) Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9

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14.4.2 MIB Block Counters Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1014.4.3 FEC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1314.4.4 FIFO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36

14.5 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4614.5.1 Hardware Controlled Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4614.5.2 User Initialization (Prior to Asserting ETHER_EN) . . . . . . . . . . . . . . . . . . . . 14-4714.5.3 Frame Control/Status Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4814.5.4 Network Interface Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5014.5.5 FEC Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5114.5.6 Ethernet Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5114.5.7 Full-Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5614.5.8 Inter-Packet Gap Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5714.5.9 Collision Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5714.5.10Internal and External Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5814.5.11Ethernet Error-Handling Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-58

Chapter 15

Programmable Serial Controller (PSC)15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1

15.1.1 PSC Functions Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-315.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

15.2 Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-515.2.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-615.2.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7

15.3 PSC Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5215.3.1 PSC in UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5315.3.2 PSC in Codec Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5915.3.3 PSC in AC97 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7415.3.4 PSC in IrDA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-80

15.4 PSC FIFO System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8815.4.1 RX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9015.4.2 TX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9115.4.3 Looping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9215.4.4 Multidrop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-93

Chapter 16

XLB Arbiter16.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1

16.1.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-116.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4

16.2.1 XLB Arbiter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-416.2.2 Arbiter Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19

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Chapter 17

Serial Peripheral Interface (SPI)17.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1

17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-217.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

17.2 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-217.2.1 Master In/Slave Out (MISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-317.2.2 Master Out/Slave In (MOSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-317.2.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-317.2.4 Slave-Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3

17.3 Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-417.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1117.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1117.4.2 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1117.4.3 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1217.4.4 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1317.4.5 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1717.4.6 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1717.4.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1917.4.8 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2017.4.9 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21

Chapter 18

Inter-Integrated Circuit (I2C)18.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1

18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-218.2 I2C Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3

18.2.1 START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-318.2.2 STOP Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3

18.3 Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-718.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7

18.4 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2418.5 Transfer Initiation and Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24

18.5.1 Post-Transfer Software Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2418.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2518.5.3 Special Note on AKF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-25

Freescale Semiconductor Table of Contents-xi

Chapter 19

Controller Area Network (MSCAN)19.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-119.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-219.3 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3

19.3.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-319.3.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3

19.4 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-319.5 Memory Map / Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4

19.5.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-419.5.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6

19.6 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2519.6.1 Identifier Registers (IDR0–IDR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2719.6.2 Data Segment Registers (DSR0–DSR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28

19.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3019.7.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3019.7.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3119.7.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3419.7.4 Protocol Violation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3819.7.5 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3819.7.6 Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4019.7.7 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4119.7.8 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4119.7.9 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4519.7.10Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4619.7.11Recovery from STOP or WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-46

Chapter 20

Byte Data Link Controller (BDLC)20.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-120.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-120.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-220.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-620.5 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-720.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7

20.6.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-720.7 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7

20.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-720.7.2 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-720.7.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8

20.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2320.8.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-23

Table of Contents-xii Freescale Semiconductor

20.8.2 Mux Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3620.8.3 Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3820.8.4 Transmitting A Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4020.8.5 Receiving A Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4420.8.6 Transmitting An In-Frame Response (IFR) . . . . . . . . . . . . . . . . . . . . . . . . . 20-4820.8.7 Receiving An In-Frame Response (IFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5720.8.8 Special BDLC Module Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5920.8.9 BDLC Module Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-60

20.9 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6420.9.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-64

Chapter 21

Debug Support and JTAG Interface21.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-121.2 TAP Link Module (TLM) and Slave TAP Implementation . . . . . . . . . . . . . . . . . . . . . . . 21-121.3 TLM and TAP Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5

21.3.1 Test Reset (TRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-521.3.2 Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-521.3.3 Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-621.3.4 Test Data In (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-621.3.5 Test Data Out (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6

21.4 Slave Test Reset (STRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-621.4.1 Enable Slave—ENA[0:n] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-621.4.2 Select DR Link—SEL[0:n] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-621.4.3 Slave Test Data Out—STDO[0:n] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7

21.5 TAP State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-721.6 e300 Core JTAG/COP Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-821.7 TLM Link DR Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9

21.7.1 TLM:TLMENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-921.7.2 TLM:PPCENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9

21.8 TLM Test Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-921.8.1 IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1021.8.2 BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1021.8.3 SAMPLE/PRELOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1021.8.4 EXTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1121.8.5 CLAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1121.8.6 HIGHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11

21.9 e300 COP/BDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11

Freescale Semiconductor Table of Contents-xiii

Appendix A

Acronyms and Terms

Appendix B

Revision HistoryB.1 Changes Between Revisions 1.3 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1B.2 Changes Between Revisions 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Table of Contents-xiv Freescale Semiconductor

MPC5200B User’s Manual, Rev. 3

Freescale Semiconductor 1-1

Chapter 1 Introduction

1.1 OverviewThe digital communication networking and consumer markets require significant processor performance to enable operating systems and applications such as VxWorks™, QNX™, JAVA and soft modems. High integration is essential to reducing device and systems costs. The MPC5200B is specifically designed to meet these market needs while building on the family of microprocessors that use PowerPC™ architecture. For more information on PowerPC architecture, see “The Programming Environments Manual for 32-bit Implementations of the PowerPC Architecture”.

The MPC5200B integrates a high performance e300 core with a rich set of peripheral functions focused on communications and systems integration. The e300 core design is based on the PowerPC™ core architecture. The MPC5200B incorporates an innovative I/O subsystem, which isolates routine maintenance of peripheral functions from the embedded e300 core.

The MPC5200B supports a dual external bus architecture. It has a high speed SDRAM Bus interface that connects directly to the e300 core. In addition, the MPC5200B has a LocalPlus Bus used as a generalized interface to system level peripheral devices and debug environments.

1.1.1 Features

Key features are shown below.• e300 core

— Superscalar architecture— 760MIPS at 400MHz (-40 to +85°C)— 16k Instruction cache, 16k Data cache— Double precision FPU— Instruction and Data MMU— Standard & Critical interrupt capability

• SDRAM / DDR Memory Interface— up to 132MHz operation— SDRAM and DDR SDRAM support — 256-MByte addressing range per Chip Select (Two CS lines available)— 32-bit data bus— Built-in initialization and refresh

Introduction


1-2 Freescale Semiconductor

• Flexible multi-function External Bus Interface— Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices— 8 programmable Chip Selects— Non multiplexed data access using 8/16/32 bit data bus with up to 26 bit address— Short or Long Burst capable— Multiplexed data access using 8/16/32 bit data bus with up to 25 bit address

• Peripheral Component Interconnect (PCI) Controller— Version 2.2 PCI compatibility— PCI initiator and target operation— 32-bit PCI Address/Data bus — 33 and 66 MHz operation— PCI arbitration function

• ATA Controller— Version 4 ATA compatible external interface—IDE Disk Drive connectivity

• BestComm DMA subsystem— Intelligent virtual DMA Controller— Dedicated DMA channels to control peripheral reception and transmission— Local memory (SRAM 16kBytes)

• 6 Programmable Serial Controllers (PSC), configurable for:— UART or RS232 interface — CODEC interface for Soft Modem, Master/Slave CODEC Mode, I2S and AC97— Full duplex SPI mode— IrDA mode from 2400 bps to 4 Mbps

• Fast Ethernet Controller (FEC) — Supports 100Mbps IEEE 802.3 MII, 10Mbps IEEE 802.3 MII, 10Mbps 7-wire interface

• Universal Serial Bus Controller (USB) — USB Revision 1.1 Host— Open Host Controller Interface (OHCI)— Integrated USB Hub, with two ports.

• Two Inter-Integrated Circuit Interfaces (I2C)• Serial Peripheral Interface (SPI)• Dual CAN 2.0 A/B Controller (MSCAN)

— Motorola Scalable CAN (MSCAN) architecture— Implementation of version 2.0A/B CAN protocol— Standard and extended data frames

• J1850 Byte Data Link Controller (BDLC)— J1850 Class B data communication network interface compatible and ISO compatible for low

speed (

Introduction



• Systems level features— Interrupt Controller supports 4 external interrupt request lines and 47 internal interrupt sources— GPIO/Timer functions

– Up to 56 total GPIO pins (depending on functional multiplexing selections) that support a variety of interrupt/Wake Up capabilities.

– 8 GPIO pins with timer capability supporting input capture, output compare and pulse width modulation (PWM) functions

— Real-time Clock with 1 second resolution— Systems Protection (watch dog timer, bus monitor)— Individual control of functional block clock sources— Power management: Nap, Doze, Sleep, Deep Sleep modes— Support of Wake Up from low power modes by different sources (GPIO, RTC, CAN)

• Test/Debug features— JTAG (IEEE 1149.1 test access port)— Common On-Chip Processor (COP) debug port

• On-board PLL and clock generation• Software

— QNX— VXWorks— Linux— Software Modem capable— JAVA

1.2 ArchitectureThe following areas comprise the MPC5200B system architecture:

• Embedded e300 Core• BestComm I/O Subsystem• Controller Area Network (CAN)• Byte Data Link Controller - Digital BDLC-D• System Level Interfaces• SDRAM Controller and Interface• Multi-Function External LocalPlus Bus• Power Management• Systems Debug and Test• Physical Characteristics

A dynamically managed external pin multiplexing scheme minimizes overall pin count. The result is low cost packaging and board assembly costs.

Figure 1-1 shows a simplified MPC5200B block diagram.

MP

C5200B

User’s M

anu

al, Rev. 3

1-4Freescale S

emiconductor

Intro

du

ction

Figure 1-1. Simplified Block Diagram—MPC5200B

e300 Core

SDRAM / DDR

JTAG / COPInterface

Reset / Clock

MS

CA

N

Real-Time Clock

System Functions

Interrupt Controller

GPIO/Timers

PCI Bus Controller

LocalPlus Controller

ATA Host Controller

Systems Interface Unit (SIU)

SDRAM / DDR

CommBus

LocalBestC

omm

DM

A

SR

AM

16K

Bus

J1850

US

B

SP

I

I 2C

Ethernet

PS

C

Memory Controller

Generation

2x2x2x6x

Introduction



The MPC5200B supports a dual external bus architecture consisting of:1. An SDRAM Bus2. A multi-function LocalPlus Bus

The SDRAM Bus has a Memory Controller interface which supports standard SDRAM and Double Data Rate (DDR) SDRAM devices. The Memory Controller has 13 Memory Address (MA) lines multiplexed with 32 Data Bus lines. Standard SDRAM control signals are included.

The high-speed Memory Controller SDRAM interface connects directly to the microprocessor, allowing optimized instruction and data bursting. The dedicated memory interface, coupled with on-chip 16 Kilobyte instruction and 16Kilobyte data caches, enables high performance for computer intensive applications, such as Java and soft modems. Still, plenty of processing power remains for peripheral management and system control tasks.

The LocalPlus Bus provides for connection of external peripheral devices, disk storage, and slower speed memory. The LocalPlus Bus also supports an external Boot ROM/FLASH/SRAM interface.

The MPC5200B integrates a high performance e300 core with an I/O subsystem containing an intelligent Direct Memory Access (DMA) unit, BestComm. The BestComm unit is capable of:

• Responding to peripheral interrupts, independent of the e300 core.• Providing low level peripheral management, protocol processing, and peripheral data movement

functions.

The MPC5200B has an optimized peripheral mix to support today’s embedded automotive and telematics requirements.

Figure 1-2 shows an MPC5200B-based system.

1.2.1 Embedded e300 Core

The MPC5200B embedded e300 core is derived from Freescale’s (formerly Motorola) MPC603e family of Reduced Instruction Set Computer (RISC) microprocessors. The e300 core is a high-performance, low-power implementation of the PowerPC superscalar architecture. The MPC5200B e300 core contains:

• 16 KBytes of instruction cache• 16 KBytes of data cache

Caches are 4-way set associative and use the Least Recently Used (LRU) replacement algorithm.

Four independent execution units are used:1. Branch Processing Unit (BPU)2. Integer Unit (IU)3. Load/Store Unit (LSU)4. System Register Unit (SRU)

Introduction



Figure 1-2. MPC5200B-Based System

Up to 3 instructions can be issued and retired per clock. Most instructions execute in a single cycle. The core contains an integrated Floating Point Unit (FPU), a Data Cache Memory Management Unit and an Instruction Cache Memory Management Unit. The core implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addressing and integer data types of 8-, 16-, and 32-bits.

Enhancements in this core version, specific to embedded automotive/telematics include:• Improved interrupt latency (critical interrupt)• New MMU with additional 8 BAT (16 total) registers and 1KByte page management

Ethernet

Printer or I/O port

IC Control

SDRAM/DDR Controller Demodulator

SRAM Interface

PCI Bus

ATA Interface

SIU Transport &

Video Decoder/

Audio

SDRAM

SDRAM

Video

Graphics

Encoder

Flash,

Boot ROM

IDE Disk

Interface

Memory

Controller

MPC5200

Control SRAM DMA

Embedded

e300 Core

(MPC603e)

AC97

Debug Interface

PS

C1

PS

C2

PS

C3

US

B

I2C

1

PS

C4

EN

ET

PS

C5

PS

C6

UART

Codec

UART

IrDA Rx/Tx

Introduction



The e300 core performance for SPEC95 benchmark integer operations, ranges between 4.4 and 5.1 at 200MHz. In Drystone 2.1MIPS, the e300 core is 280 MIPS at 200 MHz.

1.2.2 BestComm I/O Subsystem

BestComm contains an intelligent DMA unit. This unit provides a front-line interrupt control and data movement interface via a separate peripheral bus to the on-chip peripheral functions. This leaves the e300 core free for higher level activities. The concurrent operation enables a significant boost in overall systems performance.

BestComm supports up to 16 simultaneously enabled DMA tasks from up to 32 DMA requestors. Also included is:

• A hardware logic unit• A hardware CRC unit

BestComm uses internal buffers for prefetched reads and post writes. Bursting is used whenever possible. This optimizes both internal and external bus activity.

1.2.2.1 Programmable Serial Controllers (PSCs)

The MPC5200B supports six PSCs. Each can be configured to operate in different modes. PSCs support both synchronous and asynchronous protocols. They are used to interface to external full-function modems or external CODECs for soft modem support. 8, 16, 24 and 32-bit data widths are supported. PSCs can be configured to support 1200 baud POTS modem, SPI, I2S, V.34 or V.90 protocols. The standard UART interface supports connection to an external terminal/computer for debug support.

1.2.2.2 10/100 Ethernet Controller

The Ethernet Controller supports the following standard MAC-PHY interfaces:• 100 Mbps IEEE 802.3 MII• 10 Mbps IEEE 802.3 MII• 10 Mbps 7-wire interface

The controller is full duplex, supports a programmable maximum frame length and retransmission from the Tx FIFO following a collision.

1.2.2.3 Universal Serial Bus (USB)

The MPC5200B supports two USB channels. The USB Controller implements the USB Host Controller/Root Hub in compliance with the USB1.1 specification. The user may choose to have either one or two USB ports on the root hub, each of which can interface to an off-chip USB transceiver. The Host Controller supports the Open Host Controller Interface (OHCI) standard.

Introduction



1.2.2.4 Infrared Support

The MPC5200B supports the IrDA format. All three IrDA modes are supported (SIR, MIR, FIR) to 4.0 Mbps. The required 48 MHz clock can be generated internally or supplied externally on an input pin.

1.2.2.5 Inter-Integrated Circuit (I2C)

The MPC5200B supports two I2C channels. Both master and slave interfaces can be controlled directly by the processor or can use the BestComm Controller to buffer Tx/Rx data when the I2C data rate is high.

1.2.2.6 Serial Peripheral Interface (SPI)

The SPI module allows full-duplex, synchronous, serial communication between the MPC5200B and peripheral devices. It supports master and slave mode, double-buffered operation and can operate in a polling or interrupt driven environment.

1.2.3 Controller Area Network (CAN)

The MPC5200B supports two CAN channels. The CAN is an asynchronous communications protocol used in automotive and industrial control systems. It is a high speed, short distance, priority based protocol that runs on a variety of mediums. For example, transmission media of fiber optic cable or unshielded twisted wire pairs can be used.

MSCAN supports both standard and extended identifier (ID) message formats specified in BOSCH CAN protocol specification, revision 2.0, part B. Each MSCAN module contains:

• 4 receive buffers (with FIFO storage scheme)• 3 transmit buffers• Flexible maskable identifier filters

1.2.4 Byte Data Link Controller - Digital BDLC-D

The MPC5200B supports J1850 Class B data communication network interface compatible and ISO compatible for low speed (

Introduction



1.2.5 System Level Interfaces

System Level Interfaces are listed below and described in the sections that follow:• Chip Selects• Interrupt Controller• Timers• General Purpose Input/Outputs (GPIO)• Functional Pin Multiplexing• Real-Time Clock (RTC)

1.2.5.1 Chip Selects

The MPC5200B integrates the most common system integration interfaces and signals. There are 8 fully programmable external chip selects, which are independent of the SDRAM interface. LP_CS0 has special features to support a Boot ROM. Two of the chip selects may be used by the IDE disk drive interface, when enabled.

1.2.5.2 Interrupt Controller

The Interrupt Controller has 4 external interrupt signals and manages both external and internal interrupts. All interrupt levels and priorities are programmable.

The Interrupt Controller takes advantage of the new critical interrupt feature defined by the PowerPC architecture. This allows e300 core interrupts outside operating system boundaries, for critical functions such as real-time packet processing.

1.2.5.3 Timers

MPC5200B integrates several timer functions required by most embedded systems:• Two internal Slice timers can create short-cycle periodic interrupts.• A WatchDog timer can interrupt the processor if not regularly serviced, catching software

hang-ups.

A bus monitor monitors bus cycles and provides an interrupt if transactions take longer than a prescribed time.

1.2.5.4 General Purpose Input/Outputs (GPIO)

A total of 56 pins on the MPC5200B can be programmed as GPIOs.• 8 pins can interrupt the processor.• 8 pins can support a “Wake Up” capability that brings the MPC5200B out of low power modes.• 8 pins are “output only” GPIOs.

Introduction



The remaining GPIO pins support a simple “set the output level” or “detect the input level” type GPIO function. Eight I/Os can be connected to one of eight general purpose timers to support input capture, output compare or pulse width modulation functions.

The number of GPIOs available in the various modes depends on the peripheral functionality required. See pin descriptions and I/O port maps below for more information.

1.2.5.5 Functional Pin Multiplexing

Many serial/parallel port pins serve multiple functions, allowing flexibility in optimizing the system to meet a specific set of integration requirements. For example, when PSC3 interfaces to a full function external modem, 10 pins are required:

• PSC3_TXD—Transmit Data• PSC3_RXD—Receive Data• PSC3_RTS—Ready to Send• PSC3_CTS—Clear to Send• PSC3_CD—Carrier Detect• MODEM_RI—Ring Indicator• MODEM_DSR—Hook Switch• MODEM_IO—Control I/O (A0 gain)• MODEM_IO—Control I/O (Mode 1)• MODEM_IO—Control I/O (Mode 2)

If PSC3 connects to a simple UART, only the first four signals (shown above) are required. The remaining 6 signals can be used as GPIOs.

If a 7-wire Ethernet connection is adequate, the additional 11 Ethernet I/Os can be used as GPIOs.

1.2.5.6 Real-Time Clock (RTC)

An RTC is included on the MPC5200B. The RTC provides a 2-pin interface to an external 32.768 kHz crystal. This allows internal time-of-day/calendar tracking, as well as clock based periodic interrupts.

1.2.6 SDRAM Controller and Interface

The MPC5200B high speed SDRAM Controller supports both standard SDRAM and Double Data Rate (DDR) SDRAM devices. It supports up to 256 MBytes per chip select (2 Chip Select lines available) with a 32-bit interface. Memory sizes of 64 Mbit, 128 Mbit, 256 Mbit and 512 Mbit are supported.

1.2.7 Multi-Function External LocalPlus Bus

The MPC5200B supports a multi-function external LocalPlus Bus to allow connections to PCI and ATA compliant devices, as well as external ROM/SRAM.

The MPC5200B integrates a 3.3 V, PCI V2.2 compatible external LocalPlus Bus controller and interface. This bus is a 32-bit multiplexed address/data bus.

Introduction



The external LocalPlus Bus provides support for an ATA disk drive interface. ATA control signals (chip selects, write/read, etc.) are provided independent of the PCI control signals. This prevents bus contention. However, the 32-bit data bus is shared. When The MPC5200B recognizes an external LocalPlus Bus access meant for the ATA Controller, ATA control logic arbitrates for PCI interface control. The 32-bit address/data bus function is transformed into 16bits of ATA data and 3bits of ATA address.

The external LocalPlus Bus also allows connection to external memory or peripheral devices that adhere to a ROM or SRAM-like interface. These devices occupy a separate location in the memory map and have independent control signals. When an internal access is decoded to fall in the SRAM/ROM memory space, the 32-bit PCI address/data bus is transformed into either:

• 24bits of address and 8bits of data• 16bits of address and 16bits of data.

The MPC5200B supports a reset configuration mode common on the family of processors that use the PowerPC architecture. 16 bits of configuration information is driven and sampled during reset to establish the initial processor configuration.

1.2.8 Power Management

The MPC5200B is processed in a low-power static CMOS technology. In addition, it supports the dynamic power management modes available on the MPC52xx series processors using the e300 core. These modes include:

• Nap• Dose• Sleep• Deep sleep

In deep sleep, all internal clocks can be disabled, thus, reducing the power draw to CMOS leakage levels.

A Wake Up capability is supported by CAN, RTC, several GPIOs and the interrupt lines. Therefore, the MPC5200B can be shut down to a low-power standby mode, then re-enabled by one of the Wake Up inputs without resetting the MPC5200B.

1.2.9 Systems Debug and Test

The MPC5200B supports the Common On-chip Processor (COP) debug capability common on other microprocessors that use the PowerPC architecture. The COP interface supports features such as:

• Memory down load• Single step instruction execution• Break/watch point capability• Access to internal registers• Pipeline tracking, etc.

The MPC5200B also supports a JTAG IEEE 1149.1 controller and test access port (TAP).

Introduction



1.2.10 Physical Characteristics• 1.5 V internal, 3.3 V external operation (2.5 V for DDR interface)• TTL compatible I/O pins• 272-pin Plastic Ball Grid Array (PBGA)



Chapter 2 Signal Descriptions

2.1 OverviewThe MPC5200B contains a e300 core, an internal DMA engine, BestComm, multiple functional blocks and associated I/O ports. There are two external data/address bus structures, the LocalPlus bus and SDRAM bus. A block diagram of the MPC5200B structure is shown in Figure 1-1.

In general, the LocalPlus bus connects to external SRAM, FLASH, peripheral devices, etc. The LocalPlus bus is capable of executing standard memory cycles, PCI cycles and ATA cycles. In addition to the data and address bus pins on the LocalPlus bus, there are pins specifically dedicated to ATA transactions, PCI transactions and standard memory transactions. When the MPC5200B is released from reset, Chip Select 0 is the only active chip select. Program execution must always start from the “boot device” on the LocalPlus bus. There are 8 chip select signals associated with the LocalPlus bus. It’s possible to execute from every CS. Also every CS can address “data space”.

The SDRAM bus interfaces to Synchronous DRAM. Both Single Data Rate and Double Data Rate DRAMs are supported. Executable programs are generally loaded into memory residing on the SDRAM bus. The SDRAM bus has a 32-bit wide data/address bus structure and is capable of burst accesses. It is possible to execute program code over the LocalPlus bus. However, the data transfer rate on the SDRAM bus is many times faster than LocalPlus.

There are 16 peripheral functional blocks on the MPC5200B. These are General Purpose I/O, I2C, TIMER, PSC1, PSC2, PSC3, PSC4, PSC5, PSC6, Ethernet, USB, MSCAN, SPI and J1850. Each of these functional blocks are routed to one or more I/O ports through a system of multiplexers. A functional block can only be routed to one I/O port at a time and in many cases, several functional blocks can be routed to the same I/O port.

The I/O ports are Dedicated GPIO Group, I2C Group, Timer Group, PSC1 Group, PSC2 Group, PSC3 Group, PSC6 Group, Ethernet Group, and the USB Group.

Figure 2-3 through Figure 2-12 present detailed on the multiplexing options for each I/O port.

MPC5200B is packaged in a 272-pin Plastic Ball Gate Array (PBGA). Package ball locations are shown in Figure 2-1. See Figure 2-2 for case diagram.

Signal Descriptions



Figure 2-1. 272-Pin PBGA Pin Detail

Table 2-1 gives a list of MPC5200B I/O signals sorted by package ball name. Table 2-2 gives the same list sorted by signal name.

Many signal pins can have multiple functions depending on internal register settings. These additional functions are described in Table 2-3 through Table 2-31.

KJHGFEDCBA

YWVUTRPNML

101 2 3 4 5 6 7 8 9 11 13 14 15 16 17 18 19 2012

View Looking at Pins (Balls)

A1 signal: A20 signal:test_mode_1 mem_dqm_2

Notes:Table 2-1 and Table 2-2 give the signals on each pin/ball.

Y20 signal:timer0

Y1 signal:ext_ad_27

Sig

nal D

escriptio

ns

MP

C5200B

User’s M

anu

al, Rev. 3

Freescale Sem

iconductor2-3

Figure 2-2. 272-Pin PBGA — Top View

A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20TEST_MODE_1 JTAG_TDO JTAG_TDI JTAG_TMS PSC3_8 PSC3_5 PSC3_2 PSC2_4 PSC2_2 PSC1_4 PSC1_1 PSC6_2 PORRESET SRESET SYS_XTAL_IN MEM_MA_1 MEM_MBA_1 MEM_RAS MEM_WE MEM_DQM_2

B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20TEST_SEL_0 TEST_MODE_0 JTAG_TRST JTAG_TCK PSC3_7 PSC3_4 PSC3_1 PSC2_3 PSC2_1 PSC1_3 PSC1_0 PSC6_0 HRESET SYS_PLL_AVDD SYS_PLL_TPA MEM_MA_2 MEM_MA_10 MEM_CS_0 MEM_CAS MEM_MA_4

C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20RTC_XTAL_OUT RTC_XTAL_IN TEST_SEL_1 PSC3_9 PSC3_6 PSC3_3 PSC3_0 CORE_PLL_AVDD PSC2_0 PSC1_2 PSC6_1 GPIO_WKUP_7 PSC6_3 SYS_PLL_AVSS GPIO_WKUP_6 MEM_MA_3 MEM_MA_0 MEM_MBA_0 MEM_MA_5 MEM_MA_6

D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20TIMER_4 TIMER_3 TIMER_2 VSS VDD_CORE VDD_IO VDD_CORE LP_OE VDD_IO VDD_CORE VDD_CORE VDD_MEM_IO VDD_MEM_IO SYS_XTAL_OUT VDD_MEM_IO VSS VDD_MEM_IO MEM_MDQS_2 MEM_MA_7 MEM_MA_8

E01 E02 E03 E04 E17 E18 E19 E20TIMER_7 TIMER_6 TIMER_5 VDD_IO VDD_MEM_IO MEM_MDQ_16 MEM_MA_9 MEM_MA_11

F01 F02 F03 F04 Key for IO Balls: F17 F18 F19 F20USB_7 USB_8 USB_9 VDD_IO A6

Signal Descriptions



Figure 2-3. MPC5200B Peripheral Muxing

11

22

5

ATA chip selects

2

8 4 2

P2 P110 100

5

518 107 10

5 5

5 5 10 14 4

8 Pins 5 pins 5 pins 10 pins 18 pins 10 pins 4 pins

muxmuxmuxmux

PSC6

SPI

PSC5

PSC2

PSC1

GPIO

TIMERS

mux mux mux

PSC1Group

PSC2Group

PSC3Group

EthernetGroup

USBGroup

PSC6Group

MSCAN

TimerGroup

8

4 pins

mux

I2CGroup

I2C

Dedicated GPIO

Reset Conf.

TSIZE_1

mux

5

J1850

PSC4

PSC3

4

mux

2 4

System chip

selects

2

SDRAMCS1

44

4 8

ETHER

USB

Signal Descriptions



2.2 Pinout TablesTable 2-1. Signals by Ball/Pin (Sheet 1 of 4)

Ball/Pin Pin Name Ball/Pin Pin Name

A01 TEST_MODE_1 B16 MEM_MA_2

A02 JTAG_TDO B17 MEM_MA_10

A03 JTAG_TDI B18 MEM_CS_0

A04 JTAG_TMS B19 MEM_CAS

A05 PSC3_8 B20 MEM_MA_4

A06 PSC3_5 C01 RTC_XTAL_OUT

A07 PSC3_2 C02 RTC_XTAL_IN

A08 PSC2_4 C03 TEST_SEL_1

A09 PSC2_2 C04 PSC3_9

A10 PSC1_4 C05 PSC3_6

A11 PSC1_1 C06 PSC3_3

A12 PSC6_2 C07 PSC3_0

A13 PORRESET C08 CORE_PLL_AVDD

A14 SRESET C09 PSC2_0

A15 SYS_XTAL_IN C10 PSC1_2

A16 MEM_MA_1 C11 PSC6_1

A17 MEM_MBA_1 C12 GPIO_WKUP_7

A18 MEM_RAS C13 PSC6_3

A19 MEM_WE C14 SYS_PLL_AVSS

A20 MEM_DQM_2 C15 GPIO_WKUP_6

B01 TEST_SEL_0 C16 MEM_MA_3

B02 TEST_MODE_0 C17 MEM_MA_0

B03 JTAG_TRST C18 MEM_MBA_0

B04 JTAG_TCK C19 MEM_MA_5

B05 PSC3_7 C20 MEM_MA_6

B06 PSC3_4 D01 TIMER_4



B09 PSC2_1 D04 VSS_IO/CORE

B10 PSC1_3 D05 VDD_CORE

B11 PSC1_0 D06 VDD_IO

B12 PSC6_0 D07 VDD_CORE

B13 HRESET D08 LP_OE

B14 SYS_PLL_AVDD D09 VDD_IO

B15 SYS_PLL_TPA D10 VDD_CORE

D11 VDD_CORE H04 VDD_IO

D12 VDD_MEM_IO H17 VDD_MEM_IO

D13 VDD_MEM_IO H18 MEM_MDQ_20

Signal Descriptions



D14 SYS_XTAL_OUT H19 MEM_DQM_1

D15 VDD_MEM_IO H20 MEM_MDQS_1

D16 VSS_IO/CORE J01 ETH_3

D17 VDD_MEM_IO J02 ETH_4

D18 MEM_MDQS_2 J03 ETH_10

D19 MEM_MA_7 J04 ETH_17

D20 MEM_MA_8 J09 VSS_IO/CORE

E01 TIMER_7 J10 VSS_IO/CORE



E04 VDD_IO J17 MEM_MDQ_22

E17 VDD_MEM_IO J18 MEM_MDQ_21

E18 MEM_MDQ_16 J19 MEM_MDQ_8

E19 MEM_MA_9 J20 MEM_MDQ_9

E20 MEM_MA_11 K01 ETH_0

F01 USB_7 K02 ETH_1

F02 USB_8 K03 ETH_2

F03 USB_9 K04 VDD_CORE

F04 VDD_IO K09 VSS_IO/CORE

F17 VDD_MEM_IO K10 VSS_IO/CORE

F18 MEM_MDQ_17 K11 VSS_IO/CORE

F19 MEM_MA_12 K12 VSS_IO/CORE

F20 MEM_CLK_EN K17 VDD_MEM_IO

G01 USB_3 K18 MEM_MDQ_23



G04 USB_6 L01 ETH_9

G17 MEM_MDQ_18 L02 ETH_16

G18 MEM_MDQ_19 L03 ETH_5

G19 MEM_CLK L04 ETH_11

G20 MEM_CLK L09 VSS_IO/CORE

H01 USB_0 L10 VSS_IO/CORE



L17 MEM_DQM_3 R18 MEM_MDQ_29

L18 MEM_MDQS_3 R19 MEM_MDQ_5

L19 MEM_MDQ_12 R20 MEM_MDQ_4

L20 MEM_MDQ_13 T01 PCI_CLOCK

M01 ETH_13 T02 EXT_AD_26

M02 ETH_12 T03 EXT_AD_28

Table 2-1. Signals by Ball/Pin (Sheet 2 of 4)


Signal Descriptions



M03 ETH_8 T04 VDD_IO

M04 VDD_CORE T17 VDD_MEM_IO

M09 VSS_IO/CORE T18 MEM_MDQ_30



M12 VSS_IO/CORE U01 PCI_REQ

M17 VDD_MEM_IO U02 PCI_IDSEL

M18 MEM_MDQ_24 U03 EXT_AD_24

M19 MEM_MDQ_14 U04 VSS_IO/CORE

M20 MEM_MDQ_15 U05 VDD_IO

N01 ETH_7 U06 VDD_IO

N02 ETH_6 U07 VDD_CORE

N03 ETH_15 U08 EXT_AD_15

N04 ETH_14 U09 VDD_IO

N17 MEM_MDQ_25 U10 VDD_IO

N18 MEM_MDQ_26 U11 EXT_AD_6

N19 MEM_DQM_0 U12 VDD_CORE

N20 MEM_MDQS_0 U13 VDD_IO

P01 IRQ1 U14 LP_ACK

P02 IRQ2 U15 VDD_CORE

P03 IRQ0 U16 VDD_IO

P04 VDD_CORE U17 VSS_IO/CORE

P17 VDD_MEM_IO U18 MEM_MDQ_31

P18 MEM_MDQ_27 U19 MEM_MDQ_1

P19 MEM_MDQ_7 U20 MEM_MDQ_0

P20 MEM_MDQ_6 V01 EXT_AD_31

R01 IRQ3 V02 EXT_AD_20

R02 PCI_RESET V03 EXT_AD_22

R03 EXT_AD_30 V04 EXT_AD_18

R04 PCI_GNT V05 PCI_FRAME

R17 MEM_MDQ_28 V06 PCI_STOP

V07 PCI_PAR Y04 EXT_AD_19

V08 EXT_AD_13 Y05 EXT_AD_17

V09 EXT_AD_11 Y06 PCI_IRDY

V10 EXT_AD_9 Y07 PCI_PERR

V11 EXT_AD_4 Y08 PCI_CBE_1



V14 LP_ALE Y11 EXT_AD_7

V15 LP_CS2 Y12 EXT_AD_3



Signal Descriptions



V16 LP_CS5 Y13 LP_TS

V17 ATA_DRQ Y14 LP_CS1

V18 TIMER_1 Y15 LP_CS4

V19 I2C_0 Y16 ATA_ISOLATION

V20 I2C_2 Y17 ATA_IOR

W01 EXT_AD_29 Y18 ATA_DACK

W02 EXT_AD_25 Y19 ATA_INTRQ

W03 EXT_AD_23 Y20 TIMER_0

W04 EXT_AD_16

W05 PCI_TRDY

W06 PCI_CBE_2

W07 PCI_DEVSEL

W08 PCI_SERR

W09 EXT_AD_14

W10 PCI_CBE_0

W11 EXT_AD_8

W12 EXT_AD_5

W13 EXT_AD_1

W14 LP_CS0

W15 LP_CS3

W16 LP_RW

W17 ATA_IOW

W18 ATA_IOCHRDY

W19 I2C_1

W20 I2C_3

Y01 EXT_AD_27

Y02 PCI_CBE_3

Y03 EXT_AD_21



Signal Descriptions



Table 2-2. Signals by Signal Name (Sheet 1 of 4)

Signal Name Ball/Pin Signal Name Ball/Pin

ATA_DACK Y18 EXT_AD_6 U11

ATA_DRQ V17 EXT_AD_7 Y11

ATA_INTRQ Y19 EXT_AD_8 W11

ATA_IOCHRDY W18 EXT_AD_9 V10

ATA_IOR Y17 EXT_AD_10 Y10

ATA_IOW W17 EXT_AD_11 V09

ATA_ISOLATION Y16 EXT_AD_12 Y09

LP_CS0 W14 EXT_AD_13 V08

LP_CS1 Y14 EXT_AD_14 W09

LP_CS2 V15 EXT_AD_15 U08

LP_CS3 W15 EXT_AD_16 W04

LP_CS4 Y15 EXT_AD_17 Y05

LP_CS5 V16 EXT_AD_18 V04

ETH_0 K01 EXT_AD_19 Y04

ETH_1 K02 EXT_AD_20 V02

ETH_2 K03 EXT_AD_21 Y03

ETH_3 J01 EXT_AD_22 V03

ETH_4 J02 EXT_AD_23 W03

ETH_5 L03 EXT_AD_24 U03

ETH_6 N02 EXT_AD_25 W02

ETH_7 N01 EXT_AD_26 T02

ETH_8 M03 EXT_AD_27 Y01

ETH_9 L01 EXT_AD_28 T03

ETH_10 J03 EXT_AD_29 W01

ETH_11 L04 EXT_AD_30 R03

ETH_12 M02 EXT_AD_31 V01

ETH_13 M01 GPIO_WKUP_6 C15

ETH_14 N04 GPIO_WKUP_7 C12

ETH_15 N03 CORE_PLL_AVDD C08

ETH_16 L02 CORE_PLL_AVSS NC (no connection)

ETH_17 J04 HRESET B13

EXT_AD_0 V13 I2C_0 V19

EXT_AD_1 W13 I2C_1 W19

EXT_AD_2 V12 I2C_2 V20

EXT_AD_3 Y12 I2C_3 W20

EXT_AD_4 V11 PSC6_0 B12

EXT_AD_5 W12 PSC6_2 A12

PSC6_3 C13 MEM_MBA_1 A17

PSC6_1 C11 MEM_MDQ_0 U20

Signal Descriptions



IRQ0 P03 MEM_MDQ_1 U19

IRQ1 P01 MEM_MDQ_2 T20

IRQ2 P02 MEM_MDQ_3 T19

IRQ3 R01 MEM_MDQ_4 R20

JTAG_TCK B04 MEM_MDQ_5 R19

JTAG_TDI A03 MEM_MDQ_6 P20

JTAG_TDO A02 MEM_MDQ_7 P19

JTAG_TMS A04 MEM_MDQ_8 J19

JTAG_TRST B03 MEM_MDQ_9 J20

LP_ACK U14 MEM_MDQ_10 K19

LP_ALE V14 MEM_MDQ_11 K20

LP_OE D08 MEM_MDQ_12 L19

LP_RW W16 MEM_MDQ_13 L20

LP_TS Y13 MEM_MDQ_14 M19

MEM_CAS B19 MEM_MDQ_15 M20

MEM_CLK_EN F20 MEM_MDQ_16 E18

MEM_CS_0 B18 MEM_MDQ_17 F18

MEM_DQM_0 N19 MEM_MDQ_18 G17

MEM_DQM_1 H19 MEM_MDQ_19 G18

MEM_DQM_2 A20 MEM_MDQ_20 H18

MEM_DQM_3 L17 MEM_MDQ_21 J18

MEM_MA_0 C17 MEM_MDQ_22 J17

MEM_MA_1 A16 MEM_MDQ_23 K18

MEM_MA_2 B16 MEM_MDQ_24 M18

MEM_MA_3 C16 MEM_MDQ_25 N17

MEM_MA_4 B20 MEM_MDQ_26 N18

MEM_MA_5 C19 MEM_MDQ_27 P18

MEM_MA_6 C20 MEM_MDQ_28 R17

MEM_MA_7 D19 MEM_MDQ_29 R18

MEM_MA_8 D20 MEM_MDQ_30 T18

MEM_MA_9 E19 MEM_MDQ_31 U18

MEM_MA_10 B17 MEM_MDQS_0 N20

MEM_MA_11 E20 MEM_MDQS_1 H20

MEM_MA_12 F19 MEM_MDQS_2 D18

MEM_MBA_0 C18 MEM_MDQS_3 L18

MEM_CLK G19 PSC3_5 A06

MEM_CLK G20 PSC3_6 C05

MEM_RAS A18 PSC3_7 B05

MEM_WE A19 PSC3_8 A05

PCI_CBE_0 W10 PSC3_9 C04



Signal Descriptions



PCI_CBE_1 Y08 RTC_XTAL_IN C02

PCI_CBE_2 W06 RTC_XTAL_OUT C01

PCI_CBE_3 Y02 SRESET A14

PCI_CLOCK T01 SYS_PLL_AVDD B14

PCI_DEVSEL W07 SYS_PLL_AVSS C14

PCI_FRAME V05 SYS_PLL_TPA B15

PCI_GNT R04 SYS_XTAL_IN A15

PCI_IDSEL U02 SYS_XTAL_OUT D14

PCI_IRDY Y06 TEST_MODE_0 B02

PCI_PAR V07 TEST_MODE_1 A01

PCI_PERR Y07 TEST_SEL_0 B01

PCI_REQ U01 TEST_SEL_1 C03

PCI_RESET R02 TIMER_0 Y20

PCI_SERR W08 TIMER_1 V18

PCI_STOP V06 TIMER_2 D03

PCI_TRDY W05 TIMER_3 D02

PORRESET A13 TIMER_4 D01

PSC1_0 B11 TIMER_5 E03

PSC1_1 A11 TIMER_6 E02

PSC1_2 C10 TIMER_7 E01

PSC1_3 B10 USB_0 H01

PSC1_4 A10 USB_1 H02

PSC2_0 C09 USB_2 H03

PSC2_1 B09 USB_3 G01

PSC2_2 A09 USB_4 G02

PSC2_3 B08 USB_5 G03

PSC2_4 A08 USB_6 G04

PSC3_0 C07 USB_7 F01

PSC3_1 B07 USB_8 F02

PSC3_2 A07 USB_9 F03

PSC3_3 C06 VDD_CORE D05

PSC3_4 B06 VSS_IO/CORE J12

VDD_CORE D10 VSS_IO/CORE K09

VDD_CORE D11 VSS_IO/CORE K10

VDD_CORE K04 VSS_IO/CORE K11

VDD_CORE M04 VSS_IO/CORE K12

VDD_CORE P04 VSS_IO/CORE L09

VDD_CORE U07 VSS_IO/CORE L10





Signal Descriptions



VDD_IO D06 VSS_IO/CORE M09

VDD_IO D09 VSS_IO/CORE M10

VDD_IO E04 VSS_IO/CORE M11

VDD_IO F04 VSS_IO/CORE M12

VDD_IO H4 VSS_IO/CORE U04

VDD_IO T4 VSS_IO/CORE U17

VDD_IO U05 VDD_CORE D07

VDD_IO U06

VDD_IO U09

VDD_IO U10

VDD_IO U13

VDD_IO U16

VDD_MEM_IO D12

VDD_MEM_IO D13

VDD_MEM_IO D15

VDD_MEM_IO D17

VDD_MEM_IO E17

VDD_MEM_IO F17

VDD_MEM_IO H17

VDD_MEM_IO K17

VDD_MEM_IO M17

VDD_MEM_IO P17

VDD_MEM_IO T17

VSS_IO/CORE D04

VSS_IO/CORE D16

VSS_IO/CORE J09

VSS_IO/CORE J10

VSS_IO/CORE J11



Signal Descriptions



Table 2-3. LocalPlus Bus Address / Data Pin Assignments

MPC5200B LocaLPlus Bus Address / Data

Pins

EXT_AD31

EXT_AD30

EXT_AD29

EXT_AD28

EXT_AD27

EXT_AD26

EXT_AD25

EXT_AD24

EXT_AD23

EXT_AD22

EXT_AD21

EXT_AD20

EXT_AD19

EXT_AD18

EXT_AD17

EXT_AD16

EXT_AD15

EXT_AD14

EXT_AD13

EXT_AD12

EXT_AD11

EXT_AD10

EXT_AD9

EXT_AD8

EXT_AD7

EXT_AD6

EXT_AD5

EXT_AD4

EXT_AD3

EXT_AD2

EXT_AD1

EXT_AD0

16 bit Adr, 16 bit Data

D15

D14

D13

D12

D11

D10

D09

D8

D7

D6

D5

D4

D3

D2

D1

D0

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

24 bit Adr, 8 bit Data

D7

D6

D5

D4

D3

D2

D1

D0

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Muxed modes

All Muxed mode Address tenures

0 TS1ZE2

TS1ZE1

TS1ZE0

0 BS1

BS0

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

8 bit Data tenure

D7

D6

D5

D4

D3

D2

D1

D0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

16 bit Data tenureD15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D3

D2

D0

32 bit Data tenureD31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Signal Descriptions



Table 2-4. LocalPlus Pin Functions (Sheet 1 of 3)

PinName BALL

LocalPlusNon-mux

LocalPlusMULTIPLEXED BUS PCI BUS

ATA MOST LargeFlash RESETAddr/Data24/8

Addr/Data16/16

AddressPhase

32-bitData

Phase

16-bitData

Phase

8-bitData

Phase

PCIAddressPhase

32-bitData

Phase

16-bitData

Phase

8-bitData

Phase

EXT_AD_31 V01 D7 D15 0 D31 D15 D7 A31 D31 0 0 D31 D15

EXT_AD_30 R03 D6 D14 TSIZ0 D30 D14 D6 A30 D30 0 0 D30 D14

EXT_AD_29 W01 D5 D13 TSIZ1 D29 D13 D5 A29 D29 0 0 D29 D13

EXT_AD_28 T03 D4 D12 TSIZ2 D28 D12 D4 A28 D28 0 0 D28 D12

EXT_AD_27 Y01 D3 D11 0 D27 D11 D3 A27 D27 0 0 D27 D11

EXT_AD_26 T02 D2 D10 BS1 D26 D10 D2 A26 D26 0 0 D26 D10

EXT_AD_25 W02 D1 D9 BS0 D25 D9 D1 A25 D25 0 0 D25 D9

EXT_AD_24 U03 D0 D8 A24 D24 D8 D0 A24 D24 0 0 D24 D8

EXT_AD_23 W03 A23 D7 A23 D23 D7 0 A23 D23 0 0 D23 D7

EXT_AD_22 V03 A22 D6 A22 D22 D6 0 A22 D22 0 0 D22 D6

EXT_AD_21 Y03 A21 D5 A21 D21 D5 0 A21 D21 0 0 D21 D5

EXT_AD_20 V02 A20 D4 A20 D20 D4 0 A20 D20 0 0 D20 D4

EXT_AD_19 Y04 A19 D3 A19 D19 D3 0 A19 D19 0 0 D19 D3

EXT_AD_18 V04 A18 D2 A18 D18 D2 0 A18 D18 0 0 SA_2 D18 D2

EXT_AD_17 Y05 A17 D1 A17 D17 D1 0 A17 D17 0 0 SA_1 D17 D1

EXT_AD_16 W04 A16 D0 A16 D16 D0 0 A16 D16 0 0 SA_0 D16 D0

EXT_AD_15 U08 A15 A15 A15 D15 0 0 A15 D15 D15 0 D15 D15 A15

EXT_AD_14 W09 A14 A14 A14 D14 0 0 A14 D14 D14 0 D14 D1

MPC5200B User’s Manual - NXP Semiconductors · 2016-11-23 · arising out of the application or...

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Transcript of MPC5200B User’s Manual - NXP Semiconductors · 2016-11-23 · arising out of the application or...