MOSAIC1 - Institut Pluridisciplinaire Hubert CURIEN · Web viewADC Clock and Digital Test...

Mosaic 1Mosaic 1Design documentation

Date Description Revision31/03/2005 Creation V0.106/04/2005 Chapter “analog” complete ,Michal verification V0.1208/04/2005 Chapter “digital” complete V0.2

CONTENTS

CONTENTS........................................................................................................................................................- 1 -

I. MOSAIC1 CHIP ARCHITECTURE.....................................................................................................- 2 -

I.1. GENERAL CHIP DESCRIPTION.............................................................................................................- 2 -I.2. ORGANIZATION OF THE MOSAIC1 CHIP..........................................................................................- 2 -

II. ARRAY OF PIXELS AND PIXEL DESIGN.........................................................................................- 4 -

II.1. PIXEL 1 TO 3: NMOS COMMON SOURCE AMPLIFIER AND 4 MEMORY CELLS......................................- 5 -II.1.a. Standard structures..................................................................................................................- 5 -II.1.b. Test structures..........................................................................................................................- 5 -

II.2. PIXEL 4 TO 5: PMOS COMMON SOURCE AMPLIFIER AND 4 MEMORY CELLS......................................- 7 -II.2.a. Standard structures..................................................................................................................- 7 -II.2.b. Test structures..........................................................................................................................- 8 -

II.3. PIXEL 6: NMOS COMMON SOURCE AMPLIFIER AND 2 CLAMPING CAPACITORS..................................- 9 -II.3.a. Standard structure...................................................................................................................- 9 -II.3.b. Test structure.........................................................................................................................- 10 -

III. DIGITAL BLOCK DESIGN.............................................................................................................- 11 -

III.1. DIGITAL ARCHITECTURE.................................................................................................................- 11 -III.1.a. Digital block concept.............................................................................................................- 11 -III.1.b. External command signals timing diagram...........................................................................- 12 -

III.2. TIMING DIAGRAM FOR PIXEL WITH FOUR CAPACITORS (PIXEL 1 TO 5)...........................................- 12 -III.3. TIMING DIAGRAM FOR PIXEL WITH CLAMPING CAPACITORS (PIXEL6)............................................- 14 -III.4. ADC CLOCK AND DIGITAL TEST SIGNALS.....................................................................................- 15 -

III.4.a. ADC Clock.............................................................................................................................- 15 -III.4.b. Digital Test Signals...............................................................................................................- 16 -

1

I. MOSAIC1 Chip Architecture

I.1. General Chip description.

MOSAIC1 is a monolithic active pixel sensor device designed for charged particle detection and tracking. The chip was implemented in a 0.35µm commercial process from austriamicrosystems (AMS CMOS C35B4C3) through CMP’s facilities. The process features double polysilicons and four metal layers, the nominal power supply Vnom = 3.3V, the gate oxide thickness toxn=7.6nm and twin tubs set in a P-type, so called high resistivity substrate (p = 19 /cm). The chip has been fabricated on the MPW run in …. 2005. The goal of fabrication was to validate the usefulness of in-pixel memory cells. This specific structure is particularly well adapted when the time, during the beams’ crossing, is short in comparison of time between two beams’ crossings. In this case, it is possible to store quickly several frames in pixel’s memory cells during beams’ interaction and, in a second step, read them slowly during the dead time, in order to minimize the impact of speed for the readout.In addition, further test structures were placed to explore AMS 0.35µm technology. Their goal is to increase our knowledge about Nwell-Polysilicium capacitors and limits of AC coupling principle needed, in the pixel, between sensitive element and first amplifier stage.Mosaic1’s design documentation includes the chip organization, detail pixel’s descriptions and basic digital control information.

I.2. Organization of the MOSAIC1 Chip

The die size of MOSAIC1 is 2 X 2.8mm².The chip is divided into two parts: the pixels matrix and its digital control block, a test structure block.

The matrix is composed of an array of 14 X 48 pixels, where the first and the last column are dummies not connected to the readout circuitry. The matrix is divided into 6 groups of 8 rows. Each group represents one pixel’s type described in detail in the next chapter. For each type of pixel, the first 8 valid columns are dedicated to the standard pixel structure whereas the last 4 valid columns are dedicated to test in pixel sub-circuits thanks to additional access points.Columns are directly connected to PAD through in pixel source follower circuitry. Biasing current, needed by the source follower, is common for all pixels connected to the same column and is supplied by a specific circuitry at the end of each column.

The matrix is controlled by a digital block which decodes digital signals from the parallel control interface, selects the active row and supplies pixels’digital control signals. It creates also a clock, at pin “ClockOut”, which can be used directly as an ADC clock by the data acquisition boards to sample outputs of the eight columns connected to standard pixel structure. In order to have the possibility to verify correct operation of the internal digital circuitry, the opportunity to pry several internal signals was introduced to the chip. The choice of one, between four possible total digital signals, is achieved by setting a select word on “SelTestDig<1:0>” lines.

2

The Test structure block is composed of an array of XXXX Nwell-Poly capacitors for a total of C = XX pF. Poly potential is available at “Poly” PAD and diode potential is available at “vdiode_test” PAD. The Test structure block is not independent of the rest of the chip: power supplies are shared with the matrix.

ClockOut

TestDigout

SelTestDig0

SelTestDig1

Vdd

Gnd

Gnd

Vdda

Vdd_diode

Iref

Ib iasPix

Vdda

Vdd_diode

VacPix

VrefPix

Vdiode_test

Poly

Pixel_Out_TS<3>

Pixel_Out_TS<2>

Pixel_Out_TS<1>

Pixel_Out_TS<0>

Vdd

Gnd

Gnd

Ck

InC

kLin

e

InD

ata

InPr

ech

InPw

rOn

InR

ead

InR

eset

InW

rite

Pixe

l_O

ut<0

>

Pixe

l_O

ut<1

>

Pixe

l_O

ut<2

>

Pixe

l_O

ut<3

>

Pixe

l_O

ut<4

>

Pixe

l_O

ut<5

>

Pixe

l_O

ut<6

>

Pixe

l_O

ut<7

>

VcascPixDig

ital

part

14 x 48pixels array35 X 35 µm ²

Readoutdirection

Dum m ycolum ns

M atrixTest-

structures

Output

Mat

rixou

tput

8 Sourcefollowers 4 SF

Nw

ell-P

oly

Cap

acito

rsTe

st-s

truct

ure

8 to Pixel_O ut

4 to Pixel_O ut_TS

Amp. cascodereference (1.4V)

C lamping reference(2V)

Amp. AC référence(0.7 or 2.5 V)

Nw ell-PolyTest-

structures

Output SF currentreference (10µA)

P ixel SF currentreference (10µA)

C lock for DAS

Digital s ignal output

Controlfor

TestD igOut

Pare

llel c

ontr

olin

terf

ace

P1 : 8 row sNmos Amp.4 in-pixel memory cellsC~200fF

P2 : 8 row sidem P1C~100fF

P3 : 8 row sidem P1C~50fF

P4: 8 row sPmos Amp.Ac coupling= poly-poly

P5: 8 row sPmos Amp.Ac coupling=NW ell-poly

P6: 8 row sC lampingmemorycellsC~50 fF

Figure 1 : Simplified structure and pin-out of the MOSAIC1 chip

3

II. Array of pixels and pixel design

The matrix of pixels is divided in six sub-blocks. The division is made horizontally, which means that each row contains always pixel of the same type. Description of content of each pixels and associated name is presented figure 2.The main goal of Mosaic1 is to prove feasibility of integrating memory cells in the pixel. Pixels’ types 1 to 5 include four memory cells working with sample and hold principle and pixel’s type 6 include two memory cells working with clamping capacitors principle. Furthermore, Pixel1TS and Pixel6TS give a direct access to capacitors through a source follower connected to the “Vac” line in order to guaranty the testability of the structure even if sensitive node, AC coupling or amplifier circuit do not work.On the other hand, it was decided to test with Mosaic1 different solutions of in pixel amplifiers. Pixels 1 to 3 and Pixel 6 include Nmos common source amplifier whereas Pixel 4 and 5 include Pmos common source auto-biased amplifier. In order to be independent of the sensitive node and of Ac coupling, Pixel2TS, Pixel4TS and Pixel5TS give a direct access to these amplifiers.

4

Standard StructuresTest

Structures

Pixel1T S : d irec taccess to m em ory

ce lls

P ixe l1T S : d irec taccess to N m os

am p lifier

P ixe l3T S : S elf-b iasw ith no A c coup ling

circu it (D Ccoup ling)

P ixe l4T S : d irec taccess to P m os

am p lifier

P ixe l5T S : d irec taccess to P m os

am p lifier

P ixe l6T S : d irec taccess to

m em oryce lls

P ixe l1 :S e lf-b ias

Nm os CS A m pl.4 Nm os capacito rs

C = 200fF



C = 100fF



C = 50 fF


A c coup ling P o ly-P o ly(C = 50 fF )

Pm os CS A m pl.


Ac coup ling N we ll-Po ly(C = 50 fF )

Pm os CS A m pl.


Nm os CS A m pl.2 P o ly-P oly capacitors

C = 50 fF

8 O u tputs toP ixe l_O ut

4 O utputs toP ixe l_O ut_T S

8 Rows

8 Rows

8 Rows

8 Rows

8 Rows

8 Rows

Figure 2 : Matrix subdivision’s schematic.

II.1. Pixel 1 to 3: Nmos common source amplifier and 4 memory cells

II.1.a. Standard structures

The first three sub-blocks of pixels share the same standard architecture. Signal coming from self-bias sensitive node is shifted from 3.2V (diode ideal voltage before the impact of a particle) to 0.7V thanks to AC coupling circuit composed of a coupling Nwell-Poly capacitor of 50fF and an Nmos transistor with drain and gate connected together. Due to the high impedance of the transistor, voltage applied at the “Vac” line is directly available at the source of the transistor. The coupling capacitor is used to filter DC component and to transmit fast variations of diode signal according to time constant determined by the couple coupling capacitor / transistor’s high impedance.Small variations from diode are next amplified by Nmos common source amplifier with a gain of 15.

5

Four memory cells, commanded by digital signals, are used to store the analog signal from the amplifier. They are composed of four switches connected to four Nmos capacitors referenced to VDDA. Storage capacitances are 200fF for Pixel1, 100fF for Pixel2 and 50fF for Pixel3.

Vdd_diode

Vdda

VcascAm p

Pow erOnAm pVdda

Read

Vdda

Vac

Sw itchM em

PrechM em

VrefM em

S<0> S<1> S<2> S<3>

Self-bias sensitive node

Ac coupling capacitor (50fF)

and biasing transitor

Nmos common source amplifier

(gain = 15 )

Four memory cellsPixel 1 : C~ 200fFPixel 2 : C~ 100fFPixel 3 : C~ 50fF

Source follower amplifier

Figure 3 : Schematic diagram of a single pixel of MOSAIC1 chip (standard pixel).

Timing diagram of digital commands for the four memory cells is presented in next chapter.

II.1.b. Test structures

In order to test separately each parts of the standard structure, three test structures were added in 4 additional columns (as shown in figure 2).

Pixel1TS

The first test structure is designed to measure separately performance of memory cell’s capacitors. The self-bias sensitive node, the AC coupling and the Nmos common source amplifier were replaced by a source follower circuit. External voltage from the “Vac” line is connected to source follower input. The bias current is supplied through the “Ibias_Pixel” line.

6

Vdda

Read

Vdda

Sw itchM em

PrechM em

VrefM em

S<0> S<1> S<2> S<3>

Vdda

Vac

PowerOnAm p

Ibias_P ixel

Source follower 4 memory cellsC = 200fF Source follower

Figure 4 : Schematic diagram of test pixel with direct access to memory capacitors.

Pixel2TS

The second test structure is dedicated of measurement of amplifier’s performances. The self bias sensitive node and the AC coupling circuit are removed and direct access to input amplifier is provided through the “Vac” line.

Vdda

VcascAm p

Pow erO nAm pVdda

Read

Vdda

Sw itchM em

PrechM em

VrefM em

S<0> S<1> S<2> S<3>

Vac

Nmos common source amplifier(gain = 15)

4 memory cellsC = 200fF Source follower

Figure 5 : Schematic diagram of test pixel with direct access to Nmos amplifier.

Pixel3TS

The third test structure is dedicated of exploring DC coupling in AMS0.35 technology. The self-bias sensitive node is here directly connected to amplifier input. Common mode voltage from diodes is set by the “vdd_diode” line.

7

Vdda

VcascAm p

Pow erO nAm pVdda

Read

Vdda

Sw itchM em

PrechM em

VrefM em

S<0> S<1> S<2> S<3>

Vdd _diode

Self-bias without AC

coupling(DC coupling)

Nmos common source amplifier

(gain = 15)


Figure 6 : Schematic diagram of test pixel with DC coupled sensitive node

II.2. Pixel 4 to 5: Pmos common source amplifier and 4 memory cells

II.2.a. Standard structures

Sub-blocks 4 and 5 were designed with the same architecture that sub-blocks 1 to 3 but use a different amplifier. Signal coming from self-bias sensitive node is shifted from 3.2V (diode ideal voltage before the impact of a particle) to 2.5V thanks to a Poly-Poly coupling capacitor for Pixel4 and an Nwell-Poly coupling capacitor for Pixel5 of 50fF both. The coupling capacitor is used to filter DC component of diode signal and to transmit fast variations of diode signal according to time constant determined by the couple coupling capacitor – Nmos transistor’s high impedance.Small variations from diode are next amplified by Pmos common source amplifier with a gain of 7.

8

Vdd a

Read

Vdda

Sw itchM em

PrechM em

VrefM em

S<0> S<1> S<2> S<3>

Vdda

Vac

Pow erO nAm p

AC couplingPixel4 Poly-PolyPixel5Nwell-Poly

C = 50 fF

Pmos common source

amplifier(gain = 7)


Figure 7 : Schematic diagram of single pixel with Pmos common source amplifier.

II.2.b. Test structures

The fourth and fifth test structures are dedicated to measurements of Pmos amplifier performance. The AC coupling circuit is removed and the “Vac” line is connected to amplifier input.

Vdda

Read

Vdda

Sw itchM em

PrechM em

VrefM em

S<0> S<1> S<2> S<3>

Vdda

Vac

Pow erOnAm p

Pmos common source amplifier(gain = 7)


Figure 8 : Schematic diagram of test pixel with direct access to Pmos amplifier.

9

II.3. Pixel 6: Nmos common source amplifier and 2 clamping capacitors

II.3.a. Standard structure

Sub-block 6 reuses Nmos common source amplifier from Pixel 1 to 3 but introduces second type of memory cells based on clamping capacitors principle. . Signal coming from self-bias sensitive node is shifted from 3.2V (diode ideal voltage before the impact of a particle) to 0.7V thanks to AC coupling circuit composed of a coupling Nwell-Poly capacitor of 50fF and an Nmos transistor with drain and gate connected together. Due to the high impedance of the transistor, voltage applied at “Vac” line is directly available to the source of the transistor. The coupling capacitor is used to filter DC component and to transmit fast variations of diode signal according to time constant determined by the couple coupling capacitor / transistor’s high impedance.Small variations from diode are next amplified by Nmos common source amplifier with a gain of 15.Amplifier output is next send to two 100fF Poly-Poly capacitors selected by 2 Nmos switches. Timing diagram of digital commands for clamping capacitors is presented in next chapter.

Vdda

Vdd_diode

Vdd a

Vdda

Vac

VcascAm p

Pow erOnAm p

S<0>

S<3>

S<1>

S<2>

VrefM em

Read

PrechM em

OutSf

Self-bias

sensitive

node

Ac coupling capacitor (50fF)

and biasing transitor

Nmos common source amplifier (gain = 15 )

2 memory cellsC = 100fF Source follower amplifiers

Figure 9 : Schematic diagram of single pixel with clamping capacitors.

10

II.3.b. Test structure

The sixth test structure is used to measure separately performance of memory cells with clamping capacitors. The self-bias sensitive node, the AC coupling and the Nmos common source amplifier were replaced by a source follower circuit. External voltage from the “Vac” line is used as input. The bias current is supplied through “Ibias_Pixel”.

Vdda

Vac

Pow erOnAm p

Ibias_Pixel

Vdda

Vdda

S<1>

S<2>

VrefM em

Read

PrechM em

O utSf

S <0>

S <3>

Source follower 2 memory cellsC = 100fF Source follower

Figure 10 : Schematic diagram of test pixel with direct access to clamping capacitors.

11

III.Digital Block Design

III.1. Digital Architecture

III.1.a. Digital block concept

The digital block was designed to be flexible and to take advantage of the low frequency of the main clock (1 MHz).

In consequence, parts of the digital command signals are generated from an external logic programmable device which continuously provides 8 digital signals to Mosaic1. The low frequencies guaranty the feasibility of such test structure. The external digital signals are sum up in the next table.

Signal Active DescriptionClk Positive-edge Main clock of Mosaic 1. Freq = 1 MHz.

InCkLine Logic-High Flag to change active capacitorInData Logic-High Select switch of pixel capacitorsInPrech Logic-High Precharge pixel internal line before the readoutInRead Logic-High Connect pixel output to column

InPwrOn Logic-High Select pixel amplifier power on switchInReset Logic-Low Global Reset of digital circuitsInWrite Logic-High Connect pixel amplifier to pixel capacitors

Table 1 : Mosaic1 digital signals Input.

12

External digital signals are then sampled and treat by the internal digital block in order to create specific digital command signals for Pixel 1 to 5 and for Pixel 6 (Pixel with clamping capacitors). At the end, generated signals are transferred to a 48 elements’ shift-register which sends signals only to active row. The shift-register circuit is common for all the pixels of the matrix.

Sampling Block

Clk

InC

kLin

e

InD

ata

InPr

ech

InPw

rOn

InR

ead

InR

eset

InW

rite

To o therpixels

T o clam pingpixel

Sh ift Reg

Sh ift Reg

Sh ift Reg

Sh ift Reg

Sh ift Reg

Sh ift Reg

8 8

To 40 pixelsRow s

To 8 pixelsRow s

III.1.b. External command signals timing diagram

External digital command signals are identical for the entire matrix. Nevertheless, two different patterns of digital signals are needed: one for the writing phase and one for the readout phase. During each phases, the pattern is repeated 48 X 4 = 192 times, in order to traverse the shift-register and select, one after the other, in pixel capacitors. 6 clock cycles are needed to command the pixel. Consequently, at main clock frequency = 1 MHz, each phase takes 1.152ms.

Figure 11 : Timing diagram for capacitors writing operation.

13

6µs

Figure 12 : Timing diagram for capacitors readout operation

External digital signals Writing Phase Readout Phase WFigure 13 : Timing diagram send by external logic programmable device.

III.2. Timing diagram for pixel with four capacitors (Pixel 1 to 5)

External digital signals are sampled by Mosaic1 digital circuit with clock supplied by the logic programmable device (1 MHz). A specific digital block dedicated to the first 40 pixels rows treats sampled signals. Five digital signals are created: the main clock divided by 6 (6 cycles are needed to command pixels) and four signals by demultiplexing the “Data” line. These four signals are connected to the four switches of in-pixel memory cells. A total of 8 bits are send to a bus connected to the first 40 elements of the shift-register.

The global behavior of standard pixel’s digital commands is presented in figure 14 with the first and last row for each signal (signals number 0 and 39). Capacitors are selected one after the other with synchronization of “PowerOn” and “Write” lines during writing phase and of “Read” and “Prech” lines during readout phase.

14

1152µs

Selected capacitor

Figure 11 Figure 12

Internal digital signals Writing Phase Readout Phase Writing Phase Readout PhaseFigure 14 : Timing diagram for digital command signals of standard pixel.

These specific synchronizations are presented in figures 15 and 16 with the first capacitor selected (“S<0>” line). In addition, figure 16 shows the ADC clock, generated on line “ClockOut”. Two cycles are needed for each pixel’s capacitor data: first, to sample reference data, second to sample capacitor data. The acquisition scheme is repeated for each capacitor.

Figure 15 : Timing diagram of standard pixel writing phase.

Figure 16 : Timing diagram of standard pixel readout phase.

III.3. Timing diagram for pixel with clamping capacitors (Pixel6)

In parallel with standard pixel’s specific treatment, a second digital block dedicated to the last 8 pixels rows treats sampled signals. As for standard pixel’s digital commands, a digital word is send on 8 bits bus every 6 clock cycles and is changed every 288 clock cycles, i.e. four

15

C1 C2 C3 C4 C1 C2 C3 C4

2 X 1152µs Figure 15 Figure 16

Precharge signal available at analog output

Pixel signal available at analog output

Clock synchronized with pixel analog output

Signals instead of C4 selection is not used

times in 1152µs. In our case, only 3 steps are useful as describe in figures 17 and 18. The remaining time is not used.

Figure 17 : Timing diagram of clamping pixel writing phase.

Nm osComm on

sourceAm plifier

Sensitivenode

Vref

Vref

S<0>

S<3>

S<2>

S<1>Vdda

Read

Vdda

PrechM em

Nm osComm on

sourceAm plifier

Sensitiveno de

Vref

Vref

S<3>

S<2>

S<1>Vdda

Read

Vdd a

PrechM em

S1 is available at amplifier output.C1 voltage = Vref-S1

C2 voltage : not define

Nm osCom m on

sourceAm plifier

Sensitivenode

Vref

Vref

S<0>

S<3>

S<2>

S<1>Vdda

Read

Vdda

Pre chM em

Nm osCom m on

sou rceAm plifier

Sensitivenode

Vref

Vref

S<3>

S<2>

S<1>Vdda

Read

Vdda

Pre chM em

All switches are openC1 voltage and C2 voltage remain constant

NmosCom mon

sourceAm plif ier

Sensitivenode

Vref

Vref

S<0>

S<3>

S<2>

S<1>Vdda

Read

Vdda

PrechMem

Nm osCom mon

sourceAm plifier

Sensitivenode

Vref

Vref

S<0>

S<3>

S<2>

S<1>Vdda

Read

Vdda

PrechMem

S2 is available at amplifier outputOut1 = Vref-S1+S2

C2 voltage = Vref –S2

NmosCom m on

sourceAm plifier

Sensitivenode

Vref

Vref

S<0>

S<3>

S<2>

S<1>Vdda

Read

NmosCom m on

sourceAm plifier

Sensitivenode

Vref

Vref

S<0>

S<3>

S<2>

S<1>Vdda

Read

Vdda

PrechM em

S3 is available at amplifier outputOut1 = Vref –S1 +S2Out2 = Vref-S2+S3

Figure 18 : Schematic diagram of clamping write phase

Standard pixel stores four frames in situ. Furthermore, before reading the analog data, a Precharge data, image of pixel offset, is saved. So, standard pixel’s readout provides eight positive edges ADC clock per pixel. Clamping pixel only needs two ADC clock cycles. So, complete readout of the eight rows of clamping pixel is achieved during the first readout step, i.e. C1 readout step where it si provided 2 positive edge at ADC clock output. During C2 to C4 readout step, analog outputs of the clamping pixel’s block supplies wrong data (see chapter: ADC Clock).

16

Signals instead of C1 selection



S1

S2 S3

Out1

Out2

Out1

Out2

Out1

Out2

Figure 19 : Timing diagram of clamping pixel readout phase

III.4. ADC Clock and Digital Test Signals

III.4.a. ADC Clock

An ADC Clock signal is available at “ClockOut” line. It is only generated during readout phase.

Internal digital signals Writing Phase

Readout Phase

Writing Phase

Readout Phase

Writing Phase

Readout Phase

Writing Phase

Figure 20 : Timing diagram of ADC Clock signal.

ADC Clock signal is common for both pixels’ types.

Figure 21 : Detail of ADC Clock Signal.

III.4.b. Digital Test Signals

17

Clock synchronized with pixel analog output

Standard pixel output Clamping pixel output

Wrong data

In order to have the possibility to verify correct operation of the internal digital circuitry, the opportunity to pry several internal signals was introduced to the chip. The choice of one, between four possible total digital signals, is achieved by setting a select word on “SelTestDig<1:0>” lines. The following table sums up the digital signals available.

SelTestDig0, SelTestDig1 Internal signal on TestDigOut00 ReadSelectSamp<47>01 ClockSelectSamp10 S0SelSamp11 S0SelSampClamp

Table 2 : Choice of internal digital signals

18

MOSAIC1 - Institut Pluridisciplinaire Hubert CURIEN · Web viewADC Clock and Digital Test...

Documents

Transcript of MOSAIC1 - Institut Pluridisciplinaire Hubert CURIEN · Web viewADC Clock and Digital Test...