MOS Transistor Modeling for RF IC Design (Enz)

186 IEEE TRANSACTIONS ON SOLID-STATE CIRCUITS, VOL. 35, NO. 2, FEBRUARY 2000

MOS Transistor Modeling for RF IC DesignChristian C. Enz, Member, IEEE,and Yuhua Cheng, Senior Member, IEEE

Abstract—This paper presents the basis of the modeling of theMOS transistor for circuit simulation at RF. A physical equivalentcircuit that can easily be implemented as a Spice subcircuit is firstderived. The subcircuit includes a substrate network that accountsfor the signal coupling occurring at HF from the drain to the sourceand the bulk. It is shown that the latter mainly affects the outputadmittance 22. The bias and geometry dependence of the subcir-cuit components, leading to a scalable model, are then discussedwith emphasis on the substrate resistances. Analytical expressionsof the parameters are established and compared to measure-ments made on a 0.25-m CMOS process. The parameters andtransit frequency simulated with this scalable model versus fre-quency, geometry, and bias are in good agreement with measureddata. The nonquasi-static effects and their practical implementa-tion in the Spice subcircuit are then briefly discussed. Finally, a newthermal noise model is introduced. The parameters used to char-acterize the noise at HF are then presented and the scalable modelis favorably compared to measurements made on the same devicesused for the -parameter measurement.

Index Terms—Modeling, MOS devices, MOSFET’s, RF CMOSIC, semiconductor device modeling, semiconductor device noise,simulation, SPICE.

I. INTRODUCTION

T ODAY, deep-submicrometer CMOS processes typicallyreach the 50-GHz region and offer low noise figures,

making them serious alternative for RF circuits integration[1]–[5]. In addition, CMOS offers very large scale integration(VLSI) capabilities allowing for a high level of integration.The feasibility of RF CMOS circuits integration has beendemonstrated with prototypes that used even older CMOSprocesses [10]. There is no doubt that in the coming years newwireless products will appear with CMOS as the technologyused for the integration of the RF portion [6]–[12].

Nevertheless, the design of RF circuits for real productsremains a challenge due to the strong constraints on powerconsumption and noise that leave very little margins for theRF IC designer. Therefore, it is crucial to be able to accuratelypredict the performance of the CMOS RF circuits in order toreduce design cycles and have first-time success. Althoughgood results can be obtained for lower frequency circuits(typically below 100 MHz), the simulation of RF circuits inthe gigahertz frequency range with the available MOS compactmodels such as BSIM3v3 [13], [14], MOS Model 9 [15],[16], or EKV [17]–[20] without consideration of the parasiticcomponents gives inaccurate or even wrong results. Therefore,

Manuscript received April 2, 1999; revised October 19, 1999C. Enz was with Conexant Systems, Inc., Newport Beach, CA 92660 USA.

He is now with the Swiss Center for Electronics and Microtechnology (CSEM)and with the Swiss Federal Institute of Technology, Lausanne (EPFL), Switzer-land.

Y. Cheng is with the Conexant Systems Inc., Newport Beach, CA 92660 USA.Publisher Item Identifier S 0018-9200(00)00936-7.

these models have to be enhanced in order to be used for RFCMOS IC design. It can be shown that the strict minimum toimprove the models used for RF circuit simulation is to add ter-minal resistances, mainly a gate resistance [21], [22]. However,this is not sufficient. At HF, the signal coupling through thesubstrate has to be accounted for by adding adequate substrateresistances [21], [23]–[32]. Also, nonquasi-static (NQS) effectshave to be accounted for at least for the slower-channeldevice and/or for nonminimum channel length devices used forexample in bias circuits [21], [36]–[51].1

Section II presents the modeling of the MOS transistor at RFwith emphasis on the small-signal operation in strong inversionand in saturation. Simple expressions for theparameters arederived that are useful for direct parameter extraction and forcircuit analysis and optimization. Section III discusses the noiseproperties of the MOS at HF and gives simple expressions forthe four noise parameters.

II. MOS TRANSISTORMODELING AT RF

A. MOST Equivalent Circuit at RF

Although it is always possible to have a detailed equivalentcircuit that accounts for all the physical elements that are partof the RF MOS transistor, it is often too complex to be imple-mented as a compact model or a subcircuit for circuit simulationpurposes. Moreover, many of the component values would bedifficult or even impossible to extract and the subcircuit wouldcontain too many internal nodes which would significantly in-crease the simulation time. As is often the case in modeling,a tradeoff has to be found between accuracy and efficiency. Agood compromise is obtained when simplifying the completedetailed equivalent circuit to the one presented in Fig. 1 [21],[25]–[32], which from experience has shown to be sufficient formost RF circuit simulation. In order to implement this equiva-lent circuit in a Spice simulator as a subcircuit (SUBCKT), allthe extrinsic components have been pulled out of the MOS tran-sistor compact model, so that the MOS transistor symbol onlyrepresents the intrinsic part of the device. This allows to haveaccess to internal nodes and model extrinsic components suchas series resistances and overlap capacitances in a different waythan what is available in the compact model.

The source and drain series resistors have been added outsidethe MOS model since the internal series resistances are only“soft” resistances embedded in the expression used to calculatethe drain current to account for the dc voltage drop across the

1One may argue that bias circuits do not need to be simulated at RF, whichis partially true. However, sometimes dc control loops have to be checked forstability and therefore require careful simulation at RF. Even open-loop biascircuits must be simulated at RF to check crosstalk between the circuits it biasesto determine its output impedance, the PSRR at high frequencies, etc.

0018-9200/00$10.00 © 2000 IEEE

ENZ AND CHENG: MOS TRANSISTOR MODELING FOR RF IC DESIGN 187

Fig. 1. MOS transistor equivalent circuit.

source and drain resistances, but they do not add any poles andare therefore invisible for ac simulation. The gate resistanceis usually not part of the MOS compact model, but plays afundamental role in RF circuits and therefore has to be addedto. The substrate resistors , , and have been addedto account for the signal coupling through the substrate. Thiseffect will be discussed in more detail in Section II-E. Thesource-to-bulk and drain-to-bulk diodes are also part of thecompact model but their anodes are connected to the samesubstrate node. The diodes internal to the compact model havetherefore also been turned off and two external diodesand

have been added in order to account for the substrate resis-tance existing between the source and the drain diffusions.Note that the intrinsic substrate node should be connected at

some point along the resistor, but simulations have shownthat connecting the intrinsic substrate to the source or the drainside of have little influence on the parameters. There-fore, the intrinsic substrate has been connected to the sourceside of in order to save one node and one component. InFig. 1(b), two bias-dependent overlap capacitances and

have been added. This is not always required, dependingon the compact model used. For example, BSIM3v3 accountsfor bias-dependent overlap capacitances that, if extractedcorrectly, have shown a sufficient accuracy. Pulling them outallows also one to correct for the inaccuracies of the intrinsiccapacitances appearing for short-channel devices. The circuitof Fig. 1(b) can then easily be implemented in Spice as asubcircuit as shown in Fig. 1(c).


Fig. 2. Quasi-static small-signal circuit of circuit shown in Fig. 1(b) valid insaturation.

B. Small-Signal Circuit in Saturation

The small-signal equivalent circuit of Fig. 1(b) is shown inFig. 2 where it has been assumed that the MOS transistor oper-ates in saturation and in quasi-static regime [21]. The voltage-controlled current sources (VCCS) are defined as

(1)

for substrate-referenced models (such as EKV) or

(2)

for source-referenced models (such as BSIM3v3 or MOS model9) with

(3)

The slope factor2 used in (3) is equal to

(4)

which depends on the gate-to-bulk voltage and typically rangesfrom 1.6 in weak inversion to 1.3 in strong inversion for an

-channel transistor (1.4–1.2 for thechannel) [18], [21].

C. Component Bias Dependence

The capacitances shown in Fig. 2 include both intrinsic andextrinsic parts

(5)

where , and are the intrinsic capaci-tances, , and are the overlap capacitances, and

2The slope factor is related to the slope of thelog (I ) � V characteristicin weak inversion which is equal to1=(nU ) whereU = kT=q [18].

Fig. 3. Normalized intrinsic capacitances and transcapacitances.

and are the junction capacitances. Note that all thesecapacitances (including the overlap capacitances) are bias-de-pendent [21]. The long-channel intrinsic capacitances normal-ized to the total gate oxide capacitance

are plotted versus the gate overdrive voltage inFig. 3(a). is the number of fingers, and are the ef-fective width and length of a single finger, and is the oxidecapacitance per unit area. Capacitance corresponds to thetotal intrinsic gate capacitance .The shape of the intrinsic capacitances versus bias are slightlydifferent for short-channel devices due mainly to polydepletion[21], [53] and short-channel effects [21], [54]. As an example,capacitance may typically look as shown by the dashed linein Fig. 3.

The gate and source transadmittancesand are givenby

(6)

where and are, respectively, the gate and source tran-scapacitances [21]. According to (6), the transcapacitances adda certain phase shift to the drain current variation that partly ac-counts for the propagation delay along the channel. They canbe interpreted as a first-order approximation of the NQS effects[21]. The long-channel transcapacitances are plotted versus the


overdrive voltage in Fig. 3(b). It is interesting to notethat, to first-order, the ratios between the transcapacitances andthe related transconductances are equal

(7)

so the transadmittances can be rewritten as

(8)

It is worth mentioning that any charge-based compact model,such as BSIM3v3, MOS Model 9, or EKV, inherently havetranscapacitances and therefore transadmittances given by (8).Although the phaseof the transadmittances given by (8)areequalto thatofa first-orderNQSmodel, theirmagnitude increases withfrequency instead of decreasing as it would in the first-order (orhigher order) NQS model. This difference has to be accountedfor when implementing an NQS model on top of a charge-basedmodel toavoidwrongmagnitudeandphasecharacteristics.

The overlap capacitances are also bias-dependent due to thelightly-doped source and drain (LDD) regions [55]. The overlapportion of the LDD regions behave similarly to a MOS capacitorof the opposite type than the channel. Therefore, when the tran-sistor is biased in inversion, the overlap LDD regions may be inaccumulation. Even though this bias dependence is accountedfor in the BSIM3v3 compact model, it may be advantageous toinclude it into the separate overlap capacitances appearing in thesubcircuit. By doing this, the capacitances and cannot only account for the bias-dependent overlap capacitancesbut can also correct the intrinsic capacitance bias dependence forshort-channel effects in the case they are not correctly accountedfor.3 Good results for the bias dependence of the overall gate-to-source and gate-to-drain capacitances have been obtained byusing the simple empirical relation as described in [33]–[35].

Note that all the terminal resistances as well as the substrateresistances are also bias-dependent. The bias dependence of thesource and drain resistances is mostly due to the LDD regions.The gate resistance bias dependence results primarily from thedistributed nature of the channel resistance and the oxide capac-itance [21], [32]. The substrate resistances may also be bias-de-pendent due to the variations of the depletion regions below thegate and surrounding the source and drain diffusions. Althoughthey could be implemented in the subcircuit of Fig. 1, good re-sults have been obtained without accounting for the bias depen-dencies of these resistances.

D. -Parameter Analysis

Since the capacitances are all approximately proportional tothe total gate width and since the terminal re-sistances are inversely proportional to , the time constantdue to the terminal resistances depend only on the gate length

, the overlap length , or the diffusion width [31].The latter dimensions are usually taken as minimum to achievethe highest cutoff frequency. Therefore, the poles due to the ter-

3Strictly speaking, capacitancesC andC in this paper should not becalled overlap capacitances since they may account for part of the intrinsic ca-pacitances that are not correctly modeled in the compact intrinsic model.

minal resistances are at a much higher frequency than typicallythe transit frequency, so that they basically can be neglectedwhen calculating the parameters and the related quantities.Neglecting also the substrate resistances in the small-signal cir-cuit of Fig. 2 allows one to derive the following analytical ex-pressions for the parameters:

(9)

where it has also been assumed that . Equation (9)has been verified experimentally in Fig. 4, which shows a com-parison between the measured (after a two-step de-embeddingprocess), the simulated, and the analyticalparameters for an

-channel transistor with , m,m. The simulations have been performed with the complete

quasi-static (QS) model of Fig. 1(b), with the EKV v2.6 compactmodel. Fig. 4 shows that the analytical expressions match themeasurements very well up to 10 GHz except for . Thisdiscrepancy is due to the substrate coupling effect discussed inthe next section. Note that Fig. 4 also shows that there may bea big discrepancy in if the transcapacitance in (9)is neglected.

Note that the simplified parameters given by (9) can beused for a direct extraction of the RF model parameters frommeasurements as presented in [30] and [31]. For example,can be extracted from and from .In the linear region, and ,whereas in saturation, and therefore

. The gate resistance can be extracted as. The extraction of the substrate resis-

tances requires a more complicated procedure described in [30]and [31].

E. Substrate Coupling

At high frequency, the signal at the drain couples to the nearbysource and the bulk terminals through the junction capacitanceand the substrate resistances (cf. Fig. 1). As mentioned aboveand observed in Fig. 4, this coupling mainly affects the outputadmittance . Fig. 5 shows the cross sections of multifingerRF MOS transistors where only the most important substrate re-sistances have been drawn. In order to match the equivalent cir-cuit shown in Fig. 1(b), equivalent capacitances and resistanceshave to be calculated from the individual capacitances and resis-tances shown in Fig. 5. Since all the source (drain) diffusions areconnected together via metal layers (assumed to have negligibleresistances compared to the substrate resistances), the junctioncapacitances and as well as the substrate resistances


Fig. 4. Comparison between the measured, simulated, and analyticalY parameters (n-channel,N = 10,W = 12 �m,L = 0:36 �m, andV = V = 1

V).

, , and are given by

(10)

where and are, respectively, the number of source anddrain diffusions. By symmetry, all the individual source (drain)junction capacitances are equal to that of a single source (drain)diffusion .4 The same is validfor the individual drain-to-source substrate resistances ,leading to

(11)

4Note that, in general,C 6= C due to different source-to-bulk anddrain-to-bulk voltages.

where and are the junction capacitances ofa single source and drain diffusion and is thedrain-to-source substrate sheet resistance which is typically

k . The calculation of the source-to-bulk anddrain-to-bulk substrate resistances needs to distinguish betweeneven and odd numbers of fingers, as shown in Fig. 5(a) and (b).For a transistor with an even number of fingers,and since the outer source diffusions are closerto the bulk than the inner source diffusions and by symmetry

and , resulting in

and

for even. (12)

For a transistor with an odd number of fingers, ,, and which results in

for odd (13)

Asimplescalingrulecanbederivedforbulksubstratesif it isas-sumedthat thereareonlysubstratecontactsoneachsideof thede-vice which are parallel to the ending source or drain junctions, assketched in Fig. 6 (i.e., no substrate contacts surrounding the de-vice). In thiscase, thesubstratecurrentswillonly flowinaperpen-


Fig. 5. Substrate resistances.

diculardirectiontothesourceanddraindiffusionsresultinginsub-strateresistancesinverselyproportional tothefingerwidth

and for even (14)

and

for odd (15)

where and are the source-to-bulk and drain-to-bulk sub-strate resistances per unit length (i.e., transistor width) whichtypically range from 1 to 10 k m (for a bulk technology). Theabove scaling relations might not hold anymore if there are alsosubstrate contacts surrounding the device, since in this casethe substrate currents have a complicated three-dimensionaldistribution within the substrate. Also, note that and arebias-dependent, but this discussion is beyond the scope of thispaper.

A comparison between several substrate resistive networksis presented in [77]. It is claimed that a single substrate resistor,corresponding to the circuit of Fig. 1with , isadequateto accurately model the small-signal parameters up to 10 GHz. Itis important to note that this is true only for devices having a largenumbersoffingers( for thedevicesmeasuredin[77]) forwhich becomesnegligiblewithrespectto and .Also,even for devices with a large number of fingers, it was observedthat the model with a single substrate resistor starts to deviatesignificantly from the measured data for frequencies above 10GHz.

F. Parameters and Measurements

The subcircuit of Fig. 1 has been used to build a scalable RFMOS model using adequate scaling rules [31]. Both BSIM3v3

Fig. 6. RF MOS transistor layout with symmetrical substrate contacts.

and EKV v2.6 have been used for the intrinsic compact model( in the schematic of Fig. 1). The parameters have been ob-tained from the measuredparameters which have been de-em-bedded using a two-step procedure [58]. DC parameters, in-cluding the series resistance parameter , have been ex-tracted from dc measurements [59]. Most parameters specificto the RF part have been extracted using the methodology pre-sented in [30] and [31]. A comparison between measured andsimulated parameters versus frequency is presented in Fig. 7.The simulation has been performed with three different models:1) EKV v2.6 with parameters extracted for that particular device(line); 2) a scalable RF subcircuit with EKV v2.6 (dashed line);and 3) a scalable RF subcircuit with BSIM3v3. Both BSIM3v3and EKV v2.6 show a very good match with measurements in-cluding the output admittance . There are small differencesbetween the scalable models and the model optimized for theparticular device mainly due to the simple scaling rules used forthe substrate resistances. Note that the discrepancies inare not critical since is dominated by its imaginary part cor-responding approximately to . Similar results have beenobtained for other operating points and other device geome-tries using thesame scalable model. The bias dependence hasbeen checked by measuring theparameters at 1 GHz andsweeping the gate voltage. The de-embeddedparameters areplotted versus the inversion factor in Fig. 8, where

is the specific current delimiting the regionsof weak and strong inversion with [18]. The in-version factor is a useful way to characterize the state of in-version of the channel of a MOST in saturation: it is muchlarger than one in strong inversion, close to unity in the mod-erate inversion, and much smaller than one in weak inversion[18]. Note that depends on the transistor geometry ac-cording to [18]. A good match is ob-tained in Fig. 8 for EKV v2.6 except for . The reasonfor this discrepancy is that the model assumes that the gate resis-tance used in the subcircuit of Fig. 1 is only due to the poly-sil-icon gate resistance, which is bias-independent. Actually, part of

includes the effects of the resistance in series with thegate-to-source intrinsic capacitance that models the distributednature of the oxide capacitance and the channel resistance whichis obviously bias-dependent. In the model of Fig. 1,had tobe overestimated in order to fit at a higher frequency


Fig. 7. Comparison between the measured and simulatedY parameters versus frequency (n-channel,N = 10, W = 12 �m,L = 0:36 �m, andV =V = 1 V).

(>2 GHz). This resulted in a value of that is smallerthan the measured one, as can be observed in Fig. 8.

The performance of RF devices are often evaluated bylooking at their transit frequency which can be defined asthe frequency for which the extrapolated small-signal currentgain drops to unity. The measured for two

-channel transistors having different gate lengths are plottedin Fig. 9. The measurements are compared to simulations usingthe subcircuit of Fig. 1 with EKV v2.6 for the compact model.The simulation results agree well with the measured data overa wide bias range. The peaking of is due to the transistorleaving saturation and entering into the triode region. At thispoint, the transconductance starts to saturate or even decreasewhile the gate-to-drain intrinsic capacitance starts to increasemaking the reach a maximum and then sharply decrease.

G. Nonquasi-Static Effects

The quasi-static assumption used for deriving thesmall-signal circuit of Fig. 1 and the associated compo-nents does not hold anymore when the frequency gets closeto the intrinsic cutoff frequency of the device defined as

.5 NQS effects may appear for nonminimumchannel length transistors, particularly for p-channel MOStransistors (PFET’s) which have a smaller mobility and there-fore a smaller than n-channel MOS transistors (NFET’s).Many NQS models have been proposed in the literature takinginto account different effects and with different degrees of

5Note thatf = 1=(2��) is always larger thanf , typicallyf =f �= 5 � � � 6.

approximation [21], [36]–[51]. These models all require one toreplace the intrinsic capacitances and transconductances withhigher order admittances and transadmittances. This imple-mentation is not straightforward in compact models since thepoles and zeros require additional nodes internal to the compactmodel that have to be solved. NQS effects can be modeledat first-order by replacing each intrinsic capacitance by anRC series network. However, this is impossible to do withouthaving access to the compact model implementation. Thisproblem can be circumvented by using a voltage-controlledcurrent source (VCCS) connected in parallel to the compactmodel intrinsic capacitances and transconductances, as shownin Fig. 10(a) and (c). The VCCS can then be synthesized inmany different ways in order to be implemented in Spice. Thisapproach allows one to keep the QS intrinsic compact MOSmodel unchanged. Additional nodes are then added outsidethe QS compact model in order to implement the desiredtransadmittances. An example is shown in Fig. 10(b) and(d). The admittance and transadmittance corresponding to thecircuits of Fig. 10(b) and (d) are given by

(16)

with , , , and. A first-order NQS model would require


Fig. 8. Comparison between the measured and simulatedY parameters versus inversion factorI =I (n-channel,N = 10,W = 12 �m,L = 0:36 �m,andV = V = 1 V).

, , and[21], but the domain of validity of this first-order NQS modelcan be extended beyond the limit of by using the zeroof (16) by setting and . The circuitsof Fig. 10(c) and (d) have been added to the subcircuit ofFig. 1 for the simulation of a -channel MOS transistor witha nonminimum gate length m. The simulationresults are very close to the measuredparameters, as canbe seen from Fig. 11. It should be noticed that these resultshave been obtained with EKV v2.6 with the XQC switch [17]set to select the capacitive model instead of the charge-basedmodel in order to avoid the left-hand-side zero of the intrinsictransadmittance, as discussed earlier.

III. N OISE MODELING AT RF

A. Noise Sources in the MOS Transistor

The different noise sources in the MOS transistor are shownin Fig. 12 together with their power spectral densities (PSD).They include: the noise at the drain , constituted by thechannel thermal noise and the flicker noise

, the terminal resistances thermal noise, , and the substrate resistances thermal noise, and . The flicker noise mainly affects the

low-frequency performance of the device and can be ignoredat high-frequency.6 In addition to the channel thermal noise atthe drain, at HF the local noise sources within the channel are

capacitively coupled to the gate and generate an induced gatenoise [21], [61]–[68].

B. Channel Thermal Noise

Although all the noise sources contribute to the total noiseat HF, the dominant contribution still comes from the channelthermal noise having a PSD given by[18] and [21]

with (17)

where is the Boltzmann constant,isthe absolute temperature in kelvin, is the channel thermalnoise conductance, andis a bias-dependent factor, which forlong-channel devices is equal to unity in the linear region andto in saturation [61]. is related to another factordefined as [61]

(18)

is a good figure of merit to compare the thermal noise per-formance of different transconductors. It shows how much noiseis generated by the device at the input for a given transcon-ductance. As stated by (18), is proportional to and istypically equal to unity in strong inversion. For short-channel

6Flicker noise is nevertheless important for some RF circuits such as mixersor oscillators that up-convert the low-frequency noise around the carrier anddeteriorate the phase noise or the signal-to-noise ratio.


Fig. 9. Transit frequencyf versus bias for two different transistors: (a)fversus the inversion factorI =I and (b)f versus the overdrive voltageV � V .

devices in saturation, might become larger than thelong-channel value due to both velocity satura-tion and hot electrons [61], [70], [73]. This effect had alreadybeen analyzed by van der Ziel twenty years ago [61] and hasbeen verified experimentally by Abidi more than ten years ago[70]. Some models have been proposed to account for the ve-locity saturation effect [71] and hot carrier effects [72], but theyhave not been implemented in any compact model yet. More re-cently, Klein proposed a simple model for the thermal noise thataccounts for both velocity saturation and hot carriers and canbe easily implemented in a compact model [73]. Klein’s noisemodel was originally developed for a transistor biased in satu-ration and in strong inversion, but it can be extended to coverweak to strong inversion by rewriting the noise parameteras

(19)

where is a relaxation time (of the order of 1 ps) used as afitting parameter and [20]

(20)

Fig. 10. NQS admittances and transadmittances implementation: (a)admittance parallel implementation, (b) admittance Spice implementation,(c) transadmittance parallel implementation, and (d) transadmittance Spiceimplementation.

is the normalized ratio with being theinversion factor in saturation [20]. also depends on thebias according to

for (strong inv.)for (weak inv.)

(21)

This simple model assumes that the carrier velocity is satu-rated and that the lateral field is equal to the critical field all


Fig. 11. Y parameters for a NQS model using VCCS shown in Fig. 9.

Fig. 12. Noise sources in the MOS transistor.

along the channel from source to drain. Although these assump-tions are questionable, the resulting model can fit the measureddata over bias and geometry [73].

The noise parameter calculated from (19) is plottedversus the inversion factor in Fig. 13 for a long- and ashort-channel device. For long-channel, the second term in (19)becomes negligible and therefore reduces to .For short-channel, increases in strong inversion to about

six times the long-channel value. This is in good agreementwith the measured data [70] and device simulation data [76].

C. Induced Gate Noise

At HF, the local channel voltage fluctuations due to thermalnoise couple to the gate through the oxide capacitance andcause an induced gate noise current to flow (cf. Fig. 14) [21],[61]–[68]. This noise current can be modeled by a noisy current


Fig. 13. � noise factor computed from(19)for a long- (L = 10 �m) anda short-channel (L = 0:36 �m) device withv = 10 m/s and� = 1 ps.

source connected in parallel to and having a PSDgiven by [64]–[66]

(22)

with

and where is a bias-dependent factor that is equal to 4/3 for along-channel device in saturation and [65], [66].Note that PSD is frequency-dependent.

Since the physical origin of the induced gate noise is thesame as for the channel thermal noise at the drain, the two noisesources and are partially correlated with a correlationfactor [61], [65], [66]

with

long-channel (23)

where is the cross-power spectral density [21]. Devicenoise simulations performed for a finger length mhave shown that the correlation factorremains mainly imagi-nary (real part about 10 times smaller than the imaginary part)and that its value is slightly smaller than the long-channel value0.395 (it typically ranges from 0.35 to 0.3 forfor short-channel devices) [75].

The induced gate noise and, moreover, its correlation to thethermal noise at the drain are not implemented in compactmodels yet (except for MOS Model 9 that includes the inducedgate noise but without the correlation). This is probably not toosevere for frequencies much smaller than the device, sincebesides the thermal noise at the drain, the other most importantcontributor to the total noise are the substrate and the gateresistances.

D. HF Noise Parameters

The noise at HF is characterized by four parameters: the min-imum noise factor [or minimum noise figure

], the input referred noise resistance and theoptimum source admittance for which theminimum noise figure is obtained [68]. The latter are usually theparameters obtained from measurements. They are not very ap-pealing from a circuit designer’s point of view. They prefer touse the parameters related to the noisy two-port equivalent cir-cuit shown in Fig. 15, namely, the PSD of the input noise voltagesource , the PSD of the input noise current source

and the correlation admittance ac-counting for the correlation existing betweenand . Noisesource can also be split into a noise source which is un-correlated to and a noise source that is fully correlatedwith

(24)

where is the correlation factor7 defined as .The rules to transform , , and into , ,

, and are given below:8

(25)

and inversely from , , , and into , , and

(26)

According to (26), the smaller the products andare, the smaller is.

The noise parameters can be calculated analytically using thesimplified small-signal circuit shown in Fig. 16, where it hasbeen assumed that and leading to thedefinition . The capacitances andhave also been neglected. The following noise parameters areobtained:

(27)

7The correlation factorc denoting the correlation existing between noisesourcesi and v should not be confused with the correlation factorcaccounting for the correlation existing between the induced gate noise and thedrain thermal noise.

8Note thatR , G , G , andG are usually frequency-dependent.


Fig. 14. Induced gate noise and equivalent model.

Fig. 15. Noisy two-port and its ABCD-parameter representation.

where is the ratio of the noise PSD of the gate resistanceto the input referred channel noise and

the ratio of the output referred substrate resistance noisePSD to the output referred channel noise

(28)

where has been used. Parametersandaccount for the induced gate noise and its correlation to the drainnoise

(29)

Both variables and reduce to when the inducedgate noise is ignored ( ). As expected by looking at theschematic of Fig. 16, the induced gate noise contributes mainlyto through the factor , the gate resistance contributes to,and the channel noise and substrate noise contribute to bothand . Substrate noise may typically contribute to 20% ofwhereas typically contributes to about 5%. It is thereforeimportant to account for the substrate resistance when doingnoise calculation and noise optimization.

The noise parameters of an-channel device have been mea-sured and carefully de-embedded using the methodology pre-sented in [68], [69], and [74]. The parameters are presented inFig. 17 and are compared to the results obtained from simula-

tion using the complete subcircuit of Fig. 1 with the additionalinduced gate noise source added to the subcircuit (but not ac-counting for the correlation between induced gate noise anddrain thermal noise). Also plotted are the results obtained from(27) including the correlation between induced gate noise andchannel drain noise. The switches used in theanalytical expressions and shown in the legend of Fig. 17 are de-fined as follows: enables the gate resistancenoise, en-ables the substrate resistance noise, enables the inducedgate noise without correlation ( ), and enables the in-duced gate noise correlation ( ). Fig. 17(a) shows thatthe gate and substrate resistances strongly affect the minimumnoise figure , the optimum noise conductance andthe input referred noise resistance. The induced gate noisestrongly affects and , but has no effect on . Itcan also be seen that the effect of the correlation factoron

is negligible. From these results, it can be concluded thatinduced gate noise is not the only contributor to the minimumnoise figure, but the gate and, more importantly, the substrateresistance also contribute significantly.

Note that the analytical expressions for the noise parametersgive reasonable results below and the discrepancies ap-pearing at HF between the analytical and the measured resultsmainly come from a wrong frequency behavior due to the verysimple equivalent circuit used for the derivation of (27).

IV. CONCLUSION

The design of RF CMOS integrated circuits requires MOStransistor models that are accurate up and beyond the gigahertzfrequency range. The compact models currently available do notaccount for some important effects caused by components suchas the gate resistance and the substrate coupling resistances thatstrongly affect the behavior of the MOS transistor at gigahertzfrequencies. All these effects can be accounted for by adding ina subcircuit all the extrinsic components to the existing compactmodel which is then used only as the intrinsic part of the device.The RF MOS transistor subcircuit can be made scalable by care-fully describing the geometry dependence of all the external ex-trinsic components, assuming that the intrinsic compact modelis also scalable. Although all these components show a bias de-pendence, it is generally sufficient to account for the bias de-pendence of the junction and overlap capacitances, leaving theresistances bias-independent. In some case, it might be required


Fig. 16. Simplified small-signal schematic for noise calculation.

Fig. 17. Comparison between measured and simulated noise parameters.


to also account for the bias dependence of the gate resistancewhich is mainly due to the distributed nature of the channel.

Simple expressions for the parameters are derived that givea better insight into the device frequency behavior at HF and alsoallow for a direct extraction of almost all the RF model param-eters. The only effect that this simplified-parameter analysisdoes not capture is the coupling of the signal from the drain tothe source diffusions and to the substrate contacts. This effectmainly affects the output admittance and can be modeledby a simple resistive network. A scalable model for these sub-strate resistances is proposed that gives excellent results for bothn- and p-channels up to 10 GHz. The substrate resistances canbe extracted from measurement according to the procedure de-scribed in [30] and [31]. The subcircuit presented in this paperhas been successfully validated over frequency up to 10 GHz,over geometry and over bias on a 0.25-m CMOS process forboth n- and p-channel devices.

NQS operation may be important to model for devices withnonminimum channel length and particularly for p-channeltransistors. A simple Spice subcircuit NQS implementationexample, using VCCS’s, is described. It shows excellentagreement up to 10 GHz with the parameters measured on ap-channel transistor with 0.76-m gate length.

Finally, the different noise sources in the transistor are ana-lyzed, including the induced gate noise. A new model for thechannel thermal noise of short-channel transistors accountingfor velocity saturation and hot electrons effects is described. Thefour noise parameters of a simplified MOS transistor model in-cluding the induced gate noise, the correlation between the in-duced gate noise and the drain thermal noise, the substrate re-sistance noise, and the gate resistance noise are derived. The an-alytical results as well as the simulation results obtained fromthe complete subcircuit model are favorably compared to mea-surements. This analysis also shows that the contribution of thesubstrate resistances may be significant and should therefore notbe neglected as it is often the case.

For some RF applications in the gigahertz range using futuredeep-submicrometer processes, it may be advantageous to movethe operating point of the RF devices from strong inversion tomoderate inversion to take advantage of the higher ratioand therefore of the higher current efficiency and benefit fromthe lower electrical fields within the transistor. This avoids ve-locity saturation and hot carrier effects, resulting in smaller ex-cess noise factor . It also allows one to take full advantageof the scaling of the transit frequency compared to the

scaling when velocity saturation is present. Finally, mod-erate inversion also better accommodates the more and morestringent low-voltage constraint.

ACKNOWLEDGMENT

The authors would like to thank their colleagues M. Schroter,M. Matloubian, and V. Delatorre for fruitful discussions and D.Pehlke, J. Chen, and L. Tocci for taking excellent measurements.

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Christian C. Enz (M’84) received the M.S. andPh.D. degrees in electrical engineering from theSwiss Federal Institute of Technology, Lausanne(EPFL), in 1984 and 1989, respectively.

From 1984 to 1989, he was a Research Assistantat the EPFL, working in the field of micropoweranalog CMOS integrated circuits (IC) design. In1989, he was one of the founders of Smart SiliconSystems S.A. (S3), where he developed severallow-noise and low-power IC’s, mainly for high-en-ergy physics applications. From 1992 to 1997, he

was an Assistant Professor at EPFL, working in the field of low-power analogCMOS and BiCMOS IC design and device modeling. From 1997 to 1999, hewas Principal Senior Engineer at Conexant (formerly Rockwell SemiconductorSystems), Newport Beach, CA, where he was responsible for the modeling andcharacterization of MOS transistors for the design of RF CMOS circuits. In1999, he joined the Swiss Center for Electronics and Microtechnology (CSEM)where he was heading the RF and Analog IC design group and, recently, waspromoted to Head of the Advanced Microelectronics Department. He is alsoAdjunct Professor at EPFL. His technical interests and expertise are in the fieldof very low-power analog and RF IC design and MOS transistor modeling. Heis the author or co-author of more than 60 scientific papers and has contributedto numerous conference presentations and advanced engineering courses.

Yuhua Cheng (SM’99) received the B.S. degree inelectrical engineering from Shandong PolytechnicUniversity, Jinan, China, in 1982, the M.S. degreein electrical engineering from Tianjin University,Tianjin, China, in 1985, and the Ph.D. degree inelectrical engineering from Tsinghua University,Beijing, China, in 1989.

In 1990, he joined the Institute of Microelectronics(IME), Peking University, China. From 1992 to 1996,he was an Associate Professor in the IME and theDepartment of Computer Science and Technology.

From 1994 to 1995, he was a Visiting Professor at the University of Trond-heim, Norway, and a Research Fellow of the Norwegian Research Council.From 1995 to 1997, he was a Research Scientist at the Department of ElectricalEngineering and Computer Sciences, University of California, Berkeley, wherehe was working on the BSIM3 model development and providing technical sup-port to BSIM3 users from both industry and academics. He was the ProjectCoordinator of the BSIM3v3 model development and was one of the principalcontributors of the BSIM3v3 model which has been chosen as an industry stan-dard model for IC simulation by the Electronics Industry Association/CompactModel Council and given an R&D 100 Award in 1996. In 1997, he worked forseveral months in Cadence Design Systems as a Member of Consultant Staff.Since May 1997, he has been with Conexant Systems (formerly Rockwell Semi-conductor Systems), Newport Beach, CA, as a Senior Staff Engineer, respon-sible for radio frequency (RF) device modeling and parameter extraction forcircuit design. His research interests include high-speed bulk and silicon-on-in-sulator (SOI) CMOS device, modeling and RF IC design. In 1991, he served asthe Chairperson of the Technology CAD session of VLSI Process and DeviceSimulation (VPAD) in Japan and served as a Chairperson in Compact Modeland Circuit Simulation session at the 1998 IEEE International Conference onSolid-State and Integrated Circuit Technology (ICSICT’98) in China. He hasauthored or co-authored more than 40 research papers, including several invitedones, and one bookMOSFET Modeling & BSIM3 User’s Guide.

MOS Transistor Modeling for RF IC Design (Enz)

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