MIT International Journal of Electronics and Communication ... · An Application specific...

MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 1, January 2014, pp. 1–6 1

Application specific full custom design integrated circuit is a methodology for making a logic cell, circuit or layout specifi-cation. Full custom design circuit is the part of Application specific integrated circuit. A gate array or uncommitted logic arrayas an approach to the design and manufacture of application specific integrated circuit. It requires custom chip fabricationusing a complete set of unique masks which define the semiconductor processing of the design. A full custom IC includessome logic cells that are customised using microprocessor full custom IC. In most recent CMOS feature sizes (e.g., 90 nm and45 nm); leakage power dissipation has become an overriding concern for VLSI circuit designers. A goal of this paper is toevaluate the performance of one-bit Hybrid full adder cell, provide the technical community with a basic understanding of thetechnologies and options available in the Integrated Circuits (ICs) that they design and use. Hybrid-CMOS design stylesutilize various CMOS logic style circuit to build new Full Adder with desired performance.Keywords: Power consumption, ASIC, full custom circuit CMOS CAD tool, and Programmable gate array.

Design of CMOS Full Adder ApplicationSpecific Integrated Circuit

ABSTRACT

I. INTRODUCTIONAn integrated circuit (IC) customized for a particular use, ratherthan intended for general-purpose use. For example, a chip de-signed solely to run a cell phone is an ASIC. Full-custom ICdesign is limited to ICs that are to be fabricated in extremelyhigh volumes. “Application Specific Integrated Circuits”(ASICs) are changing the way electronic systems are designed,manufactured, and marketed. Thus, it is important in this com-petitive environment to understand the nature, options, designstyles, and costs of ASIC technology and of the related pro-grammable logic IC families. ASIC chips are not generally justapplication specific, they are customer specific. It can be ar-gued that customer programmable logic devices are the onlytrue ASICs. To compound this problem, the term is used differ-ently by different people in different contexts. ASIC is definedvariously as gate array, any custom, semi-custom, or program-mable technology, and as a design methodology [1].

An Application specific integrated circuit is a kind of inte-grated circuit that is specially built for a specific application orpurpose, an ASIC can improve speed because it is specially de-signed to do one thing and it does this one thing well. It can alsobe made smaller and use less electricity. The disadvantage ofthis circuit is that it can be more expensive to design and manu-facture, particularly if only a few units are needed.

An ASIC can be found in almost any electronic device andits uses can range from custom rendering of image to soundconversion. Because ASICs are all custom made and thus onlyavailable to the company that designed them, they are consid-ered to be proprietary technology. In full custom design, customlogic cells are designed, starting at the lowest level (i.e., transis-tor-based cell design) and extending to higher levels (e.g., com-binations of cells for higher level functions) to create the over-all IC function.

A full custom IC are the most expensive to manufactureand to design. The manufacturing lead time is typically eightweek for a full custom IC. One of the exciting ASIC areas un-dergoing rapid development is the addition of analog integratedcircuits to the standard digital VLSI ASIC, corresponding tomixed-signal VLSI. Mixed-signal ICs allow the IC to interactdirectly with the real physical world. Library cells representingvarious analog circuit functions supplement the usual digitalcircuit cells of the library, allowing the ASIC designer to addneeded analog circuits within the same general framework asthe addition of digital circuit cells. Automotive electronics is arepresentative example, with many sensors providing analoginformation which is converted into a digital format and ana-lyzed using microcomputers or other digital circuits. Mixed-sig-nal library cells include A/D and D/A converters, comparators,

Neha RaniDepartment of E & C

Assistant Professor, MITMoradabad, U.P., [email protected]

Alpana SinghDepartment of E & C

Assistant Professor, MITMoradabad, U.P., INDIA

[email protected]

Ritika TandonDepartment of E & C


[email protected]

Priyanka SaxenaDepartment of E & C


[email protected]

ISSN 2230-7672 © MIT Publications


analog switches; sample-and-hold circuits, etc., while analoglibrary cells include op amps, precision voltage sources, andphase-locked loops. As such mixed-signal VLSI ASICs evolve,EDA/CAD tools will also evolve to address the performanceand design issues related to analog circuits and their behaviourin a digital circuit environment. In addition, analog high-leveldescription languages (AHDLs) are being developed to supporthigh level specifications of mixed-signal circuits [2].

II. TYPES OF ASIC DESIGNASIC describes a methodology (or group of methodolo-

gies) for designing electronic systems, and it describes a tech-nology (or group of technologies) used to build electronic sys-tems. Most of today’s flexible and cost effective electronic sys-tems are designed using ASIC methodologies and built usingASIC technology.

ICs are made on a thin (a few hundred microns thick), cir-cular silicon wafer, with each wafer holding hundred of die.The transistor and wiring are made from many layers (usuallybetween 10 and 15 distinct layers) built on top of one another.Each successive mask layer has a pattern that is defined using amask similar to a glass photographic slide. The first half-dozenor so layers define the metal wires between the transistors.

ASIC design can be classified as:Application Specific ICs

Full Custom Semicustom Silicon

Standard Cell

Gate Array FPL

(i) Full Custom DesignIn the classic full custom design style, each primitive logic func-tion or transistor is manually designed and optimized. This re-sults in the most compact chip design with the highest possiblespeed and lowest power dissipation. However, the initial invest-ment or Non-Recurring Engineering (NRE) cost is highest com-pared to all other design styles.

Fig. 1. Full custom layout circuit using CAD Tool

Full-custom ASIC cannot be modified to suit different applica-tions, and is generally produced as a single, specific product fora particular application only. The designer must manipulate theindividual geometric shapes which represent the features of eachtransistor on the chip; hence the often applied term for full cus-tom design: “polygon pushing”. A relatively simple 3000 gatedesign might require the handling of 300,000 rectangles perchip.1 although this design style was used exclusively in earlyICs; engineers rarely use it for today’s ASICs due to the highengineering costs and low designer productivity. Productivityfor full custom logic designs is typically only 6 to 17 transistorsper day. The exception is in high volume commodity productssuch as memories which must be hand-crafted to meet densityand performance requirements [4]. In addition, at least portionsof high-end products such as microprocessors are full customdesigned for performance reasons. Worldwide sales of full cus-tom ASIC designs are predicted to grow only slightly from thecurrent level of $2.7 Billion to $2.9 Billion in 1998 (a decliningmarket share from 23% to 16%).

(ii) Semi-custom DesignSemi custom design is realised solely with standard integratedcircuits may be inappropriate for an application due to cost, size,power consumption, complexity, maintainability, or speed. Forexample the gate array, a chip which contains several identicalcells of uncommitted transistors and resistors. These may beconnected in different ways to perform assorted logical function.This provides the benefits of integrating entire printed circuitboard assemblies onto a single chip, while sharing the time andcosts of mask and wafer development and circuit characterisationamong several small to moderate volume users. Semicustomcustom design circuit can be further divided in to:

Standard Cell DesignIn the standard cell design methodology, pre-defined logic andfunction blocks are made available to the designer in a celllibrary.

Fig. 2. Designing of gate array and standard cells

Typical libraries begin with gate level primitives such as AND,OR, NAND, NOR, XOR, Inverters, flip-flops, registers, and thelike. Libraries generally include more complex functions suchas adders, multiplexers, decoders, ALUs, shifters, and memory(RAM, ROM, FIFOs, etc.). In some cases, the standard cell



library may include complex functions such as multipliers,dividers, microcontrollers, microprocessors, and microprocessorsupport functions (parallel port, serial port, DMA controller,event timers, real-time clock, etc.). Standard cell designs arecreated using schematic capture tools or via synthesis from aHardware Description Language (HDL). Automated tools arethen used to place the cells on a chip image and wire themtogether. Standard cell layouts are easily identified by rows ofequal height cells separated by wiring channels. Large macro-cells such as multipliers or microcontrollers may span multiplecell rows and block some of the wiring channels [5].

Standard cell designs operate a lower clock rates and aregenerally less area efficient than a full custom design due to thefixed cell size constraints and requirements for dedicated wir-ing channels. It is basic building blocks have been custom de-signed and are available in a library of parts. Designer takesthese blocks and connects them together to make a circuit withthe required function. More expensive than GAs because eachdesign will use a different configuration of standard cells re-quiring thus a full mask set.

Gate Arrays (GAs)A Gate Array is a standard LSI chip that consists of gates andthe designer has to do the interconnections between them tocustomise the chip. Full custom and standard cell design meth-odologies require custom chip fabrication using a complete setof unique masks which define the semiconductor processing ofthe design. The gate array technology [3] is based on partiallyprefabricated (up to but not including the final metallizationlayer) wafers with simple gate cells. Such non-customized wa-fers are stockpiled and the ASIC designer specifies the finalmetallization layer added to customize the gate array.

Fig. 3. Cell of gate array and sea-of-gate

* GAs is available in ECL, CMOS and bipolar technologies.* GAs is available in a variety of gate counts from a few hundred

up to 40000.* Designer needs to know nothing about the transistor and circuit

level.

Field Programmable LogicA field programmable logic device is a chip whose final logicstructure is directly configured by the end user. By eliminatingthe need to cycle through an integrated circuit production facility,

both time to market and financial risk can be substantiallyreduced. The Field Programmable Gate Array (FPGA), like thegate array, places fixed cells on the wafer and the FPGA designerconstructs more complex functions from these cells. However,the cells provided on the FPGA can be substantially morecomplex than the simple gates provided on the gate array. Inaddition, the term field programmable” highlights thecustomizing of the ASIC by the user, rather than by the foundrymanufacturing the FPGA. The mask-programmable gate array(MPGA) is similar to the FPGA (using more complex cells thanthe gate array) but the programming is performed by addition ofthe metal layer by the FPGA manufacturer [6]. FPGAs and PLDsare similar, except that the FPGA is usually larger and morecomplex than the PLD. In fact, some companies that manufactureprogrammable ASICs call their products FPGAs, while somecall them complex PLDs (CPLDs).

Fig. 4. Programmable ICs

The Two major classes of field programmable logic, Program-mable Logic Devices (PLDs) and Field Programmable GateArrays (FPGAs), have emerged as cost effective ASIC solutionsbecause they provide low-cost prototypes with nearly instant“manufacturing”. This class of device consists of an array ofuncommitted logic elements whose interconnect structure and/or logic structure can be personalized on-site according to theuser’s specification. Although field programmable logic repre-sents only a small percentage of total ASIC market sales, statis-tics indicate that approximately one half of all chip designprojects today are begun using FPGAs.

(iii) Silicon CompilationSilicon compilation takes place in three major steps:• It Convert a hardware-description language such as Verilog

or VHDL or FPGA into logic (typically in the form of a“net list”).

• Place equivalent logic gates on the IC. Silicon compilerstypically use standard-cell libraries so that they do not haveto worry about the actual integrated-circuit layout and canfocus on the placement.

• Routing the standard cells together to form the desired logic.



III. ASIC DESIGN FLOWASIC Design is based on a flow that uses HDL as the entry levelfor design, which applies for both Verilog and VHDL [8]. Thefollowing description describes the flow from specification ofdesign up to tapeout, which is the form sent to silicon foundryfor fabrication.

Fig, 5. Block Diagram of ASIC Design Flow

The steps are listed below with brief description:(a) Specification: This is the beginning and most important

step towards designing a chip as the features andfunctionalities of the chip are defined. Both design at macroand micro level are taken into consideration which is de-rived from the required features and functionalities. Speed,size, power consumption are among the considerations onwhich the accepted range of values is specified. Other per-formance criteria are also set at this point and deliberatedon its viability; some form of simulation might be possibleto check on this.

(b) RTL Coding: The micro architecture at specification levelis then transformed in RTL code which marks the begin-ning of the real design phase towards realising a chip. As areal chip is expected, so the code has to be a synthesizableRTL code.

(c) Simulation and Test bench: RTL code and test bench aresimulated using HDL simulators to check on the function-ality of the design. If Verilog is the language used a Verilogsimulator is required while VHDL simulator for a VHDLcode. Some of the tools available at CEDEC include:Cadence’s Verilog XL, Synopsys’s VCS, and MentorGraphic’s Modelsim. If the simulation results do not agreewith the intended function expected, the test bench file orthe RTL code could be the cause. The process of debuggingthe design has to be done if the RTL code is the source oferror. The simulation has to be repeated once either one ofthe two causes, or both, have been corrected. There could

be a possibility of the loop in this process, until the RTLcode correctly describes the required logical behaviour ofthe design.

(d) Synthesis: This process is conducted on the RTL code. Thisis the process whereby the RTL code is converted into logicgates. The logic gate produced is the functional equivalentof the RTL code as intended in the design. The synthesisprocess however requires two input files: firstly, the “stan-dard cell technology files” and secondly the “constraintsfile”. A synthesised database of the design is created in thesystem.

(e) Pre-Layout Timing Analysis: When synthesis is com-pleted, the synthesized database along with timing infor-mation from the synthesis process is used to perform a StaticTiming Analysis (STA). Tweaking (making small changes)has to be done to correct any timing issues.

(f) APR: This is the Automatic Place and Route processwhereby the layout is being produced. In this process, thesynthesized database together with timing information fromsynthesis is used to place the logic gates. Most designs havecritical paths whose timings required them to be routed first.The process of placement and routing normally has somedegree of flexibility.

(g) Back Annotation: This is the process where extractionsfor RC parasitic are made from the layout. The path delayis calculated from these RC parasitic. Long routing linescan significantly increase the interconnect delay for a pathand for sub-micron design parasitic cause significant in-crease in delay. Back annotation is the step that bridges syn-thesis and physical layout.

(h) Post-Layout: Timing Analysis: This step in ASIC flow al-lows real timing violations such as hold and setup to bedetected. In this step, the net interconnect delay informa-tion is fed into the timing analysis and any setup violationshould be fixed by optimizing the paths that fail while holdviolation is fixed by introducing buffers to the path to in-crease the delay. The process between APR, back annota-tion and post-layout timing analysis go back and forth untilthe design is cleared of any violation. Then it will be readyfor logic verification.

(i) Logic Verification: This step acts as the final check to en-sure the design is correct functionally after additional tim-ing information from layout. Changes have to be made onthe RTL code or the post-layout synthesis to correct the logicverification.

(j) Tapeout: When the design passed the logic verificationcheck, it is now ready for fabrication. The tapeout design isin the form of GDSII file, which will be accepted by thefoundry.

IV. FULL ADDER SCHEMATIC AND SIMULATION OFCIRCUIT

The Full-adder is one of the most used basic circuits since addi-tion of binary numbers are one of the most used operations in



digital electronics. Full-adders exist everywhere in electronicsystems and a large amount of research has been done in thisarea in order to achieve best possible performance. The ultimategoal of a binary full-adder (BFA) is to implement the followingtruth table for each bit:

Table 1. Truth Table for 1bit adder Slice

Cin A B Sum Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

Logically Ck+1 = AkBk + Ck( Ak + Bk) (1)Sum = Ak Bk Ck (2)

Where k is an integer 0 to n for an n-bit adder. Generally, addersof n-bits are created by chaining together n of these 1-bit adderslices.There are three major components of power dissipation in CMOSCircuits [5].(a) Switching power: power consumed by circuit node capaci-

tance during transistor switching.(b) Short-circuit power: power consumed due to current flow-

ing from Vdd to Gnd when both transistors are ON.(c) Static power: Due to Leakage and static currents.

The simulations have been performed in Cadence with theSpectre simulator in a 120 nm CMOS process technology andthe used transistors are of low-leakage type. The transistors us-ing minimum gate lengths, 120 nm (effective), and a width of150 nm for NMOS and a width of 380 nm for the PMOS. Thethreshold voltage, Vth, for these low-leakage transistors are 383mV for NMOS and -368 mV for PMOS according to the simu-lations [9].

Fig 6. Schematic of floating gate Full Adder Circuit

Fig. 7. EDP for Floating-gate and CMOS full-adders at 150 mV.

The plots show the limit of how large the floating-gatevoltage can be while the circuit’s gain is higher than one. If thefloating-gate voltage, VFGp, is set more negative than in theseplots, there will be an attenuation of the signal for each gate.Figure 7 shows the PDP (at 150 mV) which is almost constantfor all applied different floating-gate voltages and isapproximately 4 times worse than PDP for each of the CMOSfull-adders [10].

IV. CONCLUSIONA full custom IC includes some logic cells that are customisedusing microprocessor full custom IC. VLSI is an IC manufac-turing technology, and VHDL and Verilog are the hardware de-scription languages (programming languages) used to describedigital circuits. This Full adder has better noise immunity ascompared to the standard adder such as static CMOS, making itsuitable for deep-sub micrometer operation. We recommend theuse of hybrid-CMOS design style for the design of high-perfor-mance circuits. The characteristics of the proposed full addersare compared against previous designed full adders based onthe worst case delay time, power consumption and power delayproduct.

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