MICROWAVE AND RF Case Study: Amp5 Design of a WiMAX … · CA CB CC BONDWIRES BONDWIRES SOURCE ......
Transcript of MICROWAVE AND RF Case Study: Amp5 Design of a WiMAX … · CA CB CC BONDWIRES BONDWIRES SOURCE ......
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Case Study:Amp5Design of a WiMAX Power AmplifierPresented by Michael Steer
Reading:Chapter 19, Section 19.6 Based on material in Microwave and RF
Design: A Systems Approach, 2nd Edition, by Michael Steer. SciTech Publishing,
2013.Presentation copyright Michael Steer
MICROWAVE AND RF DESIGN
Index: CS_Amp5
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Design of a WiMAX Power Amplifier
Slides copyright 2013 M. Steer.
3.4 to 3.8 GHz Power Amplifier
Output power at 1 dB gain compression is 28 dBm
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WiMAX power amplifier
● Necessary to use nonlinear simulation, harmonic balance analysis preferred.
● Thermal heat-sinking is very important.● Must consider possible layout at the beginning.● Must have a topology in mind.● Specifications:
– 28 dBm output power– 3.4 to 3.8 GHz
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Z = 50 0
PORT 1
InputMatchingNetwork
Z = 50 0
PORT 2
MatchingNetwork
Output
_
M 1 M 2
Input
Gate bias
1 2
Transistor
50 V
100 mA
Output
21
1.115 V
119 A
Drain bias
Amplifier
RF RF
Amplifier topology● High level topology:
● LinearClass ABamplifierloadline:
VDS
ID DC loadline
AC loadline
Quiescent point4
(Final bias voltages are shown)
3.4 to 3.8 GHz
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Transistor selection
GATE
DRAIN
SOURCE
DIE
DIE
DIE
CACB
CC
BONDWIRES
BONDWIRES
SOURCE
BONDWIRES
2.1 GHz silicon LDMOS transistor.
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Bias concept
VDS
I D(m
A)
VGS
1008060402000
300
600
700
500
400
200
100
(V)
0 V
-0.5 V
-1 V
-1.5 V
6Quiescent DC power = 5 W.
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S11 and S22
11S
22S
(dB
)S
3.51.50.5 2.5 4.5 5.5
0
-5
-10
-15
-20
3.4 to 3.8 GHz operating frequency
Output33 // 4.4 pF2.5 –j11
Input almost 50 (with small parallel capacitance) 7
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S21 and S123.4 to 3.8 GHz operating frequency
S21
S12
(dB
)S
-40
-20
0
20
40
1.50.5 2.5 3.5 4.5 5.5Frequency (GHz)
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Design concept
INPUT
OUTPUT
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Amplifier Layout
10Presentation copyright Michael SteerIndex: CS_Amp5B
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Layout
OUTPUTINPUT
11
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Input matching network
TRANSISTOR GATERF INPUT
GND
GND
DC BLOCK
CAPACITORS
500 RESISTOR
LINE WITH HIGH Z0
GATE BIAS
50 LINE
12
GND
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Output matching network
TRANSISTOR DRAIN RF OUTPUT
GND
GND
DC BLOCK
CAPACITORS
LINE WITH HIGH Z0
DRAIN BIAS
50 LINE
(2.5 –j11
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Input matching network
MTEEID=TL3
MSTEPID=TL25W1=1 mmW2=1.88 mm
MLINID=TL2W=1.88 mmL=3.55 mm
MLINID=TL1W=1.88 mmL=8 mm
MLINID=TL8W=1.88 mmL=2.8 mm
CAPID=C2C=5.6 pF
500
PORTP=2Z=50 Ohm
MSUBEr=3.38H=0.8128 mmT=0.03556 mmRho=1.0Tand=0.002ErNom=3.38Name=SUB1
MLINID=TL23W=1.156 mmL=0.8 mm
MSTEPID=TL24W1=1.156 mmW2=0.254 mm
MLINID=TL6W=0.254 mmL=12.8 mm
MTEEID=TL12
MTEEID=TL5
MTEEID=TL9
MLINID=TL4W=1.2 mmL=1 mm
VIAID=V1D=0.635 mmH=0.813 mmD=0.0356 mm
VIAID=V2D=0.635 mmH=0.813 mmD=0.0356 mm
MLINID=TL13W=1.2 mmL=1 mm
CAPID=C4C=10 nF
VIAID=V3D=0.635 mmH=0.813 mmD=0.0356 mm
MLINID=TL21W=1.2 mmL=1.5 mm
MLINID=TL10W=1.2 mmL=1 mm
MLINID=TL20W=1.2 mmL=1.5 mm
MLINID=TL17W=0.254 mmL=0.99 mm
MLINID=TL14W=1.6 mmL=1 mm
MTEEID=TL15
MLINID=TL22W=1.6 mmL=1.5 mm
VIAID=V4D=0.635 mmH=0.813 mmD=0.0356 mm
MLINID=TL18W=3 mmL=5 mm
MLINID=TL16W=0.254 mmL=1 mm
MLINID=TL11W=0.254 mmL=1 mm
MLINID=TL7W=0.254 mmL=1 mm
PORTP=1Z=50 Ohm
MLINID=TL19W=1.2 mmL=1.5 mm
CAPID=C3C=5.6 pF
CAP
C=1 nFID=C1
CAPID=C6C=1 uF
1.115 VGate DC bias voltage
RF input Active device
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MTEEID=TL3
MSTEPID=TL25W1=1 mmW2=1.88 mm
MLINID=TL2W=1.88 mmL=3.55 mm
MLINID=TL1W=1.88 mmL=8 mm
MLINID=TL8W=1.88 mmL=2.8 mm
CAPID=C2C=5.6 pF
500
PORTP=2Z=50 Ohm
MSUBEr=3.38H=0.8128 mmT=0.03556 mmRho=1.0Tand=0.002ErNom=3.38Name=SUB1
MLINID=TL23W=1.156 mmL=0.8 mm
PORTP=1Z=50 Ohm
1.115 VGate DC bias voltage
RF input Active device
Input matching network (RF Path)
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Input matching network (detail)
MTEEID=TL3
MSTEPID=TL25W1=1 mmW2=1.88 mm
MLINID=TL2W=1.88 mmL=3.55 mm
MLINID=TL1W=1.88 mmL=8 mm
MLINID=TL8W=1.88 mmL=2.8 mm
CAPID=C2C=5.6 pF
500
PORTP=2Z=50 Ohm
MSUBEr=3.38H=0.8128 mmT=0.03556 mmRho=1.0Tand=0.002ErNom=3.38Name=SUB1
MLINID=TL23W=1.156 mmL=0.8 mm
MSTEPID=TL24W1=1.156 mmW2=0.254 mm
MLINID=TL6W=0.254 mmL=12.8 mm
MTEEID=TL5
MLINID=TL4W=1.2 mmL=1 mm
VIAID=V1D=0.635 mmH=0.813 mmD=0.0356 mm
PORTP=1Z=50 Ohm
MLINID=TL19W=1.2 mmL=1.5 mm
CAPID=C3C=5.6 pF
RF input Active device
REST OF BIAS CIRCUIT 16
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Input matching network
MTEEID=TL3
MSTEPID=TL25W1=1 mmW2=1.88 mm
MLINID=TL2W=1.88 mmL=3.55 mm
MLINID=TL1W=1.88 mmL=8 mm
MLINID=TL8W=1.88 mmL=2.8 mm
CAPID=C2C=5.6 pF
500
PORTP=2Z=50 Ohm
MSUBEr=3.38H=0.8128 mmT=0.03556 mmRho=1.0Tand=0.002ErNom=3.38Name=SUB1
MLINID=TL23W=1.156 mmL=0.8 mm
MSTEPID=TL24W1=1.156 mmW2=0.254 mm
MLINID=TL6W=0.254 mmL=12.8 mm
MTEEID=TL12
MTEEID=TL5
MTEEID=TL9
MLINID=TL4W=1.2 mmL=1 mm
VIAID=V1D=0.635 mmH=0.813 mmD=0.0356 mm
VIAID=V2D=0.635 mmH=0.813 mmD=0.0356 mm
MLINID=TL13W=1.2 mmL=1 mm
CAPID=C4C=10 nF
VIAID=V3D=0.635 mmH=0.813 mmD=0.0356 mm
MLINID=TL21W=1.2 mmL=1.5 mm
MLINID=TL10W=1.2 mmL=1 mm
MLINID=TL20W=1.2 mmL=1.5 mm
MLINID=TL17W=0.254 mmL=0.99 mm
MLINID=TL14W=1.6 mmL=1 mm
MTEEID=TL15
MLINID=TL22W=1.6 mmL=1.5 mm
VIAID=V4D=0.635 mmH=0.813 mmD=0.0356 mm
MLINID=TL18W=3 mmL=5 mm
MLINID=TL16W=0.254 mmL=1 mm
MLINID=TL11W=0.254 mmL=1 mm
MLINID=TL7W=0.254 mmL=1 mm
PORTP=1Z=50 Ohm
MLINID=TL19W=1.2 mmL=1.5 mm
CAPID=C3C=5.6 pF
CAP
C=1 nFID=C1
CAPID=C6C=1 uF
1.115 VGate DC bias voltage
RF input Active device
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MTEEID=TL10
MTEEID=TL18
MTEEID=TL16
MTEEID=TL17
MTEEID=TL6
PORTP=1Z=50 Ohm
MLINID=TL1W=10 mmL=5 mm
MLINID=TL3W=3 mmL=5.7 mm
CAPID=C3C=5.6 pF
MSTEPID=TL9W1=10 mmW2=3 mm
PORTP=2Z=50 Ohm
MLINID=TL12W=1.88 mmL=2.88 mm
MLINID=TL23W=1.2 mmL=1.5 mm
CAPID=C1C=0.500 pF
VIAID=V1D=0.635 mmH=0.813 mmD=0.0356 mm
VIAID=V2D=0.635 mmH=0.813 mmD=0.0356 mm
CAPID=C2C=10 nF
MLINID=TL13W=1.2 mmL=1 mm
MLINID=TL24W=1.2 mmL=1.5 m
MLINID=TL15W=1.6 mmL=1 mm
MLINID=TL26W=1.6 mmL=1.5 mm
CAPID=C6C=1 uF
VIAID=V4D=0.635 mmH=0.813 mmD=0.0356 mm
VIAID=V3D=0.635 mmH=0.813 mmD=0.0356 mm
CAPID=C4C=100 nF
MLINID=TL14W=1.2 mmL=1 mm
MLINID=TL22W=3 mmL=6.6 mm
MLINID=TL5W=1.2 mmL=1 mm
MLINID=TL25W=1.2 mmL=1.5 mm
MSUBEr=3.38H=0.8128 mmT=0.03556 mmRho=1.0Tand=0.002ErNom=3.38Name=SUB1
MLINID=TL7W=0.508 mmL=1 mm
MLINID=TL8W=0.508 mmL=13.4 mm
MLINID=TL19W=0.508 mmL=1 mm
MLINID=TL20W=0.508 mmL=1 mm
MLINID=TL21W=0.508 mmL=1 mm
MLINID=TL2W=10 mmL=8.85 mm
MSTEPID=TL4W1=1 mmW2=10 mm
Drain DC bias voltage 50 V
RF OutputActive device
Output matching network
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Amplifier Design
19Presentation copyright Michael SteerIndex: CS_Amp5C
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Z = 50 0
PORT 1
InputMatchingNetwork
Z = 50 0
PORT 2
MatchingNetwork
Output
_
M 1 M 2
Input
Gate bias
1 2
Transistor
50 V
100 mA
Output
21
1.115 V
119 A
Drain bias
Amplifier
RF RF
Amplifier topology● Final bias voltages are shown.
● LinearClass ABamplifierloadline:
VDS
ID DC loadline
AC loadline
Quiescent point20
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Poweramplfiier
Signalsource Automated
tunerActivedevice
Impedancetransformer Automated
tuner
Spectrumanalyzer
Highpowerattenuator
Powersensor
PowermeterPower
sensor
Powermeter
controllerInstrument
Load‐pull system
21
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Load‐pull points
22
Poweramplfiier
Signalsource Automated
tuner
Z in
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• At 3.5 GHz showing the reflection coefficient (here S11) looking into the output matching network and the contours of constant output power.
• POUT,MAX = 42.6 dBm. • Output power for the first
contour surrounding POUT,MAX is 42.5 dBm and the powers of the contours reduce in 0.5 dBmsteps.
• S11 of the final output matching network design is shown from 3.4 to 3.8 GHz
S11
Output POUT,MAX
Output load‐pull contour of POUT
23
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POUT
50
40
30
20
10
013 33233
Gain
Gai
n (d
B)
or O
utpu
t pow
er (
dBm
)
Input power (dBm)
Output power and gain at 3.5 GHz
24
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POUT
Drain efficiency
Gain
0
50%
40%
30%
20%
10%
Dra
in e
ffici
ency
0
10
20
30
40
50
10 20 25 30 32Input power (dBm)
15
Gai
n(d
B) a
nd O
utpu
t pow
er (
dBm
)
Output power, gain, and drain efficiency at 3.4, 3.5, 3.6, 3.7, and 3.8 GHz
25
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Tones at 3.500 GHz and 3.501 GHz each 23 dBm.
34.2 dBm
-10.5 dBm-6.89 dBm
11.5 dBm10.8 dBm
-21.0 dBm
34.2 dBmf1
f5f7
f2
f3 f4
f6
40
30
20
10
0
-10
-20
-30
-40
-503.496 3.497 3.498 3.499 3.5 3.501 3.502 3.503 3.504 3.505
Pow
er (
dBm
)
Frequency (GHz)3.495
Two‐tone input f1 and f2
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Input tones are at 3.500 GHz and 3.501 GHzFundamental plotted is at 3.501 GHz.
-60
-40
-20
0
20
40O
utpu
t pow
er (
dBm
)
0 5 1510 20 25Input power (dBm)
IM3
Fundamental
3:1
1:1
Response to a two‐tone input signal
U
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Summary● Transistor vendors strive to offer transistors for
high volume applications that simplify design effort.
● A few standard topologies are used.● For high power amplifier design harmonic
balance analysis is used.– High dynamic range is not available with transient
simulators.
● Load pull analysis used in simulation and also when adjusting final amplifier design.
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