Microprocessors HC v12

8/12/2019 Microprocessors HC v12

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Horia Cucu

Speech & Dialogue Research Laboratory Faculty of Electronics, Telecommunications and Information Technology

University POLITEHNICA of Bucharest


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Introduction to Microprocessors

Historical Background

Microprocessors Evolution Tree

Typical Applications

Educational Need

Administrative Issues

22.05.2014 2Microprocessors Architecture


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Historical Background

1947: Invention of the transistor

1959: Invention of the integrated circuit (IC)

1965: Birth of Moore's Law

1971: Development of the first microprocessor

1976: Introduction of the first microcontroller



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Microprocessors andMicrocontrollers


is a CPU-on-a-chip

is a computer-on-a-chip


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Microprocessors Evolution Tree


others

Itanium

RISC

Pentium

80486

80386

80286

8086

8085

8080

8008

4004

80488051 DSPs

Comm processorsothers others

General Purpose

MicroprocessorsMicrocontrollers

Special Purpose

Microprocessors

PIC

AVR


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General purpose microprocessors: used to create computersPCs, Laptops, WorkstationsServers, Super-computers (32-bit/64-bit powerful computers)

Special purpose microprocessorsDigital Signal Processing (DSP) processors

Multimedia applications

Communication processorsNetworking equipment (switches, routers, etc.)



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Microcontrollers: used to implement embedded systemsconsumer electronics (toys, cameras, robots)consumer products (washing machines, microwave ovens, etc.)

instrumentation (oscilloscopes, medical equipment)process control (data acquisition and control)communication (telephone sets, answering machine, etc.)office appliances (fax machines, printers, etc.)

multimedia (smart-phones, PDAs, tablets, teleconferencingequipment)automotive industry (onboard computers)



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The Educational Need - a Big Question


others

Itanium

RISC

Pentium

80486

80386

80286

8086

8085

8080

8008

4004

80488051 DSPs

Comm processorsothers others

General Purpose

MicroprocessorsMicrocontrollers

Special Purpose

Microprocessors

AVR

PIC


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Microprocessors Course Outline

1. The Structure of a Microcomputer

2. Overview of a CISC, General Purpose Microprocessor Core

3. The x86 Architecture

4. RISC Architectures

5. Input/Output Strategies



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Administrative Issues

Laboratory Objective: highlight the architectural attributes for the x86MicroprocessorsSessions: 5 teaching labs + one evaluation session

Bibliography C. Burileanu, Microprocesoarele x86 o abordare software, Grupul

pentru microinformatic, Cluj -Napoca, 1999

Communication through the Moodle framework (Arhitectura

Microprocesoarelor - H. Cucu, Password: Microprocesor)Lecture slides (contain only a brief summary)Laboratory documentationEvaluation results



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Evaluation


Evaluare

Evaluarea activit ii pe parcurs (pentru care studentul primete o not : N laborator )este compus din 2 teste obligatorii i o evaluare final opional.

o Nici-o component a evalu rii activitii pe parcurs nu se reface.

o Notarea: Cele 2 teste n timpul edinelor de laborator sunt evaluate cu

note (0 10) . dac media celor 2 note < 5 : studentul va reface complet aceast

disciplin n anul urmtor. dac media celor 2 note >= 5 : studentul poate opta pentru:

prezentarea la evaluarea f inal ; n a cest caz: Nlaborator = 5 10 ; prezentarea direct la examen; n acest caz: Nlaborator = 5 .

Examen final n sesiunea de var: o Examen oral .o Studentul p rimete o not: Nexamen = 0 10 .o Se poate reface n septembrie .

Media final: M = (N laborator + N examen ) / 2

calculat prin trunchiere pentru4 =< M < 5

i prin rotunjire pentru celelaltevalori.


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Evaluation



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Definitions


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Block Diagram of a Microcomputer


A microcomputer is a general purpose device that can be programmedto carry out a set of arithmetic and/or logical operations.


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Functional Components

CPU: the hardware block which processes data andcontrols the system

Memory: the hardware block which stores data in asequence of memory locations

I/O devices: hardware blocks that form the interface

between the microcomputer and the external world

Busses: the connections between the above blocks



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The von Neumann Principles

Both data and instructions are stored in the memory

The contents of the memory is accessed by location

The microprocessor is the CPU of the microcomputer; its role isto process data and control the system

The instructions are fetched from the memory and executedsequentially by the CPU

I/O ports are used to communicate with other devices

The three hardware blocks are interconnected by the system bus



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The Memory Basic Principles

Memory sequence of memory locations used to store infoEach memory location:

stores an 8-bit number, a byte of data

is identified by a unique number, called address

The memory is accessed and organized by the CPU only The CPU can choose to create logical subdivisions within the

memory (called pages or segments)

The memory map all memory locations that can beaddressed by the CPU (not necessarily implemented)



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The Memory A Closer Look



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The size of the memory is directly linked with the addresssize through the following equation:

Example 1:using an address of 2 bits, one can form 4 different addresses:00, 01, 10, and 11, for up to 4 different memory locationsconsequently, a memory with an address of 2 bits willcomprise 4 memory locations (4 bytes).

Example 2:using a 20-bit address, one can form 2 20 different addresses,corresponding to 2 20 different memory locationsconsequently, a memory with a 20-bit address will comprise220 memory locations (1 MB).


][2 bitseaddressSiz memorySize


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The Memory Contents Significance


This could be a 16-bit result

This could be an instruction

These could be the first two elements inan array of 8-bit numbers

The significance of the information is given by the programmer. The memory doesnt know the significance of the information it stores!


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Input/Output Devices

I/O Devices hardware blocks that form the interfacebetween the microcomputer and the external world

I/O Devices can be regarded as a set of I/O Ports

Each I/O port can be used to:send an 8-bit/16-bit/32-bit number to an external devicereceive an 8-bit/16-bit/32-bit number from an external deviceis identified by a unique number, called port address

The ports map all ports that can be addressed by the CPU(not necessarily implemented)



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The System Bus

Bus set of physical connections that link several hardwareblocks; these connections are used for information transfer

The CPU, Memory and I/O Devices are connected througha unique System Bus with three components:

A bidirectional Data BusTransfers data (operands, results, etc.) and instructions

An unidirectional Address Bus

Through this bus the CPU sends addresses to the Memory andI/O Devices A bidirectional Control Bus

Transfers command and control signals from/to the CPU



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The Software Component

The microcomputer is executing instructions organized incomputer programs, namely the software

Two main categories:The Operating System: set of programs which facilitate theusers access to the systems resourcesUser Software: set of programs specifically created by the user

to achieve a certain task



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Summary


The CPU: executes instructions (processes data) and controls the systemThe Memory: stores both the data and the instructionsThe I/O Devices: interconnect the microcomputer with the outside world


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Information Representation in Computer Systems


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Information Representation inComputer Systems


Information is stored using electronic circuits, called f lip-flops (or bistables), that have two stable states: on/off

The state of a bistable can be used to represent a bit (i.e.binary digit: 0, 1) or a boolean value (true, false)

Data types with more than two possible values are stored

using sequences of bits:Byte (B) a sequence of 8 bits: can store max 2 8 (256) values Word (w) a sequence of 16 bits: can store max 2 16 valuesDouble word (dw) 32 bits: can store max 2 32 values


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Numbers representation


Unsigned (positive) integer numbersNatural binary representation

Signed integer numbersSign & magnitude representation1s complement representation2s complement representation

Signed real numbersFixed point representationFloating point representation


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Integer numbers representation


Decimalvalue

Sign and magnitude 1s complement 2s complement

5 natural binary: 00000101 natural binary: 00000101 natural binary: 00000101

-5natural binary: 00000101

flip the sign bit: 10000101natural binary: 00000101

flip all bits: 11111010

natural binary: 00000101flip all bits: 11111010

add 1: 11111011

12 natural binary: 00001100 natural binary: 00001100 natural binary: 00001100

-12natural binary: 00001100

flip the sign bit: 10001100natural binary: 00001100

flip all bits: 11110011

natural binary: 00001100flip all bits: 11110011

add 1: 11110100


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Real numbers representation


Fixed point representation A fixed sequence of bits is used to represent decimal part

Twos complement representation A fixed sequence of bits is used to represent the fractional part

Natural binary representation

Floating point representation A fixed sequence of bits is used to represent the mantissa

Twos complement representation A fixed sequence of bits is used to represent the exponent

Natural binary representationExample: real number = mantissa 2 exponent


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Characters representation


Codingconventions:

ASCII

UTF-8UTF-16Unicode


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Instructions are represented using sequences of bytes;Some processors have fixed-size instructions8086 has variable-size instructions (1-6 bytes)

The instruction codesare formed of several fields:

one instruction-type fieldnone, one or several data fields

none, one or several address fieldsare associated with mnemonics (to be used in programming)

Example: add AX, 8017h 051780h

Programs representation



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The binary, decimaland hexadecimal bases


Any sequence of bits can also be represented as:a decimal number (number in base 10)

can be written as a sequence of decimal digits (0, 1, , 9)a hexadecimal number (number in base 16)

can be written as a sequence of hexadecimal digits (0, 1, , 9, A,B, C, D, E and F)

Hexadecimal numbers representation conventions:the h suffix: 1A44hthe 0x prefix: 0x1A44

Conversion algorithms

binary decimal

hexa


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2.1 Von Neumann Architecture Reminder and Example


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Block Diagram of a Microcomputer


The CPU: executes instructions (processes data) and controls the systemThe Memory: stores both the data and the instructionsThe I/O Devices: interconnect the microcomputer with the outside world


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Instruction Execution Example


The CPU is reset and starts executing instructions from apredefined address in the memory (100h)

Reset

Executeinstructions from

address 100h


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The CPU sends the address of this first instruction (100h)through the Address BusThe CPU sends a MEM-READ signal through the Control Bus

100h

MEM-READ


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The Memory receives the MEM-READ signal and reads theaddress from the Address Bus

100h

MEM-READ


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The Memory finds the instruction (instruction #1) in thememory location(s) with the corresponding address (100h)


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The Memory sends the instruction through the Data Bus andsends an ACK signal through the Control Bus

instruction #1

ACK


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The CPU receives the ACK signal and reads the instructionfrom the Data Bus

instruction #1

ACK


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The CPU decodes the instruction to "understand" what it hasto do nextLet's suppose that it has to add the value 50h to the valuestored in the memory location with the address 2000h

Decode

instruction


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The CPU sends the address (2000h) on the Address Bus andsends a MEM-READ signal through the Control Bus

2000h

MEM-READ


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The Memory receives the MEM-READ signal and reads theaddress from the Address Bus

2000h

MEM-READ


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The Memory finds the data (85h) in the memory location with the corresponding address (2000h)


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The CPU receives the ACK signal and reads the data from theData Bus

85h

ACK


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The CPU temporarily stores the data in a register


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The CPU adds the value 50h to the register (the result will beD5h)


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The CPU sendsthe result (D5h) through the Data Bus,the address (2000h) through the Address Bus anda MEM-WRITE signal through the Control Bus

2000h

MEM-WRITE

D5h


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The Memory receives the MEM-WRITE signal,reads the address (2000h) from the Address Bus,reads the result (D5h) from the Data Bus andstores the result into the corresponding memory location

2000h

MEM-WRITE

D5h


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The CPU continues by executing the next instruction


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2.2 The Set of General Purpose Registers


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CPU Registers


Register a small amount of storage inside the CPUImplemented as a set of N synchronized bistablesStores N bits of data

Highest access speed among all storage options

Several types of registers:General vs. special purpose (dedicated) registers

Physical vs. logical registersUser-accessible vs. non user-accessible registers


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General Purpose Registers


General purpose registers (GPRs)Set of equally-sized registers used to store temporary data(operands/results) needed in the execution of the programUser-accessible (architectural attributes)Implemented as physical or logical registers

The size of the GPRs performance criterion

Equal to the size of the Internal Data BusThe number of GPRs performance criterion A larger number of GPRs => faster, more compact programs,ease of programming,


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General Purpose Registers


MUX (multiplexer) outputs one of the data inputs(depending on the address inputs)Internal Data Bus extension of the External Data Businside the CPU


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Special Purpose Registers


Special purpose registersDedicated registers that can be used only for specific purposesSize depends on the particular role of the register

Some are user-accessible (architectural attributes), some not

Examples:Data register (DR) and Address register (AR)

Accumulator (A)Status (Flags) register (F)Instruction Pointer (IP)Stack Pointer (SP)


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2.3 The interface between the CPU and the System Bus


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The Data Registerand the Address Register


DR (data register): the CPU Data Bus interface

The data in DR are available to all the hardware blocksconnected on the Data BusThe size of DR is the size of the Data BusDR is not an architectural attribute


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The Data Registerand the Address Register


AR (address register): the CPU Address Bus interface

The address in AR is available to all the hardware blocksconnected on the Address Bus; only the CPU writes in AR The size of AR is the size of the Address Bus AR is not an architectural attribute


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2.4 The Arithmetic and Logic Unit (ALU)


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The Arithmetic and Logic Unit


The Arithmetic and Logic Unit (ALU)digital circuit that performs

integer arithmetic operations: add, subtract, increment, etc.logical operations: and, or, xor, not, clear, shift, rotate, etc.

The inputs to the ALUData to be processed (one or two integer numbers)The operation to be performed (specified by the Control Unit)Possibly some status flags

The outputs of the ALUThe operation result(s) are placed in the Accumulator or on theInternal Data BusThe status flags are updated after each operation


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The Arithmetic and Logic Unit



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The Status Register


The Status Register (also called Flags Register) A collection of flag bits, which store information regardingthe state of the processor

Arithmetic and logic flags

Bits encoding the status of the previous arithmetic/logicoperationUsed and updated by the ALU

Other types of flagsInterrupt enable flagSupervisor flagDirection flag


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The Accumulator and the Shift Register


The Accumulator special purpose registerStores one of the operands before the operationStores the result of the operation

Size equal to the size of the general purpose registersIs user-accessible (architecture attribute)

The Shift Register special purpose register

Used by the ALU to make shift and rotation operationsSize double than the size of the general purpose registersIs not user-accessible


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The Memory Addressing Control Unit


The Memory Addressing Control UnitHardware block that computes the physical address needed toidentify information in the Memory or I/O PortsReceives input from the Internal Data BusPlaces its output (a physical address) in the Address Register

Functionality classificationInstruction addressing (in the program memory)

Sequentially, instruction after instructionNon-sequentially, through jumps

Data addressing (in the data memory)Elementary data addressingStack addressingData arrays addressing


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Memory Management Techniques


Linear Memory OrganizationThe memory is regarded as a single block of memory locationsThe memory is addressed using directly a physical address

Memory SegmentationThe memory is logically divided into segments (non equal-sized,possibly overlapping sections)The memory is addressed using a segment address and an offset

Memory PagingThe memory is logically divided into pages (equal sized, non-overlapping, strictly concatenated sections)The memory is addressed using a page address and an offset


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Sequential Instructions Addressing


Sequential Instructions AddressingThe main principle of the von Neumann architecture Achieved through the means of a counter register

The Program Counter (PC) special purpose registerStores the physical address of the current instructionIncremented after the execution of each instruction

Size equal to the size of a physical addressIn some architectures is user-accessible

Other hardware blocks involved: MUX2 and MUX5


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Sequential Instructions Addressing


The program is executed instruction after instructionThe Instruction Register stores the instruction beforedecoding


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Non-Sequential Instructions Addressing


Exceptions to the normal, sequential execution of a program: jumps, loops or subprogram calls

The jump address can be: An absolute address: a complete physical address

The address is provided by another hardware block through theInternal Data Bus

An offset relative to the address of the current instructionThe offset provided by another hardware block through the InternalData Bus is added to the address in PC

The Program Counter is also updatedOther hardware blocks involved: MUX2, MUX4, MUX5, Adder


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Elementary Data Addressing


The data can potentially reside anywhere in the memory

The data address can be:

An absolute address: a complete physical addressThe address is provided by another hardware block through theInternal Data Bus

An offset relative to the address of the current instructionThe offset provided by another hardware block through theInternal Data Bus is added to the address in PC

Other hardware blocks involved: MUX4, MUX5, Adder


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Stack Addressing


The Stack: LIFO data structure Accessed through the means of a pointer registerPushing an element in the Stack -> decrementing the pointerPopping an element out of the Stack -> incrementing the pointer

Software vs. hardware Stack

The Stack Pointer (SP ) special purpose registerStores the physical address of the top element

Size equal to the size of a physical addressUser-accessible (architecture attribute)

Other hardware blocks involved: MUX3 and MUX5


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Stack Addressing



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Data Arrays Addressing


The Memory can accommodate arrays of data Accessed through the means of index registers, which store thephysical of the first element in the array The address of a random element is obtained by adding a relativeoffset to the index register

Offset size => max number of elements in the array

The Index Registers (IX) special purpose registersStore the physical addresses of various data arraysSize equal to the size of a physical addressUser-accessible (architecture attribute)

Other hardware blocks involved: MUX1, MUX4, MUX5, Adder


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2.6 The Timing and Control Unit


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The Timing and Control Unit


The Timing and Control Unit (TCU)Hardware block inside the CPU that:

fetches, decodes and manages the execution of instructionscontrols the flow of data through the processorcoordinates the activities of the other units within the CPU and alsooutside the CPUachieves the above through timing and control signals

Design: hardwired vs. micro-programmed

The inputs to the TCUThe instruction in the Instruction Register (IR)Internal control signals (the status flags)

The outputs of the TCUInternal control signals (for the blocks within the CPU)External control signals (for the blocks outside the CPU)


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Th I t ti R i t d


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The Instruction Register andthe Instruction Decoder


The Instruction Register (IR) special purpose registerStores the instruction code fetched from the memory Receives input only from the Data RegisterSize equal to the smallest instruction code

Is not user-accessible (not an architecture attribute)

The Instruction DecoderHardware block that decodes instruction codes

Each code has an associated, unique output lineOnly one of the output lines will be 1 at any moment in timeReceives input from the Instruction RegisterSends its output to the Timing and Control Unit


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The Typical CISC Instruction Format


The instructions are stored in the memory in one or severalmemory locations (depending on the type of instruction)

Instruction format all the information required by the CPU to

execute an instructionComprises at least one byte: the instruction code (the semantic)The instruction code may require additional bytesMay comprise operands, addresses, offsets on one or several bytes1-6 bytes for 16-bit x86 microprocessors1-15 bytes for 32-bit x86 microprocessorsExample:

code [code] [data oraddress][data oraddress]

[data oraddress]


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Instruction Execution Timing


Typically, the execution of an instruction has several stages:Fetch the instruction code is read from the memory Decode the instruction code is decodedExecute the instruction is executed (might comprise operands fetch) Write the result is written in a register or a memory location

The instruction execution stages are called machine cycles Any instruction is executed in one or several machine cycles (depending onits complexity)In a machine cycle the CPU executes sequentially several elementaryactions accomplishing a clear, well-defined task

Elementary actions are executed once every clock cycle An internal clock signal is generated based on an external quartz oscillator A CPU state is a physical time period equal to the duration of a clock cycleIn a state, the CPU executes one elementary action or two independentelementary actions (in the same time)


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Instruction Execution Timing Example


Instruction example: (2000h)


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Machine Cycle 1: Fetch




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T1. (AR)


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T2. (PC)


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T3. (IR)


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T4. decode instruction code


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Machine Cycle 2: Read Address




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T1. (AR)


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T3. (AUX2)


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T1. (AR)


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T2. (PC)


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T3. (AUX1)


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Machine Cycle 4: Read Operand 1




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T1. (AR)


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T2. (PC)


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T3. (A)


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Machine cycle 5: Read operand 2 and Execute


T2. (DR)


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Machine cycle 5: Read operand 2 and Execute


T3. (A)


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Machine Cycle 6: Write Result




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M hi C l 6 W i R l


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Machine Cycle 6: Write Result


T2. (AR)


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2.7 Summary

S


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Summary


General Purpose Registers (GPRs)Memory Data Register (MDR)Memory Address Registers (MAR)

Arithmetic and Logic Unit (ALU)Memory Addressing Control UnitTiming and Control Unit (TCU)


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3.1 The Registers

86 R i t


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x86 Registers


Types of registers:General vs. special purpose (dedicated) registersPhysical vs. logical registersUser-accessible vs. non user-accessible registers

Size of registers:8/16-bit for the 16-bit microprocessors8/16/32-bit for the 32-bit microprocessors8/16/32/64-bit for the 64-bit microprocessors

86 G l P R gi t


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x86 General Purpose Registers


x86 GPRs: AX, BX, CX, DX (16-bit registers)Multifunctional: can be potentially used for any operationThey have implicit functions alsoCan be accessed as two separate bytes: AH, AL, BH, BL, etc.In 32-bit microprocessors they are: EAX, EBX, ECX, EDX

Implicit functions AX AccumulatorBX Base index (for use with arrays)CX Counter (for use with loops and strings)DX Extend the precision of the accumulator

86 Pointer Registers


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x86 Pointer Registers


x86 Pointer Registers: SP, BP (16-bit registers)Multifunctional: can be potentially used for any operationThey have implicit functions alsoIn 32-bit microprocessors they are: ESP, EBP (32-bit registers)

SP Stack pointerStores the effective address of the element in the top of the stackUsed implicitly in several instructions: push, pop, call, ret, int

BP Base pointerUsed to point at some other place in the stackStores the effective address of another value in the stack

x86 Index Registers


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x86 Index Registers


x86 Index Registers: SI, DI (16-bit registers)Multifunctional: can be potentially used for any operationUsed implicitly in array indexing instructions: movs, lods,stos, cmps, scas

In 32-bit microprocessors they are: ESI, EDI (32-bit registers)

SI Source IndexStores the effective address or the index of the currentelement in the source array

DI Destination IndexStores the effective address or the index of the currentelement in the destination array

x86 Flags Register


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x86 Flags Register


The x86 Flags register (F)

A collection of 16 flag bits, which store information regarding thestate of the processor

Used implicitly in several instructions: pushf, popf, lahf, sahf

Interrupt enable f lag (IF): determines whether or not the CPU willhandle maskable hardware interrupts

Trap flag (TF): permits operation of a processor in single-step mode

Direction flag (DF): controls the left-to-right or right-to-leftdirection of array processing

x86 Arithmetic and Logic Flags


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x86 Arithmetic and Logic Flags


Carry flag (CF): signals an arithmetic carry or borrow for unsignednumbers

Auxiliary flag (AF): signals an arithmetic carry over the first nibble

Parity flag (PF): signals that the number of ones in the least significantbyte of the result is even

Zero flag (ZF): signals that the result is 0

Sign flag (SF) : signals that the most significant bit of the result is set(this is the sign bit in two s complement representation)

Overflow flag (OF): signals an arithmetic overflow for signed numbers

x86 Segment Registers


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x86 Segment Registers


x86 Segment Registers: CS, DS, ES, SS (16-bit registers)Special purpose registersUsed for memory management: the memory is logicallysegmented into smaller parts called segments32-bit microprocessors use the same registers: CS, DS, ES, SS

Segment registers store segment addresses for:The code segment CSThe data segment DSThe extended data segment ESThe stack segment SS


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x86 Register Summary


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x86 Register Summary


x86 has very few registers4 general purpose registers, 2 index registers, 2 pointer registers

Some of the x86 registers are multifunctional

x86 has 4 segment registersspecial functions in memory management

All the registers are user-accessible; one exception: IP

The size of the registers is usually the size of the Internal DataBus


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3.2 Memory Management



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Memory sequence of memory locations used to store infoEach memory location:

stores an 8-bit number, a byte of datais identified by a unique number, called address

The memory is accessed and organized by the CPU only The CPU can choose to create logical subdivisions within thememory (called pages or segments)

The memory map all memory locations that can beaddressed by the CPU (not necessarily implemented)




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Linear Memory OrganizationThe memory is regarded as a single block of memorylocationsThe memory is addressed using directly a physical address

Memory SegmentationThe memory is logically divided into segments (non equal-sized, possibly overlapping sections)The memory is addressed using a segment address and anoffset


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Logic Address -> Physical Address


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Logic Address -> Physical Address


The logic address (LA)32-bit address; concatenation of SA and EA

The physical address (PA) is not an architecture attribute!The logic address, segment address and effective addressare architecture attributesThe microprocessor translates the LA into a PA in order toaccess the memory: PA = SA 0h + EA

Default Memory Segments


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Default Memory Segments


Segment addresses (SAs) can be stored in segmentregisters

CS stores the SA of the current code segmentDS stores the SA of the current data segment

ES stores the SA of the current extended data segmentSS stores the SA of the current stack segment

Segments can start only at physical addresses which aremultiples of 16

Effective addresses (EAs)can be stored in address registers:BX, SI, DI, SP, BP and IP

Special (SA EA) pairs


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Special (SA, EA) pairs


Particular address registers are associated with particularsegment registers:

IP+CS the physical address of the current instruction isformed using the effective address in IP and the segment

address in CSSP+SS the physical address of the element in the top of thestack is formed using SP and SSBP+SS, BX+DS, SI+DS, DI+ES

Segment redirectionSegment overlapping

x86 Memory Segmentation Summary


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x86 Memory Segmentation. Summary


The memory can be regarded as a sequence of memory locations

Each memory location stores an 8-bit number and has a unique20-bit address, called physical address

The x86 CPU regards the memory as being composed of 64ksegments comprising 64k locations each

The x86 CPU uses a 16-bit segment address to select a segmentand a 16-bit effective address to identify a memory locationinside the segment

The translation between the logical organization of the memoryin segments and the physical address is done as follows:PA = SA 0h + EA


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3.3 Memory Access. Addressing Modes

What is an Addressing Mode?


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What is an Addressing Mode?


A technique to specify the location of the operands andresults

Specifies how to calculate the effective memory address ofoperands and results, using information in registers and/orconstants with the instruction format

Defines how machine language instructions in thearchitecture identify the operands /results of eachinstruction

Register Implicit Addressing


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Register Implicit Addressing


The targeted information is found in a register (not in thememory)The information regarding which register stores the data iscoded in the instruction code (the first byte in theinstruction)

The instruction code comprises several fields; among them:the fields which code the source/destination registersThe targeted information is anoperand or a result

Minimum instruction size: 1B

instr.code addr low addr high data

instr.semantic

code

destregister

code

sourceregister

code

register

Immediate Addressing


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Immediate Addressing


The targeted information is found in the memory, in theinstruction, immediately after the instruction code

The targeted informationis coded in the instruction; it is a constantis an operandcannot be a resultcannot be an instruction

Minimum instruction size: 2B (the data has at least 1B)

instr.code data low data high

Direct (Absolute) Addressing


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Direct (Absolute) Addressing


The targeted information is found in the memory, at anaddress coded in the instruction

The address is in the program memory

The targeted information is in the data or program memory Minimum instruction size: 3B (the address has at least 2B)

instr.code addr low addr high

data

Relative Addressing


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Relative Addressing


The targeted information is found in the program memory,at an address obtained as a sum between the address of thecurrent instruction and an offset coded in the instruction

The offset can be positive or negativeThe targeted information can be an operand or aninstructionMinimum instruction size: 2B (the offset usually has 1B)

instr.

codeoffset data

IP (addr)

+

Register Indirect Addressing


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g g


The targeted information is found in the memory, at anaddress specified in a register coded in the instruction code

The targeted information can be an operand, a result or aninstructionOne register might not be enough to store an addressMinimum instruction size: 1B

instr.

semantic

code

addr.register

code

register (addr)

data

Memory Indirect Addressing


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y g


The targeted information is found in the memory, at theaddress specified in a memory location(s) whose address isspecified in the instruction code

The targeted information can be an operand, a result or aninstructionMinimum instruction size: 3B (the address has at least 2B)

data instr.code addr low addr high

addr low addr high

Base plus Index Addressing


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p g


The targeted information is found in the memory, at theaddress obtained as a sum between the address stored in aregister and an offset (index) coded in the instruction

The address stored in the register is usually the base addressof an array of data (the address of the first element)The targeted information can be an operand or a resultMinimum instruction size: 2B (the offset has at least 1B)

data data data instr.code offset

register (addr)

+

Addressing Modes Summary


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g y


Various addressing modessome simpler, some more complicatedsome can be used for instructions also, some only for datathe route to the data can be direct or indirect

the targeted information can be in a register, in the programmemory or in the data memory

Depending on the addressing mode, the minimuminstruction size can be 1B / 2B / 3B

The information stored in the instructions can have varioussemantics / meanings: data, offset, address, etc.

x86 Addressing Modes


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g


Program addressing modesRelative addressingDirect addressingRegister indirect addressing

Data addressing modesSeveral simple addressing modesComposed addressing modes

Base-relative addressing modesStack-relative addressing modes


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x86 Data Addressing Modes


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g


Used to address data only

Register implicit addressing (mov AH , BL)The targeted information is in a register:

8-bit register: AL, AH, BL, BH, CL, CH, DL, DH16-bit register: AX, BX, CX, DX, SI, DI, SP, BP

Immediate addressing (mov AX, 1234h)The targeted information is in the memory, in the codesegment, at the effective address IP + 1


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x86 Data Addressing Modes


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g


The targeted information is implicitly found in the datasegment

The targeted information can also be found in the codesegment, extended data segment or stack segment

A redirection prefix should be used


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x86 Stack-relative Addressing Modes


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Direct stack relative addressing (mov AX, [BP + 1234h])

The targeted information is in the memory, in the stack segment, atan effective address obtained as a sum between the content of BP andan offset stored in the current instruction

Indexed stack relative addressing (mov AX, [BP + DI + 10h] )The targeted information is in the memory, in the stack segment, atan effective address obtained as a sum between the content of BP, thecontent of SI or DI and an offset stored in the current instruction

Implicit stack relative addressing (mov AX, [BP+SI] )The targeted information is in the memory, in the stack segment, atan effective address obtained as a sum between the content of BP, thecontent of SI or DI


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3.4 The Instruction Set

Microprocessor Instruction Types


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Data transfer instructionsset a register or a memory location to a fixed constant valuecopy data from a memory location to a register, or vice versaread and write data from I/O devices

Data processing instructionsarithmetic operations (add, subtract, multiply, divide, etc.)

logic operations (and, or, exclusive or, shift, rotate, etc.)bitwise logic operationscompare operations

Control flow instructionsbranch to another location in the program and execute instructionsthereconditional branch to another location if a certain condition holdsbranch to another location, while saving the location of the nextinstruction as a point to return to (a call)

Data Transfer Instructions


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Two operands: a source and a destinationGeneral idea: the source is copied at the destination

The source and the destination:Can be registers, memory locations, constants, I/O ports Are identified using various addressing modesMust have the same size

Performance criterion: transfer as much data as possibleusing an instruction with a small format

x86 Simple Data Transfer Instructions


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MOV Move (Copy) Data

XCHG Exchange Data

LEA Load Effective Address

PUSH Push data in the Stack

POP Pop data out of the Stack


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XCHG Exchange Data


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Usage: XCHG dest, src Arguments:

dest - register or memory locationsrc register or memory location

Effects: Exchanges the source with the destination:(dest) (src)

Flags: noneMiscellaneous: two memory locations cannot be used inone instruction

XCHG Exchange Data


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PUSH Push Operand in the Stack


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Usage: PUSH src Arguments: src 16-bit immediate value, register ormemory locationEffects: Decrements stack pointer with 2 and copies src ontop of the stack:

(SP) (SP) 2((SS):(SP)+1) (srchigh)((SS):(SP)) (src low)

Flags: noneMiscellaneous: src must be a 16-bit value



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POP Pop a word from the Stack


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Usage: POP dest Arguments:

dest 16-bit register, segment register or memory locationEffects: Copies the element (16-bit) from the top of thestack into dest and increments the stack pointer with 2:

(dest high) ((SS):(SP)+1)(dest low) ((SS):(SP))(SP) (SP) + 2

Flags: none

POP Pop a word from the Stack


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The Source and the Destination Arrays


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The x86 architecture defines two implicit memory zones whichstore two arrays of 8-bit or 16-bit numbers

The source arrayStored in the data segment (the segment with the address in DS)The current element is at the effective address specified in SI

The destination array Stored in the extended data segment (the segment with the addressin ES)The current element is at the effective address specified in DI

The arrays are iterated from left-to-right or vice-versa based onthe value of the direction flag (DF)

x86 String / Array Instructions


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MOVS Move String

LODS Load StringSTOS Store String

SCAS Scan StringCMPS Compare String

STD Set Direction FlagCLD Clear Direction Flag

MOVS Move String


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Usage: MOVSB / MOVSW Arguments: noneEffects:

movsb:

((ES):(DI)) ((DS):(SI))(SI) (SI) 1, (DI) (DI) 1.movsw:

((ES):(DI)) ((DS):(SI)), ((ES):(DI)+1) ((DS):(SI)+1)(SI) (SI) 2, (DI) (DI) 2.

Flags: noneMiscellaneous: can be prefixed by rep, repe/repz,repne/repnz

MOVS Move String


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MOVS Move String


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MOVS Move String


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LODS Load String


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LODS Load String


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STOS Store String


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Usage: STOSB / STOSW Arguments: noneEffects:

stosb: Copies the value in the accumulator in the current 8-bitelement in the destination string and increments (if DF=0) ordecrements (if DF=1) the value in DI by 1:

((ES):(DI)) (AL), (DI) (DI) 1.stosw: Copies the value in the accumulator in the current 16-bit element in the destination string and increments (ifDF=0) or decrements (if DF=1) the value in DI by 2:

((ES):(DI)) (AL), ((ES):(DI)+1) (AH), (DI) (DI) 2.Flags: none


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Data Processing InstructionsAn arithmetic operation is applied to one or several sources and


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An arithmetic operation is applied to one or several sources andthe result is stored in the destinationThe arithmetic f lags (CF, AF, ZF, PF, SF, OF) are modified!

The sources and the destination:Can be registers, memory locations, constants, I/O ports Are identified using various addressing modesMust have the same size (exceptions: multiplication, division)

CISC processors characteristics:Data processing uses an accumulator (one of the sources is also thedestination)

The sources and the destination are memory locationsExecution time depends on instruction complexity

Performance criterion: fast execution of complex data processingoperations

x86 Arithmetic Instructions


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INC IncrementDEC Decrement

ADD Add ADC Add with Carry

SUB SubtractSBB Subtract with Borrow

MUL Multiply

DIV Divide

CMP Compare

CMP Compare two operands


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Usage: CMP src1, src2 Arguments:src1, src2 8bit or 16bit immediate value, register or memorylocation;

Effects: Subtracts src2 from src1: (src1) (src2). Flags are set in

the same way as the SUB instruction does, but the result is of thesubstraction is not saved.Flags: The CF, ZF, OF, SF, AF, and PF flags are modified acordingto the result.Misc:

usually the next operation would be a conditional jump to performan operation according to the result of the comparison;only one memory argument is allowed and both arguments have tobe of the same size



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ADD Integer Addition


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Usage: ADD d, s Arguments:

dest - register or memory locationsrc - immediate, register or memory location; (two memory

operands cannot be used)Effects: Adds the source to the destination:

(dest) (dest) + (src).Flags: The CF, ZF, OF, SF, AF, and PF flags are set accordingto the result.Misc: no difference between signed and unsigned operands



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ADC Add with Carry


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Usage: ADC d, s

Arguments: same as for ADD

Effects: Adds the the carry flag (CF) and the source to thedestination: (d) (d) + (s) + (CF)

Flags: same as for ADD

Misc: same as for ADD

ADC Add with Carry


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SBB Integer Subtraction with Borrow


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MUL Unsigned Multiplication of AL or AXUsage: MUL src


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g

Arguments:src 8bit or 16bit register or memory location.Effects:

if src is an 8-bit value: multiplies the value stored in AL by srcand stores the result in AX:

(AX) (AL) * (src)CF and OF are set to 0 if AH is 0, otherwise they are set to 1.

if src is a 16-bit value: multiplies the value stored in AX by srcand stores the result in DX concatenated with AX:

(DX) (AX) (AX) * (src)CF and OF are set to 0 if DX is 0, otherwise they are set to 1.

Flags: CF and OF are modified as mentioned above. Therest of the flags are undefined.

MUL Unsigned Multiplication of AL or AX


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MUL Unsigned Multiplication of AL or AX


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DIV Unsigned DivisionUsage: DIV src


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Arguments:src 8-bit or 16-bit register or memory location;Effects:

if src is an 8-bit value: divides by src the value stored in AX andstores the remainder in AH and the quotient in AL:

(AH) (AX) mod (src), (AL) (AX) div (src)if src is a 16bit value: divides by src the value stored in DXconcatenated with AX and stores the remainder in DX and thequotient in AX:

(DX) (DX) (AX) mod (src), (AX) (DX) (AX) div (src)

Flags: The CF, ZF, OF, SF, AF, and PF flags are undefined.Misc:if the quotient is larger than 8bits (16bits) and cannot be stored in AX (DX AX) then a divide overflow error will be thown.


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DIV Unsigned Division


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x86 Logic Instructions


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NOT Complement AND Logic ANDOR Logic OR XOR Exclusive OR

SHL | SAL Shift Left (Arithmetic and Logic)SHR Logic Shift RightSAR Arithmetic Shift RightROL Rotate LeftROR Rotate Right

RCL Rotate Left with Carry RCR Rotate Right with Carry

TEST Compare using AND

NOT, OR, AND, XOR


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I1 I2 OR 0 0 0

0 1 11 0 11 1 1

I1 I2 XOR0 0 0

0 1 11 0 11 1 0

I1 I2 AND0 0 00 1 01 0 01 1 1

I NOT0 11 0

SHL, ROL, RCL


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SHR and SAR


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Control Flow Instructions


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Exceptions in the sequential execution of instructions:Branch to a different instructionConditional branch to a different instruction

Can be used to create decision structures

Conditional skip of the current/following instructionCan be used to create inline decision structures

Counter update + conditional branch (loop)Can be used to create repetitive structures

Return address save + branch to a different instruction (call)Can be used for subprogram calls

x86 Control Flow Instructions


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Unconditional branch: JMP jumpConditional branches:

For unsigned numbers: JA|JNBE, JAE|JNB|JNC, JB|JNAE, etc.For signed numbers: JG|JNLE, JGE|JNL, JL|JNGE, etc.For other type of comparisons: JP, JE, JS, JO, etc.

Counter update + conditional branches:LOOP, LOOPZ, LOOPNZ

Call and return branches:CALL, RET

x86 Conditional Jump InstructionsInstruction Usage Condition Description


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Instruction Usage Condition Description

JE | JZ JE label (ZF)=1 Jump to label if equal | zero

JNE | JNZ JNE label (ZF)=0 Jump to label if not equal | not zero

JNO JNO label (OF)=0 Jump to label if not overflow

JNP | JPO JNP label (PF)=0 Jump to label if not parity | parity odd

JNS JNS label (SF)=0 Jump to label if not signed | positive

JO JO label (OF)=1 Jump to label if overflow

JP | JPE JP label (PF)=1 Jump to label if parity | parity even

JS JS label (SF)=1 Jump to label if signed | negative

x86 Loop Instructions


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Instruction Usage Condition Description

LOOPLOOPlabel

(CX) != 0Decrement CX (without modifying theflags) and jump to label if CX is notzero

LOOPE |LOOPZ

LOOPElabel

(CX) != 0AND (ZF)=1

Decrement CX (without modifying theflags) and jump to label if CX is notzero and ZF is one.

LOOPNE |LOOPNZ

LOOPNElabel

(CX) != 0AND (ZF)=0

Decrement CX (without modifying theflags) and jump to label if CX is notzero and ZF is zero.

CALL Call Subprogram


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Usage: CALL dest Arguments:

dest (target) address of the first instruction in the calledsubprogram; can be an immediate value, a general purpose registeror a memory location;

Effects:The address of the next instruction is saved in the stack and theinstruction pointer is set to the target address (the CPU performs a jump to the subprogram):

(SP) (SP) 2, ((SS):(SP)+1) (IPhigh), ((SS):(SP)) (IP low)(IP) (dest)

Flags: noneMisc: Usually there is a RET instruction in the subprogram toreturn to the instruction after the call.

CALL Call Subprogram


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RET Return from Subprogram


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Usage: RET Arguments: noneEffects:

The CPU pops the value in the top of the stack and uses it to

jump back to the caller program:(IPhigh) ((SS):(SP)+1), (IPlow) ((SS):(SP))(SP) (SP) + 2.

Flags: none

Misc: Usually the address was placed in the stack by a callinstruction and the return is made to the address thatfollows the call instruction.

RET Return from Subprogram


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x86 Subprogram Calls


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The CALL and RET instructions do not have input/outputparameters as arguments

There are several conventions for sending I/O parameters

Through General Purpose RegistersThrough the StackThrough the Memory


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3.5 Summary

Summary


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The x86 Registers

Memory Management

Memory Access. Addressing Modes

The Instruction Set


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4.1 Introduction

RISC Philosophy. Motivation


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DARPAs VLSI Project (70 80)how efficient are the current microprocessors?provided research funding to university-based teamsto improve the state of the art in microprocessor design

Studies in CPU design showed thatsimplified instructions can provide higher performance if thissimplicity enables much faster execution of each instruction

a CPU with a small, highly-optimized set of instructions, canbe more efficient than a CPU with a more specialized set ofinstructions

Historical BackgroundRISC: Reduced Instruction Set Computer

t f i hit t th t tili ll


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a type of microprocessor architecture that utilizes a small,highly-optimized set of instructions instead of a morespecialized set of instructions

The first RISC projects (mid 70s and early 80s)

IBM: the IBM 801 architectureStanford University: Stanford MIPS architectureUniversity of California, Berkeley: Berkeley RISC I and II

commercialized as the SPARC architecture

Other well-known RISC architectures: ARM, Atmel AVR, Intel i860/i960, PA-RISC, PowerPC

RISC Principles (I)


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Hardwired Control UnitOne cycle execution timeEach instruction is hardwired to be executed in a single cycleCPI (clocks per instruction) = 1reduced -> the amount of work any single instructionaccomplishes is reduced

Pipelining is usedTechnique that allows for simultaneous execution of parts ofinstructions

Leads to a more efficient instructions processingLarge number of general purpose registersPrevents large amounts of interactions with memory

RISC Principles (II)


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Small number of instructionsFixed instruction format(s)

Decreases the time needed to decode the instructionsFixed instruction size

Small number of addressing modesLeads to a small size of the addressing mode code

Memory access only through LOAD/STORE instructionsData processing instructions cannot use memory operandsHelps to obtain the CPI=1 desiderate


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4.2 The Registers

A Large Number of GPRs. Benefits


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Higher processing speed thanks to a lower number ofmemory accesses

Hardware data structures (stacks and queues) created with

general purpose registers

Input/output parameters to/from subprograms aresent/received through GPRs

Increased chip uniformity factor


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Register Set Organization


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A single set of registers

Comprising at least 32 physical registersNo logical registers

Any physical register is accessed by decoding a register codeThe registers are accessed similarly to the linearly organizedmemory

Register Set Organization


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Multiple sets of logical registers in a singleset of physical registers

Each set of logical registers

Comprises at least 32 registersCan be accessed using a pointerIs allocated to a different program

The logical physical mapping is bijective

Register Set OrganizationMultiple sets of logical registers, partiallyoverlapped, in a single set of physical registers


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overlapped, in a single set of physical registers

Each set of logical registersComprises at least 32 registersCan be accessed using a pointerIs allocated to a different program

The logical physical mapping is notbijective anymore!

The overlapping portions are called register windows

Register Set OrganizationMultiple sets of logical registers in multiple sets of physical


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registers: useful for multiprocessing

Berkeley RISC II Register Set8 sets of logical registers in a single set of 138 physical registersEach set of logical registers (the work-set for each program)


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Each set of logical registers (the work set for each program)comprises:

10 registers for global variables - shared with all programs10 registers for local variables6 registers for I/O parameters - shared with the calling program6 registers for parameters - shared with the called program

1 set of physical registers (R)8 sets of logical registers (A H)


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Mapping examples:R0 = A0 = = H0R9 = A9 = = H9

R10 = A10 = H26

R15 = A15 = H31

R16 = A16R25 = A25

R26 = A26 = B10R31 = A31 = B15


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4.3 The Instruction Set

RISC Instruction Set Characteristics


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Fewer instructions than in CISC instruction setSimpler instructions than in CISC instruction setInstruction types

Memory access instructions (load / store)

Arithmetic and logic processing instructions Always with register or immediate operandsTypically without an accumulator

Control flow instructions

Subprogram calls use register windows for parameter passingI/O instructions

RISC Typical Addressing Modes

Register implicit addressing


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Immediate addressing

Direct (absolute) addressing

Register indirect addressing

Base-relative direct addressing

Base-relative indexed addressingRelative (to PC) addressing

Intel i860 / i960 Instruction Examples


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Note: in these examples s1, s2 and d are general purposeregisters

Signed integer addition

adds s1, s2, d ;(d) (s1)+ (s2)Memory access with two pointers

ldl.l s1(s2), d ;(d) ((s2)+ (s1))Memory access using a constant

st.s s1, #const(s2) ;((s2)+ const) (s1)Left shift with three operands

shl s1, s2, d; ;(d) (s2)* 2(s1)

ARM Instruction ExamplesNote: in these examples s1, s2, s3 and d are general purposeregisters


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g

Logic AND with three operandsand d, s1, s2 ;(d) (s1)& (s2)

Memory access with pre-indexingldr d, [s1+#const]! ;(d) ((s1) + const)

;(s1) (s1) + constMemory access with post-indexing

str s1, d, #8 ;((d)) (s1)

;(s1) (s1) + constMultiply and add (four operands)

mla d, s1, s2, s3; ;(d) (s1)* (s2) + (s3)


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4.4 The Timing and Control Unit

Instruction format for:Simpler Instruction Decoder


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Intel x86 (CISC) microprocessors1 15 bytes, depending on instruction complexity Intel i860 (RISC) microprocessors

4 bytes, regardless of the instruction complexity Stanford MIPS (RISC) microprocessors

4 bytes, regardless of the instruction complexity

Fixed instruction format -> simpler Instruction Decoder-> simpler Memory Addressing Unit


Hardwired Timing and Control Unit


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The Timing Control Unit isMicro-programmed for CISC microprocessorsHardwired for RISC microprocessors

Example: 32bit x 32bit multiplicationMicro-programmed Control Unit

Uses the same ALU and MACU + a micro-programHardwired Control Unit

Uses a dedicated hardwired circuit


32b x 32b CISC Multiplication


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result 0

for i = 1 to 32 doif multiplier(i) = 1result result + multiplicand

end_if multiplicand multiplicand * 2

end_for

32b x 32b RISC Multiplication


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PremisesRISC Instructions Pipelining


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All instructions (simple/complex) are executed in the sameamount of time / clock cycles All instructions are executed in a sequence of stages; example:

fetch the instruction from the memory decode the instructionread the operandsexecute the instruction write the result into a register

Pipelining concept: at any moment in time themicroprocessor executes simultaneously several differentstages for several pipelined instructions; this leads to CPI=1


Pipeline example


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If the execution of every instruction can be broken up in Nstates, then one can build a pipeline structure with N stages

RISC Instructions Pipelining. Summary


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p p gThis leads to the simultaneous execution of N instructions

Pipelining concept: at any moment in time severalinstructions are in progress of execution, in various stages

Instructions pipelining is possible because of the fact that allinstructions are executed in the same amount of time

Instructions pipelining leads to the desiderate CPI = 1Note that pipelining does not work continuously (exceptions)



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4.5 Compiler Particularities (Issues)

Compiler computer program that transforms source code written in a high-level programming language to a lower

RISC Compilers


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level language (e.g., assembly language or machine code)

The efficiency of RISC architectures, obtained throughmany optimizations and simplifications, also involve strong

software-layer constraints=> RISC machines are shipped with dedicated compilers

RISC compilers issuesRegister allocation

Optimal allocation of variable values to logical registersPipeline correct execution and efficiency management

Data dependence, jump and load/store instructions management22.05.2014 243Microprocessors Architecture

Register allocation

Register Allocation


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the process of determining which values should be placedinto which registers and at what times during the execution ofthe program values, not variables are allocated to various registers, because

distinct uses of the same variable can be assigned to differentregisters without affecting the logic of the program

Local register allocationallocation within a very small piece of code, typically a basicblock

Global register allocationassigns registers within an entire function



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The Interference / Color Graph


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Values used in a function: A, B, C, , F

Lifetime of the values represented as timelines over asequence of CPU states

Available registers: R1, R2, R3

The interference / color graphNodes the values A, B, C, , FEdges indicate lifetime overlapping of the valuesLabels outside nodes the register allocated for the value



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The Pipeline and Jumps Management


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The problem:The instructions following JMP should not be introduced inthe pipelineThe instructions to be introduced in the pipeline are knownonly after the execution of JMP (the jump address iscomputed)

The solution:The compiler should insert several NOP instructions afterevery JMP instruction

The drawback: NOPs introduce delays => CPI > 1



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The Pipeline and Jumps ManagementOptimizations (code reordering) are sometimes possible:

ADD r3, r2, r1


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AND r0, r5, r6JMPZ r0, labelNOPNOPNOPNOPXOR r5, r3, r2....

label: SUB r1, r5, r6

AND r0, r5, r6JMPZ r0, labelADD r3, r2, r1NOPNOPNOPXOR r5, r3, r2....

label: SUB r1, r5, r6

ADD does not interfere with the execution of JMPZ,therefore it can be moved downwards, instead of a NOP. AND cannot be moved because the jump is taken / nottaken depending on its result!

The Pipeline and Data DependencyADD r1, r2, r7AND r6, r1, r3


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The Pipeline and Data Dependency

Th bl


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The problem:The value computed by ADD is not available in thedestination register (R1) when AND needs to read itThe AND reads an old value of R1 and the program does not work correctly anymore

The solution:The compiler should insert several NOP instructions afterevery ADD instruction in order to delay the next instruction

The drawback: NOPs introduce delays => CPI > 1

The Pipeline and Data Dependency


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The Pipeline and Data DependencyOptimizations (code reordering) are sometimes possible:

MUL 8 2 1


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MUL r8, r2, r1SUB r0, r5, r6ADD r1, r2, r7NOPNOPAND r6, r1, r3....

MUL and SUB do not interfere with the execution of ADD,therefore it can be moved downwards, instead of the NOPs

Data dependency appears in the case of data processinginstructions, but also for memory access instructions:

ADD r1, r2, r7MUL r8, r2, r1SUB r0, r5, r6AND r6, r1, r3....

LOAD r0, memSUB r6, r1, r0

Pipeline Correct Execution andEfficiency Management

G ll h i li h i b f ll d


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Generally the pipeline technique can be successfully usedto

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