Micro transductors ’08 Low Leakage VLSI Design Dr.-Ing. Frank Sill Department of Electrical...

Micro transductors ’08Micro transductors ’08 Low Leakage VLSI DesignLow Leakage VLSI Design

Dr.-Ing. Frank SillDepartment of Electrical Engineering, Federal University of Minas Gerais,

Av. Antônio Carlos 6627, CEP: 31270-010, Belo Horizonte (MG), Brazil

[email protected]

http://www.cpdee.ufmg.br/~frank/

Micro transductors ‘08, Low Leakage 2Copyright Sill, 2008

AgendaAgenda

Recap Trends Leakage components Leakage reduction

On technology level On transistor and gate level On architecture level


Recap: Problems of Power DissipationRecap: Problems of Power Dissipation

Continuously increasing performance demands

Increasing power dissipation of technical devices

Today: power dissipation is a main problem

High Power dissipation leads to:

High efforts for cooling

Increasing operational costs

Reduced reliability

High efforts for cooling

Increasing operational costs

Reduced reliability

Reduced time of operation

Higher weight (batteries)

Reduced mobility

Reduced time of operation

Higher weight (batteries)

Reduced mobility


Most popular method for power reduction of clock signals and functional units

Gate off clock to idle functional units Logic for generation of disable signal necessary

Higher complexity of control logic Higher power consumption Critical timing critical for avoiding of

clock glitches at OR gate output Additional gate delay on clock signal

Recap: Clock GatingRecap: Clock Gating

Reg

clock

disable

Functionalunit

Source: Irwin, 2000


Recap: Parallel ArchitectureRecap: Parallel Architecture

Comb.Logic

Copy 1

Comb.Logic

Copy 2

Comb.Logic

Copy N

Re

gis

ter

Re

gis

ter

Re

gis

ter

Re

gis

ter

N to

1 m

ulti

ple

xer

MultiphaseClock gen. and mux

control

InputOutput

CK

fclk

fclk/N

Each copy processesevery Nth input,operates atreduced voltage

Supply voltage:VN ≤ Vref

N = Deg. of parallelism

Source: Agarwal, 2007

fclk/N

fclk/N


DataData

Recap: Pipelined ArchitectureRecap: Pipelined Architecture

Reduces the propagation time of a block by factor N

Voltage can be reduced at constant clock frequency Constant throughput

Functionality:

CLK

Area A

CLK

CLK

A/N A/NA/N


Recap: BussesRecap: Busses

Shared Bus

B

B

Segmented Bus

Source: Evgeny Bolotin – Jan 2004

Bus segmentation Another way to reduce shared buses Control of bus segment by controller blocks (B)


Recap: Adaptive DVSRecap: Adaptive DVSS

peed

Time

T1 T2 T1 T2

Idle

Same work,lower energy

TaskTask

Task with 100 ms deadline, requires 50 ms CPU time at full speed Normal system gives 50 ms computation, 50 ms idle/stopped time Half speed/voltage system gives 100 ms computation, 0 ms idle

Same number of CPU cycles but: E = C (VDD/2)2 = Eref / 4

Dynamic Voltage Scaling adapts voltage to workload

Time


0

10

20

30

40

50

60

70

80

90

100

300 400 500 600 700 800 900 1000

Frequency (MHz)

% o

f m

ax p

ow

erl c

on

sum

pti

on

300 Mhz0.80 V

433 Mhz0.87 V

533 Mhz0.95 V

667 Mhz1.05 V

800 Mhz1.15 V

900 Mhz1.25 V

1000 Mhz1.30 V

Typical operating region Peak performance region

Recap: Processor ModesRecap: Processor Modes

Source: Transmeta


Battery aware designBattery aware design

1000 mAh(Standard Capacity)

Discharge current (mA)

Cap

acity

(m

Ah)

( Rated Current)125mA

1000800

600

400

200

AvailableCharge(mA) time

idleDischarge

Current(mA)

time

Non-linear effects influence life time of batteries

“Rate Capacity” If discharging currents

higher than allowed

real capacity goes under nominal capacity

“Battery Recovery” Pulsed discharge increases

nominal capacity Based on recovery times (as long there is no rate

capacity effect)

Source: Timmermann, 2007


Si Substrate

Metal Gate

High-kTri-Gate

S

G

D

III-V

S

Carbon Nanotube FET

50 nm

35 nm

30 nm

SiGe S/D

Strained Silicon

SiGe S/D

Strained Silicon

90 nm65 nm

45 nm32 nm

20042006

20082010

2012+

Technology Generation

20 nm 10 nm

5 nm5 nm

5 nm

Nanowire

Manufacturing Development Research

TrendsTrends


0

200

400

600

800

1000

1200

1400

90 nm 65 nm 45 nm 32 nm 22 nm 16 nm

Pow

er D

issi

pat

ion

[W]

(10

0 m

m²

Ch

ip)

Technologie

0

200

400

600

800

1000

1200

1400

90 nm 65 nm 45 nm 32 nm 22 nm 16 nm

Pow

er D

issi

pat

ion

[W]

(10

0 m

m²

Ch

ip)

Technology

Trends cont‘dTrends cont‘d

Dynamic Power Dissipation

Power Dissipation by Leakage currents

Source: S. Borkar (Intel), ‘05


Recap: Transistor GeometricsRecap: Transistor Geometrics

n+ n+

p-type body

polysilicongate

Gate length

L

Source: Rabaey,“Digital Integrated Circuits”,1995

Gate-widthW

SiO2 gate oxide(good insulator, eox = 3.9

tox – thickness of oxide layer

tox


Gate

Vgs < Vth

DrainSource

Gate

Vgs > Vth

DrainSource

Subthreshold LeakageSubthreshold Leakage Threshold Voltage

Transistor characteristic

If: „Gate-Source“-Voltage Vgs higher than Vth

Channel under Gate Current between Drain and Source

If: Vgs lower than Vth

(ideal) No current

Subthreshold leakage Isub

Leakage between Drain and Source when Vgs < Vth

Based on: Short Channels Diffusion Thermionic Emission

Source Drain

Gate

Isub

high Concentration

Low concentration

Diffusion


Subthreshold Leakage cont’dSubthreshold Leakage cont’d

0 Vth’ Vth

Lo

g (

Dra

in c

urr

en

t)

Gate voltage

Short-channel device

Isub

Source: Agarwal, 2007

Transistor is conducting

NMOS-Transistor


0

4

8

12

16

20

0 20 40 60 80 100 120

Nor

mal

ized

I sub

/µm

Temperature (°C)

Temperature dependenceTemperature dependence

IOFF at 1100C

Isub at 250C

130nm6x70

nm

16x

Based on Thermionic Emission: subthreshold leakage Isub increases with temperature

Source: Chatterjee, Intel-labs


GateGateoxide

DrainSource

Tox

Gate Oxide LeakageGate Oxide Leakage

Igate

Tunneling effect Electromagnetic wave strike at barrier:

Reflection + Intrusion into barrier

If thickness is small enough:

Wave interfuse barrier partially: (Electrons tunnel through Barrier)

Gate oxide leakage Igate

In Nanometer-Transistors, where Tox<

2 nm

Electrons tunnel through gate oxide

Leakage current

0

x

Potential Energy

0

x

Potential Energy

Tox


Gate Oxide Thickness at 45 nmGate Oxide Thickness at 45 nm


Gate Oxide Leakage cont’dGate Oxide Leakage cont’d

Components of Gate Oxide Leakage: Tunneling currents through overlap regions (gate-drain Igso, gate-

source Igdo)

Tunneling currents into channel (gate-drain Igis, gate-source Igcd)

Tunneling currents between gate and bulk (Igb)

Drain

Gate

SourceIgb

IgdoIgso IgcdIgcs

Bulk


Gate

DrainSource

Vds

Drain Induced Barrier Lowering (DIBL)Drain Induced Barrier Lowering (DIBL)

Gate

DrainSource

Vds

Pot

entia

l

Electrons have to overcome potential barrier to enter the channel Ideal: Potential barrier is only controlled by gate voltage

Changed by gate voltage

Vgs < Vth Vgs > Vth

Height of curve = Potential barrier


Drain Induced Barrier Lowering cont’dDrain Induced Barrier Lowering cont’d

At short channel transistors potential barrier is also affected by drain voltage

If Vds = VDD Transistors can start to conduct even if Vgs < Vth

Short-channel transistor (L < 180 nm)Long-channel transistor (L > 2 µm)

Vds = Vth

Vds = VDD

Gate

DrainSource

Vds

Vds = Vth

Vds = VDD

G

DS

Vds

Lowering of potential barrier


Gate

DrainSource

Further Leakage ComponentsFurther Leakage Components

Reverse bias pn junction conduction Ipn

Gate induced drain leakage IGIDL

Drain source punchthrough IPT

Hot carrier injection IHCI IHCI

Ipt

IGIDL

Ipn


Leakage DependenciesLeakage Dependencies

Leakage depends on: Gate Width (Isub, Igate)

Gate Length (Isub)

Gate Oxide Thickness (Igate)

Threshold Voltage (Isub)

Temperature (Isub)

Input state (Igate)


System

Algorithm

Architecture

Gate

Transistor

T

T

+

ST1

ALU

ME

M

ME

MMP3

Savings Speed Error

> 70 %

40-70 %

25-40 %

15-25 %

10-15 %

Seconds

Minute

Minutes

Hour

Hours

> 50 %

25-50 %

15-30 %

10-20 %

5-10 %

Recap: Levels of Recap: Levels of OptimizationOptimization

nach Massoud Pedram


Approaches to Reduce LeakageApproaches to Reduce Leakage

Idle states (passive)

Components have nothing to do

Active states

Components are working

Approaches for different states


Approaches on Technology LevelApproaches on Technology Level

Retrograde well Different Concentration of dopant

(implanted) inside the substrat Lowest concentration: near the

channel Lower subthreshold leakage

Highest concentration: near the bulk connection Reduced possibility for punch-

through

Gate

Source

retrograde well

Drain

p--

p--p-- p-

n+n+


Approaches on Technology Level cont’dApproaches on Technology Level cont’d

Halo Implants High doped regions near

source and drain areas Reduced Drain Induced

Barrier Lowering

Offset Spacer Silicon nitride placed beside

gate area Reduced overlap regions Reduced gate leakage

through overlap regions But: Increased channel

resistance

Gate

Source

Halo Implants

Offset Spacer

Drainp--p-- p-

n+n+


Power & Delay Dependence of VPower & Delay Dependence of Vthth

K

L DDd

DD TH

k Q k' C Vt

I (W / L ) (V V )

w.o. gate leakage

20

0

10THV

T St L DD DDCLK

WP p f C V I V

W

Source: Sakurai, ‘01


30

35

40

45

50

55

0

40

80

120

160

0.25 0.27 0.29 0.31 0.33 0.35 0.37

Lea

kag

e -

I sub

[nA

]

Threshold Voltage VthNMOS [V]

Inverter (BPTM 65 nm)

30

35

40

45

50

55

0

40

80

120

160

0.25 0.27 0.29 0.31 0.33 0.35 0.37

Leak

age

-I s

ub[n

A]

Threshold Voltage VthNMOS [V]


Dea

ly [

ps]

Influence of Threshold Voltage VInfluence of Threshold Voltage Vthth

Threshold Voltage Vth:

Influence on sub-threshold leakage Isub

Influence on delay of logic gates

IsubDelay


25

30

35

40

45

50

0

40

80

120

160

1.4 1.6 1.7 1.8 2.0 2.2

Lea

kag

e -

I gat

e[n

A]

Gate oxide Thicknes Tox [nm]


25

30

35

40

45

50

0

40

80

120

160

1.4 1.6 1.7 1.8 2.0 2.2

Lea

kag

e -

I gat

e[n

A]

Gate oxide Thicknes Tox [nm]


Del

ay [p

s]

Influence of Gate Oxide Thickness TInfluence of Gate Oxide Thickness Toxox

Gate oxide Thickness Tox:

Influence on gate oxide leakage Igate

Influence on delay

IgateDelay


FF

FF

FF

FF

FF

FF

FF

FF

FF

CLK CLK CLK

Recap: Data PathsRecap: Data Paths

Data propagate through different data paths between registers (flipflops - FF)

Paths mostly differ in propagation delay times Frequency of clock signal (CLK) depends on path with longest delay

critical path

Paths

Path


Recap: SlackRecap: Slack

B

A

Y

C

time

all Inputs of G1arrived

G1 ready withevaluation

delay of G1

all inputs of G2arrived

Slack for G1

BA Y

C

G1G2


Dual-VDual-Vthth / Dual-T / Dual-Toxox

Two different gate types:

Gates consist of „low-Vth“- or „low-Tox“-transistors

Low threshold voltage or thin gate oxide layer For critical paths High leakage

Gates consist of „low-Vth“- or „low-Tox“-transistors

Low threshold voltage or thin gate oxide layer For critical paths High leakage

“LVT / LTO”-Gates

Gate consist of „high-Vth“- „high-Tox“-transistors

High threshold voltage or thick gate oxide layer For uncritical paths Low leakage

Gate consist of „high-Vth“- „high-Tox“-transistors

High threshold voltage or thick gate oxide layer For uncritical paths Low leakage

“HVT / HTO”-Gate

Leakage reduction at constant performance

(no level converter necessary)


Performance at different Dual-VPerformance at different Dual-Vthth

High VthLow Vth0.0

0.2

0.4

0.6

0.8

1.0

1.0V 0.9V 0.8V 0.7V 0.6V

Nor

mal

ized

Perf

orm

ance

Supply Voltage VDD

Measured at NAND2 BPTM 65nm Technology


High VthLow Vth0

20

40

60

80

1.0V 0.9V 0.8V 0.7V 0.6V

Sub-

Thre

shol

d Le

kage

[nA]

Supply Voltage VDD

Leakage ILeakage Isubsub at different Dual-V at different Dual-Vthth

Measured at NAND2 BPTM 65nm Technology


Dual-VDual-Vthth / Dual-T / Dual-Toxox Example Example

Critical Path

HVT- orHTO-Gates

LVT- or LTO-Gates


Dual-VDual-Vthth / Dual-T / Dual-Toxox at Transistor Level at Transistor Level

Better leakage reduction possible

Much higher effort in design phase

Uncritic

al path

Critical path

“low-Vth” or “low-Tox” transistors

“high-Vth” or “high-Tox” transistors


Simultaneous VSimultaneous Vtt, Size and V, Size and Vdddd Assignment Assignment

Leakage reduced through either increasing Vth or lowering VDD

Lowering Vdd also reduces dynamic power

Topological constraints on VDD assignment

Requires use of voltage level converters

Assign VDD first then

perform sizing/Vth

assignment

Topology BasedSlack Distribution

Change VDD ofGates with

Sufficient Slack

Begin

Delay MinimizeAll Paths

Sensitivity BasedSlack Distribution

Change Gates With Sufficient

Slack

P

EndSource: [Nguyen, et al., ISLPED03]


Stack EffectStack Effect

Transistor stack: at least two transistor from same type (NMOS or PMOS) in a row

Based on behavior of internal nodes:

The more transistors are non-conducting (off) the lower the leakage

Source: Roy, “Lecture”

0

2

4

6

8

10

1 2 3 4

Le

aka

ge

I su

b[n

A]

Transistors off in stack


Sleep TransistorsSleep Transistors

Idea: Insertion of additional transistors between logic block and supply lines

This transistors: connect with SLEEP-signal

If circuit has nothing to do: SLEEP signal is active: Stack effect

(additional off transistor in row to other)

If sleep transistors are High-Vth:

approach also called Multi-Threshold CMOS (MTCMOS)

Mostly insertion only of 1 Transistor

Low-Vth logic cells

Vss

Vdd

sleep

Virtual Vss

Virtual Vddsleep

Source: Kaijian Shi, Synopsys


Sleep Transistors: RealizationSleep Transistors: Realization

VDDGlobal VDD

VVDD1 domain

Ring style sleep transistor implementation

Sleep transistors are placed around each VVDD island

VVDD2 domain



Sleep Transistors: Realization cont’dSleep Transistors: Realization cont’d

Grid style sleep transistor implementation


Global VDD

VVDD2

VDDVVDD1

VVDD1

VVDD1

VVDD2

VVDD2

VDD network cross chip; VVDD networks in each gating domain

Sleep transistors are placed in grid connecting VDD and VVDDs


Sleep Transistors: ProblemsSleep Transistors: Problems

Sleep transistor can be modeled as resistor R In active mode (gate is working)

Current I through sleep transistor Voltage Vx drop over resistor Output voltage reduced to VDD-Vx

high-Vth

sleep transistorSLEEP

CMOSGatter / Block

VDD VDD

R I

CMOSGatter / Block

Vx = RI

VDD - Vx

Reduced Delay (of following blocks)

Current I is not leakage current!

I is discharging current of load capacitance


StackforcingStackforcing Simple method of using stack effect

Increasing stack by splitting transistors

Cin stays constant

Only one technology is needed

Area is (almost) the same

Drive strength (drain-source current) is reduced delay goes down

VDD

WP

VDD

WP/2

WP/2

WN/2

WN/2


Stackforcing cont’dStackforcing cont’d

Source: Narendra, et al., ISLPED01

Normalized Isub

Nor

mal

ized

del

ay

No Stackforcing


Input Vector Control (IVC)Input Vector Control (IVC)

Input vector Leakage Trans. off In3 In2 In1 [nA] in NMOS-Stack 0 0 0 0,1 TN3, TN2, TN1

0 0 1 0,2 TN3, TN2

0 1 0 0,2 TN3, TN1

0 1 1 1,9 TN3

1 0 0 0,2 TN2, TN1

1 0 1 1,3 TN2

1 1 0 1,2 TN1

1 1 1 9,4 -

In1

In3

In2

VDD

TN3

TN2

TN1

Leakage of gate depends on input vector


Every circuits is input vector with minimum leakage Idea: If design is in passive mode

SLEEP signal gets active Sleep vector is applied

Input Vector Control cont’dInput Vector Control cont’d

Logic CircuitMUX

Data

Sleep Vector

SLEEP


Pin ReorderingPin Reordering

Gate Leakage in stack depends on input vector Same logic input vector (amounts of ‘0’ and ‘1’ is equal) → can

result in different leakage If input probability is know reorder pins so that highest probable

state has minimum gate leakage

116.0 nA↑Igcs, Igso, Igcd, IgdoIgci, Igso, Igdo,

IgcdIgdo011

7.6 nA↓Igdo--110

58.7 nA→Igcs, Igso, Igcd, IgdoIgdo-101

10.3 nA↓-Igdo-100

42.8 nA↑-Igci, Igcs, Igdo,

IgcdIgdo010

65.9 nA→Igcs, Igso, Igcd, Igdo-Igdo001

Example|Igate,stack|T1T2T3Input vector[In3,In2,In1]

116.0 nA↑Igcs, Igso, Igcd, IgdoIgci, Igso, Igdo,

IgcdIgdo011

7.6 nA↓Igdo--110

58.7 nA→Igcs, Igso, Igcd, IgdoIgdo-101

10.3 nA↓-Igdo-100

42.8 nA↑-Igci, Igcs, Igdo,

IgcdIgdo010

65.9 nA→Igcs, Igso, Igcd, Igdo-Igdo001

Example|Igate,stack|T1T2T3Input vector[In3,In2,In1]

BPTM, 65 nm technology

T3

T2

T1

VDD

In3

In2

In1

Drain

Igcd

Igdo

IgcsIgso


Threshold voltage Vth depends on bulk voltage (Vbs)

As leakage (Isub) and delay depends on Vth

Delay and leakage (Isub) can be controlled over Vbs

VTCMOS: dynamic adjustment of frequency and Vth through back-

gate bias (=Vbs) control

5

8

1

2

3

4

5

-1,5 -0,5 0 0,5-1Back-gate Bias VBS [V]

leakage power

delay

norm

aliz

ed p

ower

norm

aliz

ed d

elay

Variable Threshold CMOS (VTCMOS)Variable Threshold CMOS (VTCMOS)


VTCMOS: VTCMOS: VVTHTH-hopping scheme-hopping scheme

Vth - controller

Frequency- controller

VDD

GND

VBSP1 VBSP

VBSP2

VBSH1

VBSH2 VBSH

Target ProcessorVth - Selector

fclk1 or fclk2

Power Control Block

Vth_high_enableVth_low_enable

Source: NOSE et al.: - VTH HOPPING SCHEME


Voltage islandsVoltage islands

VDD1(MP3- Decoder)

VDD3(ROM)

VDD2(Cache)

VDD4(Prozessor)

+_VDD2

+_

VD

D4

fclk

LkLkL

k

Lk

Lk+_

VDD1

+_VDD3

LevelkonverterLk Level converter

(Processor)


Comparison of ApproachesComparison of Approaches

Approach Level Mode Pros Cons

retrograde well Technologyactive / passive

↓Ipt Technology ++

Halo-Implants Technologyactive / passive

↓DIBL Technology ++

Offset spacer Technologyactive / passive

↓Igate ↑td, Technology ++

Sleep transistors Gate / System passive ↓↓ Isub ↑td +

IVC Algorithm passive ↓Igate, ↓Isub - +


Comparison of Approaches cont’dComparison of Approaches cont’dApproach Level Mode Pros Cons

DVTCMOS Transistor / Gateactive / passive

↓Isub Technology +

DTOCMOS Transistor / Gateactive / passive

↓Igate Technology +

Stack forcing Transistoractive / passive

↓Isub ↑td o

VTCMOS Systempassive / slow

↓Isub Routing +

DVS Systempassive / slow

↓Igate, ↓

Isub

- +

DVDD Gateactive / passive

↓Igate,

↓Isub

Converter, Routing

+

Voltage islands Architecturepassive / slow

↓Igate,

↓Isub

Converter +


Backup


VDD

Vint

Vgs,2

Vgs,1

Vds,1Vbs,1

T2

T1

Vds,2Vbs,2

Vint

Vgs,2

Vbs,2

Vth,2

Vds,2

Vds,1

Vint

Vth,1

Isub

Low impact

Isub

Stack EffectStack Effect

Micro transductors ’08 Low Leakage VLSI Design Dr.-Ing. Frank Sill Department of Electrical...

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Transcript of Micro transductors ’08 Low Leakage VLSI Design Dr.-Ing. Frank Sill Department of Electrical...