Micro Controller 8051- New

8/14/2019 Micro Controller 8051- New

1/114

Sunday, April 12, 2009 Munish Vashishath

Section 1

Microprocessors course

By: Munish Vashishath


2/114


Contents:

IntroductionBlock Diagram and Pin Description of the 8051

Registers

Some Simple Instructions

Structure of Assembly language and Runningan 8051 program

Memory mapping in 8051

8051 Flag bits and the PSW register

Addressing Modes

16-bit, BCD and Signed Arithmetic in 8051

Stack in the 8051

LOOP and JUMP Instructions

CALL Instructions

I/O Port Programming


3/114


Introduction

CPU

General-

Purpose

Micro-processor

RAM ROM I/O

Port

TimerSerial

COM

Port

Data Bus

Address Bus

General-Purpose Microprocessor System

CPU for Computers

No RAM, ROM, I/O on CPU chip itself

Example Intels x86, Motorolas 680x0

Many chips on mothers board

General-purpose microprocessor


4/114


RAM ROM

I/O

PortTimer

Serial

COM

PortMicrocontroller

CPU

A smaller computer

On-chip RAM, ROM, I/O ports...

Example Motorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X

A single chip

Microcontroller :


5/114


Microprocessor

CPU is stand-alone, RAM,

ROM, I/O, timer are separate

designer can decide on theamount of ROM, RAM and

I/O ports.

expansive

versatility

general-purpose

Microcontroller

CPU, RAM, ROM, I/O and

timer are all on a single chip

fix amount of on-chip ROM,RAM, I/O ports

for applications in which cost,

power and space are critical

single-purpose

Microprocessor vs. Microcontroller


6/114


Embedded system means the processor is embeddedinto that

application.

An embedded product uses a microprocessor or microcontroller to

do one taskonly.

In an embedded system, there is only one application software thatis typicallyburned into ROM.

Example printer, keyboard, video game player

Embedded System


7/114


1. meeting the computing needs of the task efficiently and cost

effectively

speed, the amount of ROM and RAM, the number of I/O ports

and timers, size, packaging, power consumption

easy to upgrade

cost per unit

2. availability of software development tools

assemblers, debuggers, C compilers, emulator, simulator,

technical support

3. wide availability and reliable sources of the microcontrollers.

Three criteria in Choosing a Microcontroller


8/114


8051 Features

4K ROM 128 Bytes RAM

Four 8 Bit I/O Ports

Two 16 Bit Timers

Serial Interface

64K external code memory space

64K external data memory space

Boolean Processor

210 bit-addressable locations

4usec multiply/divide instructions


9/114


Block Diagram

CPU

On-chip

RAM

On-chip

ROM for

program

code

4 I/O Ports

Timer 0

Serial

PortOSC

Interrupt

Control

External interrupts

Timer 1

Timer/Counter

Bus

Control

TxD RxDP0 P1 P2 P3

Address/Data

Counter

Inputs


10/114


Feature 8051 8052 8031

ROM (program space in bytes) 4K 8K 0K

RAM (bytes) 128 256 128Timers 2 3 2

I/O pins 32 32 32

Serial port 1 1 1

Interrupt sources 6 8 6

Comparison of the 8051 Family Members


11/114



12/114


Pin Description of the 8051PDIP/Cerdip

1

2345678910111213141516

17181920

40

393837363534333231302928272625

24232221

P1.0

P1.1P1.2P1.3P1.4P1.5P1.6P1.7RST

(RXD)P3.0(TXD)P3.1

(T0)P3.4(T1)P3.5

XTAL2XTAL1

GND

(INT0)P3.2

(INT1)P3.3

(RD)P3.7

(WR)P3.6

Vcc

P0.0(AD0)P0.1(AD1)P0.2(AD2

)P0.3(AD3)P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)

EA/VPPALE/PROG

PSENP2.7(A15)P2.6(A14

)P2.5(A13

)P2.4(A12

)P2.3(A11)P2.2(A10)P2.1(A9)P2.0(A8)

8051

(8031)


13/114


Pins of 8051 1/4

Vcc pin 40

Vcc provides supply voltage to the chip.

The voltage source is +5V.

GND pin 20 ground

XTAL1 and XTAL2 pins 19,18

These 2 pins provide external clock.

Way 1 using a quartz crystal oscillator

Way 2 using a TTL oscillator

Example shows the relationship between XTAL and the

machine cycle.


14/114


Pins of 8051 2/4 RST pin 9 reset

It is an input pin and is active high normally low .

The high pulse must be high at least 2 machine cycles.

It is a power-on reset.

Upon applying a high pulse to RST, the microcontroller will

reset and all values in registers will be lost.

Reset values of some 8051 registers

Way 1 Power-on reset circuit

Way 2 Power-on reset with debounce


15/114


Pins of 8051 3/4 /EA pin 31 external access

There is no on-chip ROM in 8031 and 8032 .

The /EA pin is connected to GND to indicate the

code is stored externally./PSEN ALE are used for external ROM.

For 8051, /EA pin is connected to Vcc.

/ means active low.

/PSEN pin 29 program store enable

This is an output pin and is connected to the OE pinof the ROM.


16/114


Pins of 8051 4/4 ALE pin 30 address latch enable

It is an output pin and is active high.

8051 port 0 provides both address and data.

The ALE pin is used for de-multiplexing the addressand data by connecting to the G pin of the 74LS373latch.

I/O port pins

The four ports P0, P1, P2, and P3.Each port uses 8 pins.

All I/O pins are bi-directional.


17/114


XTAL Connection to 8051

C2

30pF

C1

30pF

XTAL2

XTAL1

GND

Using a quartz crystal oscillator

We can observe the frequency on the XTAL2 pin.


18/114


XTAL Connection to an External Clock Source

N

C

EXTERNALOSCILLATOR

SIGNAL

XTAL2

XTAL1

GND

Using a TTL oscillator

XTAL2 is unconnected.


19/114


Example :

Find the machine cycle for

(a) XTAL = 11.0592 MHz

(b) XTAL = 16 MHz.

Solution:

(a) 11.0592 MHz / 12 = 921.6 kHz;

machine cycle = 1 / 921.6 kHz = 1.085 s

(b) 16 MHz / 12 = 1.333 MHz;machine cycle = 1 / 1.333 MHz = 0.75 s


20/114


RESET Value of Some 8051 Registers:

0000DPTR

0007SP

0000PSW

0000B

0000ACC

0000PC

Reset ValueRegister

RAM are all zero.


21/114


Power-On RESET Circuit

30 pF

30 pF

8.2 K

10 uF

+

Vcc

11.0592 MHz

EA/VPPX1

X2

RST

31

19

18

9

i h b


22/114


Power-On RESET with Debounce

EA/VPP

X1

X2RST

Vcc

10 uF

8.2 K

30 pF

9

31


23/114


Pins of I/O Port

The 8051 has four I/O ports

Port 0 pins 32-39 P0 P0.0 P0.7

Port 1 pins 1-8 P1 P1.0 P1.7

Port 2 pins 21-28 P2 P2.0 P2.7

Port 3 pins 10-17 P3 P3.0 P3.7

Each port has 8 pins.

Named P0.X X=0,1,...,7 , P1.X, P2.X, P3.X

Ex P0.0 is the bit 0 LSB of P0

Ex P0.7 is the bit 7 MSB of P0

These 8 bits form a byte.

Each port can be used as input or output (bi-direction).


24/114


Registers

A

B

R0

R1

R3

R4

R2

R5

R7

R6

DPH DPL

PC

DPTR

PC

Some 8051 16-bit Register

Some 8-bitt Registers of

the 8051


25/114


26/114


Memory Organization

Separate memory for code & data

Internal(4K) and/or external (64K) ROM for code

On-chip RAM: General Purpose Register

Bit-addressable storage

Register banks

Special Function Registers

I/O ports are memory mapped directly to SFR RAM

locations

Stack resides within internal RAM


27/114


RAM memory space allocation in the 8051

7FH

30H

2FH

20H

1FH

17H

10H

0FH

07H

08H

18H

00HRegister Bank 0

Stack) Register Bank 1)

Register Bank 2

Register Bank 3

Bit-Addressable RAM

Scratch pad RAM/ General purpose

RAM


28/114


Program Memory


29/114


Lower 128 Bytes of Internal RAM


30/114


Internal Data Memory


31/114


Upper 128 Bytes of Internal RAM


32/114


Special Function Register


33/114


87Power ControlPCON

B0*I/O port LatchP3

A0*I/O port LatchP2

90*I/O port LatchP1

80*I/O port LatchP0

B8*Interrupt priorityIPA8*Interrupt Enable ControlIE

82Addressing External MemoryDPL

83Addressing External MemoryDPH

F0*ArithmeticB

E0*AccumulatorA

Internal Ram

address

FunctionName


34/114


8DTimer 1 High ByteTHI

8BTimer 1 Low ByteTL1

8CTimer 0 High ByteTHO

8ATimer 0 Low ByteTL0

88*Timer/Counter ControlTCON

89Timer/Counter Mode ControlTMOD

81Stack PointerSP

99Serial Port Data BufferSBUF

98*Serial Port ControlSCON

D0*Program status WordPSW

* Bit Addressable


35/114


Stack in the 8051

The register used to accessthe stack is called SP (stack

pointer) register.

The stack pointer in the8051 is only 8 bits wide,which means that it can takevalue 00 to FFH. When8051 powered up, the SPregister contains value 07.

7FH

30H

2FH

20H

1FH

17H

10H

0FH

07H

08H

18H

00HRegister Bank 0


Register Bank 2

Register Bank 3

Bit-Addressable RAM

Scratch pad RAM


36/114


8051 Flag bits and the PSW register PSW Register

CY AC F0 RS1 OVRS0 P--

CYPSW.7Carry flag

ACPSW.6Auxiliary carry flag

--PSW.5Available to the user for general purpose

RS1PSW.4Register Bank selector bit 1

RS0PSW.3Register Bank selector bit 0

OVPSW.2Overflow flag

--PSW.1User define bitPPSW.0Parity flag Set/Reset odd/even parity

RS1 RS0 Register Bank Address

0 0 0 00H-07H

0 1 1 08H-0FH

1 0 2 10H-17H

1 1 3 18H-1FH


37/114


MCS51 External R/W Operation


38/114


MCS51 Program Memory Access


39/114


40/114


Addressing Modes

Immediate Register

Direct

Register Indirect

Relative

Absolute

Long

Indexed


41/114


Immediate Addressing Mode

MOV A,#65HMOV A,#A

MOV R6,#65H

MOV DPTR,#2343H

MOV P1,#65H

Example :

Num EQU 30

MOV R0,Num

MOV DPTR,#data1

ORG 100H

data1: db IRAN


42/114


Register Addressing Mode

MOV Rn, A ;n=0,..,7

ADD A, Rn

MOV DPL, R6

MOV DPTR, A

MOV Rm, Rn


43/114


Direct Addressing Mode

Although the entire of 128 bytes of RAM can be accessed using directaddressing mode, it is most often used to access RAM loc. 30 7FH.

MOV R0, 40H

MOV 56H, A

MOV A, 4 ; MOV A, R4MOV 6, 2 ; copy R2 to R6

; MOV R6,R2 is invalid !

SFR register and their address

MOV 0E0H, #66H ; MOV A,#66H

MOV 0F0H, R2 ; MOV B, R2

MOV 80H,A ; MOV P1,A

R i t I di t Add i M d


44/114


Register Indirect Addressing Mode In this mode, register is used as a pointer to the data.

MOV A,@Ri ; move content of RAM loc.Where address is held by Ri into A

( i=0 or 1 )MOV @R1,B

In other word, the content of register R0 or R1 is sources or target in MOV, ADD and SUBBinsructions.

Example:

Write a program to copy a block of 10 bytes from RAM location sterting at 37h to RAM

location starting at 59h.

Solution:

MOV R0,#37h ; source pointer

MOV R1,#59h ; dest pointer

MOV R2,#10 ; counter

L1: MOV A,@R0

MOV @R1,A

INC R0

INC R1

DJNZ R2,L1

jump

R l i Ab l & L


45/114


Relative, Absolute, & Long

AddressingUsed only with jump and call instructions:

SJMP

ACALL,AJMP

LCALL,LJMP


46/114


47/114


Some Simple Instructions

MOV dest,source ; dest = source

MOV A,#72H ;A=72H

MOV A, #r ;A=r OR 72H

MOV R4,#62H ;R4=62H

MOV B,0F9H ;B=the content of F9th byte of RAM

MOV DPTR,#7634H

MOV DPL,#34H

MOV DPH,#76H

MOV P1,A ;mov A to port 1

Note 1:MOV A,#72H MOV A,72H

After instruction MOV A,72H the content of 72th byte of RAM will replace in Accumulator.

8086 8051

MOV AL,72H MOV A,#72HMOV AL,r MOV A,#r

MOV BX,72H

MOV AL,[BX] MOV A,72H

Note 2:MOV A,R3 MOV A,3


48/114


ADD A, Source ;A=A+SOURCE

ADD A,#6 ;A=A+6

ADD A,R6 ;A=A+R6

ADD A,6 ;A=A+[6] or A=A+R6

ADD A,0F3H ;A=A+[0F3H]


49/114


SUBB A,source ;A=A-source-CY

SETB C ;CY=1

SUBB A,R5 ;A=A-R5-1

ADC A,source ;A=A+source+CY

SETB C ;CY=1

ADC A,R5 ;A=A+R5+1


50/114


51/114


SETB bit ; bit=1

CLR bit ; bit=0

SETB C ; CY=1

SETB P0.0 ;bit 0 from port 0 =1

SETB P3.7 ;bit 7 from port 3 =1

SETB ACC.2 ;bit 2 from ACCUMULATOR =1

SETB 05 ;set high D5 of RAM loc. 20h

Note:

CLR instruction is as same as SETB

i.e:

CLR C ;CY=0

But following instruction is only for CLR:

CLR A ;A=0

Bit Addressable

Page 359,360


52/114

RR RL RRC RLC A


53/114


RR RL RRC RLC A

EXAMPLE:

RR A

RR:

RRC:

RL:

RLC:


54/114


ANL - ORL XRL

Bitwise Logical Operations:

AND, OR, XOREXAMPLE:

MOV R5,#89H

ANL R5,#08H

CPL A ;1s complementExample:

MOV A,#55H ;A=01010101 B

L01: CPL A

MOV P1,A

ACALL DELAY

SJMP L01


55/114


Stack in the 8051 The register used to

access the stack is calledSP (stack pointer)register.

The stack pointer in the8051 is only 8 bits wide,which means that it cantake value 00 to FFH.When 8051 powered up,

the SP register containsvalue 07.

7FH

30H

2FH

20H

1FH

17H

10H

0FH

07H08H

18H

00HRegister Bank 0


Register Bank 2

Register Bank 3

Bit-Addressable RAM

Scratch pad RAM


56/114


Example:

MOV R6,#25H

MOV R1,#12H

MOV R4,#0F3H

PUSH 6

PUSH 1

PUSH 4

0BH

0AH

09H

08H

Start SP=07H

25

0BH

0AH

09H

08H

SP=08H

F3

12

25

0BH

0AH

09H

08H

SP=08H

12

25

0BH

0AH

09H

08H

SP=09H


57/114


LOOP and JUMP Instructions

Jump if bit=1 and clear bitJBC

Jump if bit=0JNB

Jump if bit=1JB

Jump if CY=0JNC

Jump if CY=1JC

Jump if byte/=#dataCJNE reg,#data

Jump if A/=byteCJNE A,byte

Decrement and jump if A/=0DJNZ

Jump if A/=0JNZ

Jump if A=0JZ

Conditional Jumps :

DJNZ:


58/114


DJNZ:

Write a program to clear ACC, then

add 3 to the accumulator ten time

Solution:

MOV A,#0

MOV R2,#10

AGAIN: ADD A,#03

DJNZ R2,AGAIN ;repeat until R2=0 (10 times)

MOV R5,A


59/114


60/114


CALL Instructions

Another control transfer instruction is the CALL instruction,

which is used to call a subroutine.

LCALL(long call)

This 3-byte instruction can be used to call subroutineslocated anywhere within the 64Kbyte address space

of the 8051.

ACALL (absolute call)

ACALL is 2-byte instruction. the target addressof the subroutine must be within 2Kbyte range.


61/114


Instructions that Affect Flag Bits:

Note: X can be 0 or 1


62/114


Example:

Write a program to copy a block of 10 bytes from RAM location

starting at 37h to RAM location starting at 59h.

Solution:

MOV R0,#37h ; source pointer

MOV R1,#59h ; dest pointer MOV R2,#10 ; counter

L1: MOV A,@R0

MOV @R1,A

INC R0INC R1

DJNZ R2,L1

St t f A bl l


63/114


Structure of Assembly language

and Running an 8051 program

ORG 0H

MOV R5,#25H

MOV R7,#34H

MOV A,#0

ADD A,R5

ADD A,#12H

HERE: SJMP HERE

END

EDITOR

PROGRAM

ASSEMBLER

PROGRAM

LINKER

PROGRAM

OH

PROGRAM

Myfile.asm

Myfile.obj

Other obj fileMyfile.lst

Myfile.abs

Myfile.hex


64/114


Example:

MOV A,#38H

ADD A,#2FH

38 00111000

+2F +00101111---- --------------

67 01100111

CY=0 AC=1 P=1

Example:

MOV A,#88H

ADD A,#93H

88 10001000

+93 +10010011

---- --------------

11B 00011011

CY=1 AC=0 P=0

Example:

MOV A,#9CH

ADD A,#64H

9C 10011100

+64 +01100100

---- --------------

100 00000000

CY=1 AC=1 P=0

Example:


65/114


Example:

Assuming that ROM space starting at 250h contains Hello., write a program to transfer thebytes into RAM locations starting at 40h.

Solution:

ORG 0

MOV DPTR,#MYDATAMOV R0,#40H

L1: CLR A

MOVC A,@A+DPTR

JZ L2

MOV @R0,A

INC DPTR

INC R0

SJMP L1

L2: SJMP L2

;-------------------------------------

ORG 250H

MYDATA: DB Hello,0

END

Notice the NULL character ,0, as end of string and how we use the JZ instruction todetect that.

Example:


66/114


Example:

Write a program to get the x value from P1 and send x2 to P2, continuously .

Solution:

ORG 0

MOV DPTR, #TAB1MOV A,#0FFH

MOV P1,A

L01:

MOV A,P1

MOVC A,@A+DPTRMOV P2,A

SJMP L01

;----------------------------------------------------

ORG 300H

TAB1: DB 0,1,4,9,16,25,36,49,64,81

END

Timers /Counters Programming


67/114


Timers /Counters Programming

The 8051 has 2 timers/counters: timer/counter 0 andtimer/counter 1. They can be used as

The timer is used as a time delay generator.

The clock source is the internal crystal frequencyof the 8051.

An event counter.External input from input pin to count the number

of events on registers.

These clock pulses can represent the number of

people passing through an entrance, or the numberof wheel rotations, or any other event that can beconverted to pulses.


68/114


Timer

Set the initial value of registers

Start the timer and then the 8051 counts up.

Input from internal system clock (machine cycle)

When the registers equal to 0 and the 8051 sets abit to denote time out

toLCDP1

8051

TL0

TH0P2Set

Timer 0


69/114


Counter

Count the number of events

Show the number of events on registers

External input from T0 input pin (P3.4) for Counter 0

External input from T1 input pin (P3.5) for Counter 1

External input from Tx input pin.

We use Tx to denote T0 or T1.

T0

toLCD

P3.4

P1

8051

a switch

TL0

TH0


70/114


Basic Registers of the Timer

Both timer 0 and timer 1 are 16 bits wide. These registers stores

the time delay as a timer

the number of events as a counter

Timer 0: TH0 & TL0 Timer 0 high byte, timer 0 low byte

Timer 1: TH1 & TL1

Timer 1 high byte, timer 1 low byte

Each 16-bit timer can be accessed as two separate registers

of low byte and high byte.


71/114


Timer Registers

D15 D8D9D10D11D12D13D14 D7 D0D1D2D3D4D5D6

TH0 TL0

D15 D8D9D10D11D12D13D14 D7 D0D1D2D3D4D5D6

TH1 TL1

Timer 0

Timer 1

TCON Register:


72/114


TCON Register:

TF1: Timer 1 overflow flag.

TR1: Timer 1 run control bit. TF0: Timer 0 overflag. TR0: Timer 0 run control bit. IE1: External interrupt 1 edge flag.

IT1: External interrupt 1 type flag. IE0: External interrupt 0 edge flag. IT0: External interrupt 0 type flag. Bit Addressable as TCON.0 to TCON.7


73/114


TCON Register (1/2)

Timer control register: TMOD Upper nibble for timer/counter, lower nibble for interrupts

TR(run control bit)

TR0 for Timer/counter 0; TR1 for Timer/counter 1.

TR is set by programmer to turn timer/counter on/off.

TR=0: off (stop)

TR=1: on (start)

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Timer 1 Timer0 for Interrupt

(MSB) (LSB)


74/114


TCON Register (2/2)

TF(timer flag, control flag)

TF0 for timer/counter 0; TF1 for timer/counter 1.

TF is like a carry. Originally, TF=0. When TH-TL roll over

to 0000 from FFFFH, the TF is set to 1.

TF=0 : not reach

TF=1: reach

If we enable interrupt, TF=1 will trigger ISR.

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Timer 1 Timer0 for Interrupt

(MSB) (LSB)

Equivalent Instructions for the Timer


75/114


Control Register

CLR TCON.7=CLR TF1

SETB TCON.7=SETB TF1

CLR TCON.6=CLR TR1

SETB TCON.6=SETB TR1

For timer 1

CLR TCON.5=CLR TF0

SETB TCON.5=SETB TF0

CLR TCON.4=CLR TR0 SETB TCON.4=SETB TR0

For timer 0

TF1 IT0IE0IT1IE1TR0TF0TR1

TCON: Timer/Counter Control Register


76/114


TMOD Register

Timer mode register: TMOD

MOV TMOD,#21H

An 8-bit register

Set the usage mode for two timers

Set lower 4 bits for Timer 0 (Set to 0000 if not used)

Set upper 4 bits for Timer 1 (Set to 0000 if not used)

Not bit-addressable

GATE C/T M1 M0 GATE C/T M1 M0

Timer 1 Timer 0

(MSB) (LSB)


77/114


TMOD Register

GATE Gating control when set. Timer/counter is enabled only

while the INTx pin is high and the TRx control pin is set.

When cleared, the timer is enabled whenever the TRx

control bit is set.

C/T Timer or counter selected cleared for timer operation(input from internal system clock). Set for counter

operation (input from Tx input pin).

M1 Mode bit 1

M0 Mode bit 0

GATE C/T M1 M0 GATE C/T M1 M0

Timer 1 Timer 0

(MSB) (LSB)


78/114


C/T (Clock/Timer)

This bit is used to decide whether the

timer is used as a delay generator or an

event counter.

C/T = 0 : timer

C/T = 1 : counter

Gate


79/114


Every timer has a mean of starting and stopping.

GATE=0

Internal control The start and stop of the timer are controlled by way of

software.

Set/clear the TR for start/stop timer.

GATE=1

External control

The hardware way of starting and stopping the timer by

software and an external source.

Timer/counter is enabled only while the INT pin is high

and the TR control pin is set (TR).

M1, M0


80/114


M0 and M1 select the timer mode for timers 0 & 1.

M1 M0 Mode Operating Mode

0 0 0 13-bit timer mode

8-bit THx + 5-bit TLx (x= 0 or 1)

0 1 1 16-bit timer mode8-bit THx + 8-bit TLx

1 0 2 8-bit auto reload

8-bit auto reload timer/counter;

THx holds a value which is to be reloaded into

TLx each time it overflows.

1 1 3 Split timer mode


81/114


Timer/Counter Control Logic

XTAL

oscillator12

TR0/1

INT1/0 Input Pin

C/T = 0

Gate

T1/0 Input PinC/T = 1Counter

Timer


82/114



83/114

Interrupt :


84/114


Interrupt Enable Register :


85/114


Interrupt Enable Register :

EA : Global enable/disable.

--- : Undefined.

ET2 :Enable Timer 2 interrupt (Reserved for Future Use).

ES :Enable Serial port interrupt.

ET1 :Enable Timer 1 overflow interrupt.

EX1 :Enable External 1 interrupt. ET0 : Enable Timer 0 overflow interrupt.

EX0 : Enable External 0 interrupt.


86/114



87/114



Port 1 pins 1-8

Port 1 is denoted by P1.

P1.0 ~ P1.7

We use P1 as examples to show the operations on ports.

P1 as an output port (i.e., write CPU data to the external pin)

P1 as an input port (i.e., read pin data into CPU bus)

A Pi f P t 1


88/114


A Pin of Port 1

8051 IC

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPUbus

M1

P1.Xpin

P1.X

TB1

TB2

P0.x

H d St t f I/O Pi


89/114


Hardware Structure of I/O Pin

Each pin of I/O ports

Internal CPU bus communicate with CPU

A D latch store the value of this pin

D latch is controlled by Write to latch

Write to latch 1 write data into the D latch 2 Tri-state buffer

TB1: controlled by Read pin

Read pin 1 really read the data present at the pin

TB2: controlled by Read latch

Read latch 1 read value from internal latch

A transistor M1 gate

Gate=0: open

Gate=1: close


90/114

W iti 1 t O t t Pi P1 X


91/114


Writing 1 to Output Pin P1.X

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPUbus

M1

P1.Xpin

P1.X

8051 IC

2. output pin is

Vcc1. write a 1 to the pin

1

0 output 1

TB1

TB2


92/114

P t 1 O t t W it t P t


93/114


Port 1 as Output Write to a Port

Send data to Port 1

MOV A,#55H

BACK: MOV P1,A

ACALL DELAY

CPL A

SJMP BACK

Let P1 toggle.

You can write to P1 directly.

R di I t P t L t h


94/114


Reading Input v.s. Port Latch

When reading ports, there are two possibilities

Read the status of the input pin. from external pin value

MOV A, PX

JNB P2.1, TARGET ; jump if P2.1 is not set

JB P2.1, TARGET ; jump if P2.1 is set

Figures C-11, C-12

Read the internal latch of the output port.

ANL P1, A ; P1 P1 AND A

ORL P1, A ; P1 P1 OR A

INC P1 ; increase P1 Figure C-17

Table C-6 Read-Modify-Write Instruction (or Table 8-5)

See Section 8.3

R di Hi h t I t Pi


95/114


Reading High at Input Pin

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pin

P1.X

8051 IC

2. MOV A,P1

external pin=High1. write a 1 to the pin MOV

P1,#0FFH

1

0

3. Read pin=1 Read latch=0

Write to latch=1

1

TB1

TB2

R di L t I t Pi


96/114


Reading Low at Input Pin

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pin

P1.X

8051 IC

2. MOV A,P1

external pin=Low1. write a 1 to the pin

MOV P1,#0FFH

1

0

3. Read pin=1 Read latch=0

Write to latch=1

0

TB1

TB2

Port 1 as Inp t Read from Port


97/114


Port 1 as Input Read from Port

In order to make P1 an input, the port must be programmed by writing 1 toall the bit.

MOV A,#0FFH ;A=11111111B

MOV P1,A ;make P1 an input port

BACK: MOV A,P1 ;get data from P0

MOV P2,A ;send data to P2

SJMP BACK

To be an input port, P0, P1, P2 and P3 have similar methods.

I i F R di I P


98/114


Instructions For Reading an Input Port

Copy status of pin P2.4 to CYMOV C,P2.4MOV C,PX.Y

Jump if pin P1.3 is highJB P1.3,TARGETJB PX.Y,..

Jump if pin P2.1 is lowJNB P2.1,TARGETJNB PX.Y,..

Bring into A the data at P2

pinsMOV A,P2MOV A,PX

DescriptionExamplesMnemonics

Following are instructions for reading external pins of ports:

Reading Latch


99/114


Reading Latch

Exclusive-or the Port 1 MOV P1,#55H ;P1=01010101

ORL P1,#0F0H ;P1=11110101

1. The read latch activates TB2 and bring the data from the Q latch into

CPU.

Read P1.0=0

2. CPU performs an operation.

This data is ORed with bit 1 of register A. Get 1.

3. The latch is modified.

D latch of P1.0 has value 1.

4. The result is written to the external pin.

External pin (pin 1: P1.0) has value 1.

Reading the Latch


100/114


Reading the Latch

D Q

Clk Q

Vcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU bus

M1

P1.X pin

P1.X

8051 IC

4. P1.X=12. CPU compute P1.X OR 1

0

0

1. Read pin=0 Read latch=1 Write to

latch=0 (Assume P1.X=0 initially)

1

TB1

TB2

3. write result to latch Read

pin=0 Read latch=0

Write to latch=1

1

0

Read modify write Feature


101/114


Read-modify-write Feature

Read-modify-write InstructionsTable C-6

This features combines 3 actions in a single

instruction

1. CPU reads the latch of the port

2. CPU perform the operation

3. Modifying the latch

4. Writing to the pin

Note that 8 pins of P1 work independently.

Port 1 as Input Read from latch


102/114


Port 1 as Input Read from latch

Exclusive-or the Port 1 MOV P1,#55H ;P1=01010101

AGAIN: XOR P1,#0FFH ;complement

ACALL DELAY

SJMP AGAIN

Note that the XOR of 55H and FFH gives AAH.

XOR of AAH and FFH gives 55H.

The instruction read the data in the latch (not from the pin).

The instruction result will put into the latch and the pin.

Read-Modify-Write Instructions


103/114


Read Modify Write Instructions

ExampleMnemonics

SETB P1.4SETB PX.Y

CLR P1.3CLR PX.YMOV P1.2,CMOV PX.Y,C

DJNZ P1,TARGETDJNZ PX, TARGET

INC P1INC

CPL P1.2CPL

JBC P1.1, TARGETJBC PX.Y, TARGET

XRL P1,AXRL

ORL P1,AORL

ANL P1,AANL

DEC P1DEC

Other Pins


104/114


Other Pins

P1, P2, and P3 have internal pull-up resisters.

P1, P2, and P3 are not open drain.

P0 has no internal pull-up resistors and does not

connects to Vcc inside the 8051.P0 is open drain.

Compare the figures of P1.X and P0.X.

However, for a programmer, it is the same to programP0, P1, P2 and P3.

All the ports upon RESET are configured as output.

A Pin of Port 0


105/114


A Pin of Port 0

8051 IC

D Q

Clk Q

Read latch

Read pin

Write to latch

Internal CPUbus

M1

P0.XpinP1.X

TB1

TB2

P1.x

Port 0 pins 32 39


106/114


Port 0 pins 32-39

P0 is an open drain.Open drain is a term used for MOS chips in the

same way that open collector is used for TTLchips.

When P0 is used for simple data I/O we must connectit to external pull-up resistors.

Each pin of P0 must be connected externally to a10K ohm pull-up resistor.

With external pull-up resistors connected uponreset, port 0 is configured as an output port.


107/114

Dual Role of Port 0


108/114


Dual Role of Port 0

When connecting an 8051/8031 to an external memory, the 8051uses ports to send addresses and read instructions.

8031 is capable of accessing 64K bytes of external memory.

16-bit address P0 provides both address A0-A7, P2 provides

address A8-A15. Also, P0 provides data lines D0-D7.

When P0 is used for address/data multiplexing, it is connected to the

74LS373 to latch the address.

There is no need for external pull-up resistors as shown in

Chapter 14.

74LS373


109/114


74LS373

D

74LS373ALE

P0.0

P0.7

PSEN

A0

A7

D0

D7

P2.0

P2.7

A8

A15

OE

OC

EA

G

8051 ROM

Reading ROM (1/2)


110/114


D

74LS373ALE

P0.0

P0.7

PSEN

A0

A7

D0

D7

P2.0

P2.7

A8

A12

OEOC

EA

G

8051 ROM

1. Send address to

ROM

2. 74373 latches the

address and send to

ROM

Address

Reading ROM (2/2)


111/114


Reading ROM (2/2)

D

74LS373ALE

P0.0

P0.7

PSEN

A0

A7

D0

D7

P2.0

P2.7

A8

A12

OE

OC

EA

G

8051 ROM

2. 74373 latches the

address and send to

ROM

Address

3. ROM send the

instruction back


112/114

Port 2 pins 21-28


113/114


Port 2 pins 21-28

Port 2 does not need any pull-up resistors sinceit already has pull-up resistors internally.

In an 8031-based system, P2 are used to

provide address A8-A15.

Port 3 pins 10-17


114/114

Port 3 pins 10 17

Port 3 does not need any pull-up resistors since it alreadyhas pull-up resistors internally.

Although port 3 is configured as an output port upon reset,

this is not the way it is most commonly used.

Port 3 has the additional function of providing signals. Serial communications signal RxD, TxD.

External interrupt /INT0, /INT1

Timer/counter T0, T1

External memory accesses in 8031-based system

/WR, /RD s

Micro Controller 8051- New

Documents

Transcript of Micro Controller 8051- New