Micro controller-8051

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Tutorial of 8051

Transcript of Micro controller-8051

  • 1.Microcontroller 8051

2. CONTENTS:

  • Introduction
  • Block Diagram andPin Description of the 8051
  • Registers
  • Memory mapping in 8051
  • Stack in the 8051
  • I/O Port Programming
  • Timer

3.

  • meeting the computing needs of the task efficiently and cost effectively
    • speed, the amount of ROM and RAM, the number of I/O ports and timers, size, packaging, power consumption
    • easy to upgrade
    • cost per unit
  • availability of software development tools
    • assemblers, debuggers, C compilers, emulator, simulator, technical support
  • wide availability and reliable sources of the microcontrollers .

Introduction : Three criteria in Choosing a Microcontroller: 4. 8 bit controllers more requirements 5. Embedded System : 6. Development process Fall 2004 Embedded Systems Planning of tasks & interactions edit taskcode1.A51 taskcode2.c Assembler C-compiler misc.LIB Linker/Locator Burn in EPROM Download to board Revise ! Debugging ??? 7. 8051 Microcontroller Kit Layout 8. General Purpose Microprocessor v/s Microcontroller 9. Block Diagram : 8051 10. Block Diagram CPU On-chip RAM On-chip ROM for program code 4 I/O Ports Timer 0 Serial Port OSC Interrupt Control External interrupts Timer 1 Timer/Counter Bus Control TxDRxD P0 P1 P2 P3 Address/Data Counter Inputs PC Interface Lab. Stepper motor etc. Lab Delay Generation Labs 11. ROMLikeBrain OscillatorLikeHeart Data flow Like BloodFlow Ports like Hands/Legs Internal Data Bus Prepares thesequence of operations 12. 8051 Block Diagram 13. 14. 15. ROMLikeBrain OscillatorLikeHeart Data flow Like BloodFlow Ports like Hands/Legs Internal Data Bus Prepares thesequence of operations 16. Signal PinsFigure 8051 pinouts & Functions 17. 8051 Block Diagram 18. Fetch Cycle 19. 8051 Family State Sequence 20. 8051 Architecture: Salient features

  • 8 bit CPU with registers A and B
  • 16 bit Program Counterand data pointer DPTR
  • 8 bit Program Status Word
  • 8 bit Stack Pointer
  • Internal RAM 128 bytes
  • 4 Registers banks, each containing 8 Registers
  • 16 bytes, may be addressed at the bit level
  • 8 bytes of General Purpose memory
  • Internal ROM 4K
  • 32 I/O pins as 4 eight bit ports: P0-P3
  • 2 sixteen bit timer/counters: T0 and T1
  • Full duplex serial data receiver/transmitter: SBUF
  • Control registers: TCON, TMOD, SCON, PCON, IP AND IE
  • 2 external and 3 internal interrupt sources
  • Oscillator and clock circuits.

21. Pin Description of the 8051 22. 8051 Hardware Connections : Crystal Connection to 8051

  • Using a quartz crystal oscillator ( Frequency 11.0592 MHz)
  • We can observe the frequency on the XTAL2 pin.

Pin 18 Pin 20 Pin 19 C2 30pF C1 30pF XTAL2 XTAL1 GND 23. Pins of 8051

  • Vcc pin 40
    • Vcc provides supply voltage to the chip.
    • The voltage source is +5V.
  • GND pin 20 ground
  • XTAL1 and XTAL2 pins 19,18
  • RST pin 9 reset
    • It is an input pin and is active high normally low .
      • The high pulse must be high at least 2 machine cycles.
    • It is a power-on reset.
      • Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost.

24. Pins of 8051

  • / EA pin 31 external access
    • There is no on-chip ROM in 8031 and 8032 .
    • The /EA pin is connected to GND to indicate the code is stored externally.
    • /PSENALE are used for external ROM.
    • For 8051, /EA pin is connected to Vcc.
    • / means active low.
  • /PSEN pin 29 program store enable
    • This is an output pin and is connected to the OE pin of the ROM.

25. Pins of 8051

  • ALE pin 30 address latch enable
    • It is an output pin and is active high.
    • 8051 port 0 provides both address and data.
    • The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.
  • I/O port pins
    • The four ports P0, P1, P2, and P3.
    • Each port uses 8 pins.
    • All I/O pins are bi-directional .

26. Pins of I/O Port

  • The 8051 has four I/O ports
    • Port 0 pins 32-39 P0 P0.0 P0.7
    • Port 1 pins 1-8 P1 P1.0 P1.7
    • Port 2 pins 21-28 P2 P2.0 P2.7
    • Port 3 pins 10-17 P3 P3.0 P3.7
    • Each port has 8 pins.
      • Named P0.X X=0,1,...,7 , P1.X, P2.X, P3.X
      • Ex P0.0 is the bit 0 LSB of P0
      • Ex P0.7 is the bit 7 MSB of P0
      • These 8 bits form a byte.
  • Each port can be used as input or output (bi-direction).

27. Power-On RESET Circuit 30 pF 30 pF 8.2 K 10 uF + Vcc 11.0592 MHz EA/VPP X1 X2 RST 31 19 18 9 28. Hardware Structure of I/O Pin

  • Each pin of I/O ports
    • Internal CPU bus communicate with CPU
    • A D latch store the value of this pin
      • D latch is controlled by Write to latch
        • Write to latch 1 write data into the D latch
    • 2 Tri-state buffer
      • TB1: controlled by Read pin
        • Read pin 1 really read the data present at the pin
      • TB2: controlled by Read latch
        • Read latch 1 read value from internal latch
    • A transistor M1 gate
      • Gate=0: open
      • Gate=1: close

29. P89V51 RD2 :Electrical Specs.( Threshold Voltages) 30. 31. P89V51RD2 : Timing Specs. 32. A Pin of Port 1 8051 IC P0.x D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.XTB1 TB2 33. Writing 1 to Output Pin P1.X 8051 IC 2. output pin is Vcc 1. write a 1 to the pin 1 0 output 1 TB1 TB2 D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X 34. Writing 0 to Output Pin P1.X 8051 IC 2. output pin is ground 1. write a 0 to the pin 0 1 output 0 TB1 TB2 D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X 35. Reading High at Input Pin 8051 IC 2. MOV A,P1external pin=High

  • write a 1 to the pin MOV P1,#0FFH

1 0 3. Read pin=1 Read latch=0 Write to latch=1 1 TB1 TB2 D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X 36. Reading Low at Input Pin 8051 IC 2. MOV A,P1 external pin=Low

  • write a 1 to the pin
  • MOV P1,#0FFH

1 0 3 . Read pin=1 Read latch=0 Write to latch=1 0 TB1 TB2 D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X 37. You can not Get Logic 1 with Heavy Load and Weak Pull-up 38. Is it too much? - its the beginning - LOAD LOADING EFFECT ( SOURCE IS IN PROBLEM 39. A Pin of Port 0 8051 IC P1.x D Q Clk Q Read latch Read pin Write to latch Internal CPU bus M1 P0.X pin P1.XTB1 TB2 40. Port 0 with Pull-Up Resistors P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 DS5000 8751 8951 Vcc 10 K Port 0 41. Address Lines Bi-Directional Data Lines 42. Instruction: MOV A,# 3CH 74 3C Data5Ch is in Flash Memory 43. Instruction: MOV A,3CH Data is7F hex At RAM Address 3C hex - -ACC data will be7F h E5 3C 44. 85 80 A0 Instruction: MOV p2,p0 Mov address, address 85 45. Port 3 Alternate Functions 46. 8051 PROG. MEMORY 47. 8051 DATA MEMORY 48. Registers of 8051 49.

  • RAM memory space allocation in the 8051

7FH 30H 2FH 20H 1FH 17H 10H 0FH 07H 08H 18H 00H Register Bank 0 (Stack)Register Bank 1Register Bank 2 Register Bank 3 Bit-Addressable RAM Scratch pad RAM 50. Address Modes

  • Bit-Oriented Data Transfer transfers between individual bits.
  • SFRs with addresses ending in 0 or 8 are bit-addressable. (80, 88, 90, 98, etc)
  • Carry flag (C) (bit 7 in the PSW) is used as a single-bit accumulator
  • RAM bits in addresses 20-2F are bit addressable
  • Examples of bit transfe