Mgit Multi Level

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EEE Dept. CBIT, HyderabadEEE Dept. CBIT, Hyderabad3/5/2013 1

Over View ofMulti level inverters

By

Dr.K.KrishnaveniProfessor and Head

Dept. of EEE ,CBIT


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EEE Dept. CBIT, HyderabadEEE Dept. CBIT, Hyderabad

OUTLINE

IntroductionVarious types of multi level Inverters

--Diode clamped

--Capacitor clamped--Cascaded

Switching logic in multilevel invertersComparison

Single phase H-bridge(special case)ApplicationsConclusion

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Introduction

Wave forms of practical inverters are non-sinusoidal & contain

certain number of harmonics.

For low and medium power applications square wave or quasisquare wave voltage may be acceptable.

But for high power applications, sinusoidal wave forms withlow distortion are required.

Harmonic contents present in the output of a dc-ac inverter can

be eliminated by employing a filtering circuit or by employingPWM technique.


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Use of filters has the disadvantage of large size and cost,

PWM technique reduces the filter requirement to minimum orzero depending on the type of application.

Traditional two-level PWM Inverter have some drawbacks,namely

1.More switching losses.2.Intro.. of large amount of higher order harmonics.

3.large dv/dt rating.

4.Common mode voltages.

5.Problem of voltage sharing series connected devices.

6.Requirement of switches with very low turn-on and

turn-off times.

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To overcome the mentioned problems Multi-level Inverterscan be employed.

In addition to the above they offer the advantage of less

switching stress on the device for high voltage, high power

applications with reduced harmonic content at low switching

frequencies.

This seminar presents the basic description of 2-level,3-level

and 5-level inverters (and also presents the methodology for

switching loss calculations).

Modulation technique for 2,3,5 level Inverters & finally

comparison will be shown for the topologies on the basis of

switching losses &THD at different switching frequencies.


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Switching circuits of Multi level Inverters

One phase leg of an inverter with (a) two levels, (b) three levels,

and (c) n levels

.


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Switching circuits of Multi level Inverters

Output voltage profile of (a) 2-level, (b) 3-level, and (c) 5-level

inverter.


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Basics of two-level Inverters It is the most widely used topology in various low and medium

power applications. The full-bridge configuration of three-phase VSI is shown in the

below figure.

Figure 1: Three-phase two-level inverter.


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The switching logic to obtain the output voltage for a 120

degrees mode of operation is shown in below table


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This topology can be used at very high switching frequencies to

obtain low THD by using PWM technique.

Disadvantages in two-Level:

Power devices are to be connected in series-parallel to achieve a

large power capability, but they suffer from static and dynamicvoltage sharing problems in series & parallel connection of power

devices.

High rate of change of voltage due to synchronous commutation

of series devices.

In addition to above, high switching frequencies and harmonic

contents in inverter output voltage.


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Types of Multilevel Inverters

Commonly employed multilevel inverter topologies are:

1.Diode clamped2.Capacitor clamped

3.Cascaded Multi-Level

In all these topologies, the output voltage is synthesized for

several levels of input voltages obtained from several capacitorsconnected across the dc bus.

In capacitor clamped both real and reactive power can be

controlled, but it suffers from high switching losses due to real

power transfer & also it requires high no. of storage capacitors athigher levels.

Even a cascaded inverter uses a large no. of separate dc sources

for each of the bridges.


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Advantages/merits of diode clamped

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Hence the diode clamped topology is considered for the study, In

this all the devices are switched at fundamental frequency

resulting in low switching losses and high efficiency.

Another advantage of this topology are controlled reactive power

flow between source and load ,much better dynamic voltage

sharing among switching devices.

The control logic is simple ,especially for back- to- back inter tie

connections of two systems.

However, it requires a large number of clamping diodes for a

large number of output voltage levels. To produce an m-level output phase voltage, (m-1) switches are

required for each half phase leg, a total of (m-1) dc link

capacitors for energy storage and(m-1)*(m-2) clamping diodes for

each phase leg


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Three-Level Diode Clamped Multilevel Inverter (DCMLI)

Three-phase diode clamped three-level inverter (neutral pointclamped) topology is shown in below figure


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Capacitor clamped Multilevel Inverters

1. For voltage level Vdc/2 , switches S1and S2 need to be

turned on

2. For Vdc/2, switches S1and S2 need to be turned on3. For the 0 level, either pair(S1,S2 ) or(S2,S1 ) needs to

be turned on.4. D1and D1 diodes clamp the switch voltage to half the

level of dc voltage.


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Three-Level Diode Clamped Multilevel Inverter (DCMLI)

Three-phase diode clamped three-level inverter (neutral pointclamped) topology is shown in below figure


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The circuit consists of two dc link capacitors, 12 power

switches and six clamping diodes.

The middle point of the dc bus capacitor is known as neutral

point n.

The main feature of this topology is clamping diodes that clamp

the switch voltage to half of the dc bus voltage, reducing the

voltage stress of the switching device.

The output voltage has three different states: +, 0 and and thecorresponding output phase voltages are +Vdc/2, 0 and -Vdc/2.


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Switching states to synthesize the output voltages for phase Aare defined in below table


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Five-Level DCMLI


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Five-Level DCMLI


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Five-Level DCMLI


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It consists of 24 power switches and 36 clamping diodes. The DC

bus has four capacitors for a DC bus voltage Vdc.

The voltage across each capacitor is Vdc/4. Thus, the voltage stress across each device will be limited to

Vdc/4 through the clamping diode.

The below table shows the switching combinations andcorresponding output phase voltage levels where switching state

1 represents the switch is in on condition and state 0

indicates the switch is in off condition.

S i hi i f C i Cl d


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Switching Logic for Capacitor Clamped

C i Cl d M l il l I


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Capacitor Clamped Multilevel Inverters


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Cascaded multilevel inverter topology


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Switching Loss Calculations

Consider a single MOSFET switch connected across a dc

voltage of value Vdc.

Current through switch during on time is considered as Idc.


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Switching losses can be calculated from the turn-on and turn-off

characteristics of the devices. Instantaneous voltage and currentduring turn on time tc(on) are

V(t)=Vdc-(Vdc-Von)*(t/tc(on)); 0


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and energy dissipated during this interval is tc(on),

Ec,on=[{Vdc*Idc*(t/tc(on))}-(Vdc-Von)*(t2/tc(on)2)]dt 0 to tc(on)Ec,on=(Vdc*Idc*tc(on))/2-(Vdc-Von)*Idc*tc(on)/3

=(Vdc*Idcton)/6-(Von*Idc*tc(on))/3 (4)

and during turn-off transition, of t c(off), the current falls from

Idc to zero and the Von rises linearly to Vdc. The

instantaneous voltage and current during this period are

V(t)=Von+(Vdc-Von)/tc(off) (5)

i(t)=Idc-Idc/tc(off) (6)


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The instantaneous power dissipated during the interval tc(off) is

P(t)=V(t)*i(t)

={Von+(Vdc-Von)*(t/tc(off))}*{Idc-Idc*(t/tc(off))}

=Von*Idc+(Vdc-Von)*Idc*(t/tc(off))-Von*Idc*(t/tc(off))-(Vdc-Von)*Idc*(t2/tc(off)

2)

(7)Hence, the energy dissipated can be found as tc(off),

Ec,off=[Von*Idc+(Vdc-Von)*Idc*(t/tc(off))-Von*Idc*(t/tc(on))-(Vdc-

Von)*Idc*(t2/tc(off)2)]dt 0 tc(on)=(Vdc*Idc*tc(off))/6-(Von*Idc*tc(off))/3 (8)


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With a switching frequency of Fs, the average switching loss in

the switch during each transition of turn on and turn off can be

found as

Pc,on=(Vdc*Idc*tc(on)/Ts)/6+(Von*Idc*tc(on)/Ts)/3 (9)

Pc,off

=(Vdc

*Idc

*tc(off)

/Ts

)/6-(Von

*Idc

*tc(off)

/Ts

)/3 (10)

Hence, the average switching loss Psw in the switch is

Psw=(1/6)*Vdc*Idc*{tc(on)+tc(off)}/Ts+(1/3)*Von*Idc*{tc(on)+tc(off)}/Ts

(11)


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Eqn. (11) shows that the switching power loss in a semiconductor

switch varies linearly with the switching frequency and switchingtimes.

Therefore, with the devices having short switching times, it ispossible to operate them at a higher switching frequency thus

avoiding excessive switching power losses in the device .

M d l ti t h i


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Modulation technique

The modulation or controlled techniques are classifiedbelow

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SPWM technique is considered for the study in thisproject.

In SPWM technique a triangular carrier wave is comparedwith the sinusoidal reference wave at fundamental output

frequency.

The below figure shows the generation of switching pulsesfor power device S

1

of the two level inverter

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Figure 6: Pulse generation for two-level inverter (forswitch S1).

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The below figure shows the switching pulses for power

devices Sa1 and Sa2 of three level inverter

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EEE Dept. CBIT, HyderabadEEE Dept. CBIT, Hyderabad3/5/201302/11/2009 37


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The below figure shows the switching pulses for powerdevices Sa1,Sa2,Sa3 and Sa4 of five level inverter

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Simulation study of DCMLI with SPWM


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Simulation study of DCMLI with SPWM

Simulation studies have been performed on two, three and

five diode clamped three phase inverters

powergui

Discrete,= 5e-005

Total Harmonic

Distorsion2

signal THD

Total Harmonic

Distorsion1

signal THD

Total Harmonic

Distorsion

signal THD

Three-PhaseV-I Measurement 3

Vabc

IabcA

B

C

a

b

c

Subsystem

Series RLC Load 2

Series RLC Load 1

Series RLC Load

Scope3

Scope1

Scope

Product 2

Product 1

Product

Mean Value

InMean

Goto

voltages ]

Gain 1

-K-

Gain

-K-

From8

Von

From7

[s211]

From4

Iin

From3

Vin

From2

Iin

From

oltages ]

Display1

Display

Add

1Three -phase two-level inverter .

A

B

c

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powergui

Discrete,= 5e-005

Total Harmonic

Distorsion2

signal THD

Total Harmonic

Distorsion1

signal THD

Total Harmonic

Distorsion

signal THD

Three -phase three -level diode clamped inverter .

A

B

c

Three-Phase

V-I Measurement 3

Vabc

IabcA

B

C

a

bc

Subsystem

Series RLC Load 2

Series RLC Load 1

Series RLC Load

Scope3

Scope1

Scope

Product 2

Product 1

Product

Mean Value

InMean

Goto

[voltages ]

Gain 1

-K-

Gain

-K-

From8

Von

From7

s211

From4

Iin

From3

Vin

From2

Iin

From

oltages ]

Display1

Display

Add

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powergui

Discrete,= 5e-005

Total Harmonic

Distorsion2

signal THD

Total Harmonic

Distorsion1

signal THD

Total Harmonic

Distorsion

signal THD

Three -phase five -level diode clamped inverter .

C

b

A

Three-PhaseV-I Measurement 3

VabcIabc

A

B

C

a

b

c

Subsystem

Series RLC Load 2

Series RLC Load 1

Series RLC Load

Scope3Scope1

Scope

Product 2

Product 1

Product

Mean Value

InMean

Goto1

[currents]

Goto

[voltages ]

Gain 1

-K-

Gain

-K-

From8

Von

From7

s11

From4

Iin

From3

Vin

From2

Iin

From

oltages ]

Display1

Display

Add

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Out put voltage of two level inverter


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p g

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Frequency spectrum


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Frequency spectrum

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Pulse generation of two level inverter


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Pulse generation of two level inverter

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O/P voltage of three level inverter


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O/P voltage of three level inverter

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Frequency spectrum


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Frequency spectrum

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Pulse generation for three level


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Pulse generation for three level

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Output voltage of five level inverter


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Output voltage of five level inverter

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Harmonic order


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Harmonic order

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Pulse generation for five level


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Pulse generation for five level

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THD and Switching losses


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THD and Switching losses

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Variation of switching losses and THD with carrier frequency for the three-level

inverter.

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Variation of switching losses and THD with carrier frequency for a

five-level inverter.

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Variation of switching losses for two-level, threelevel and five-level

inverters with carrier frequency.

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Variation of percentage THD for two-level, threelevel and five-level

inverter with carrier frequency.

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References


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References

1.F. Z. Peng & J. S. 1. Lai, Multilevel Converters - A new breedof power converters,IEEE Transaction on Industry

Applications, Vol. 32, No. 3, May/June, 1996, pp. 509-517.

2. Jose Rodriguez, J. S. Lai & F. Z. Peng, Multilevel Inverters: ASurvey of Topologies, Controls, and Applications,IEEETransaction on Industrial Electronics, Vol. 49, No. 4, Aug

2002, pp. 724-738.

3. Mohan Ned, Undeland T.M. & Robbins W.P., PowerElectronics: Converters, Applications and Design, John Wileyand Sons, Second Edition, 2001.

4. G. Bhuvaneswari & Nagaraju, Multilevel Inverters AComparative Study,IETE Journal of Research, Vol. 51, No.2,Mar-Apr 2005, pp.

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