Meeting with STM HV-CMOSdarbo/BO/14-03-04_GD_HV-CMOS_STM.pdf · G. Darbo – INFN / Genova HV-CMOS...

HV-CMOS @ ST-Microelectronics G. Darbo – INFN / Genova Agrate, 4 March 2014 o

Meeting with STM HV-CMOS

!!

Giovanni Darbo INFN-‐Genova

Credits: Most of the material in these slides come from presenta<ons of: •  Ivan Peric – 9th “Trento” Workshop on Advanced Silicon Detectors – Genova, 26-‐28 Feb 2014 •  Malte Backhaus – 9th “Trento” Workshop on Advanced Silicon Detectors – Genova, 26-‐28 Feb 2014!

!!!!!!

G. Darbo – INFN / Genova Agrate, 4 March 2014 2 HV-CMOS @ ST-Microelectronics

HV-‐CMOS – The Original Idea (Monolithic Pixel)

Ideas: •  Use the standard (HV-‐)CMOS technologies to implement par<cle detectors •  Use a high voltage to deplete the sensor volume – charge collec<on by driX •  Original Implementa<on: CMOS electronics inside the deep n-‐well-‐collec<ng electrode •  “Smart diode” Ref.: I. Peric, Nucl. Instr. And Meth. A 582 (2007) 876–885

Deep n-‐well

PMOS NMOS

n-‐well

P-‐Substrate

Shallow p-‐well Shallow n-‐well

~60 V


Advantages of Monolithic Pixels Cost: •  Use of high-‐volume “standard” IC technologies to implement par<cle detectors •  Avoid the high-‐density bump-‐bonding (this is a cost and a bo^leneck)

Simplifica<on: •  Skip some of the produc<on steps •  Extend the use of wafer-‐probe test facili<es

Time: •  The detector can be built in less <me (no or small industrial produc<on

bo^lenecks)

Performance: •  Smaller pixel (i.e. be^er space resolu<on) possible •  Thinner detectors (important not to degrade the informa<on for the detectors

following the tracker).


HV-‐CMOS – The Original Idea (limita=ons) Limita<ons: •  The standard substrates are rela<vely low resis<ve (~20 Ωcm) •  The depleted region is up to ~15 µm thick – MIP signals are rela<vely weak ~1800 e •  The collec<on electrode is, at the same <me, the PMOS bulk – there is a strong

capaci<ve crosstalk from PMOS transistors to the detector input. •  General drawback of monolithic sensors: Complex in-‐pixel electronics leads to increased

detector capacitance (if everything in the same n-‐well) or to decreased electrode-‐/pixel-‐size ra<o (if separated n-‐well in the same pixel),

Deep n-‐well

PMOS NMOS

n-‐well

P-‐Substrate

Shallow p-‐well Shallow n-‐well

~60 V


HV-‐CMOS – The Hybrid Solu=on: CCPD

Hybrid detector with a “smart” HV-‐CMOS sensor and capaci<ve signal transmission to the readout ASIC (capaci<ve coupled pixel sensor – CCPD): •  Overcomes drawback of

monolithic detector: CCPD has small pixel and high electrode-‐/pixel-‐size ra<o

•  digital outputs of three pixels are mul<plexed to one pixel readout cell

•  HV-‐CMOS pixel contains an amplifier and a comparator

+

TOT = sub pixel address

Readout pixel – ATLAS FE-‐I4

Size: 50 µm x 250 µm

Size: 33 µm x 125 µm

Different logic 1 levels


CCPD Improvements: Triple Well

Detector structure improvements: •  Isolated PMOS •  Eliminates PMOS to sensor crosstalk, allows more freedom when pixel

electronics is designed

NMOS PMOS

3.3V

NMOS PMOS

Improvement:

Deep n-‐well Deep p-‐well

Shallow n-‐well


CCPD Improvements: Higher Ωcm Detector structure improvements: •  High resis<ve substrates •  Around 80 Ωcm looks op<mal

Deep-‐n-‐well

+-‐ +-‐ +-‐ +-‐ +-‐ +-‐ +-‐ +-‐

Depleted 12 µm

12 um

Primary signal 100% -‐ Signal collecWon: driX

Secondary signal ParWal signal collecWon: diffusion

+-‐ +-‐ +-‐ +-‐ +-‐ +-‐ Signal loss:

recombinaWon Signal loss

Deep-‐n-‐well

+-‐ +-‐ +-‐ +-‐ +-‐ +-‐ +-‐ +-‐

Depleted 24µm (@ equal bias voltage) Depleted 48µm (@ equal field, doubled bias voltage)

Primary signal 100% -‐ Signal collecWon: driX

+-‐ +-‐ +-‐ +-‐ +-‐ +-‐

ParWcle ParWcle

Uniformly doped substrate 20 Ω cm Signal 1800e (50%-‐50% driX-‐diffusion)

Uniformly doped substrate 80 Ω cm Signal: ~ 2700e-‐4500e (esWmaWon)

DepleWon ∝ √ ResisWvity

These processes are available within •  AMS and Lfoundry •  AMS agrees to use substrates of up to

3000 Ωcm (350 nm process – H35)


HV-CMOS Hybridization

The Wny HV2FEI4p1 prototype glued on the large FE-‐I4

HV2FEI4 2.2 × 4.4 mm2.

60 columns × 24rows

FE-I4

Ac<ve sensor HV-‐CMOS coupled to FE: •  Capaci<ve coupling through bump pads – dielectric layer very thin (<5 µm). •  Bump-‐pads are 18 µm diameter •  Cheap process to be developed

HV-‐CMOS need signal/power •  Engineered solu<on for module hybridiza<on: TSV?

Fig.: Prototype HV2FEI4 in AMS 180 nm process (H18)


HV2FEI4 Chip: Prototype Results

waveform). The response of the HitOR signal to a charge injection issued in the sensor by the USBpix system (a)as well as by a particle originating from a radioactive source (b) is shown.

pixel column0 10 20 30 40 50 60 70

pixe

l row

300

200

100

0

0

5000

10000

15000

20000

25000

30000

(a)

pixel column0 2 4 6 8 10 12

pixe

l row

180

170

160

150

140

130

0

5000

10000

15000

20000

25000

30000

(b)

Figure 7.5: Occupancy maps of the HV2FEI4 glued to an FE-I4 readout chip obtained with electrons from a90Srsource. The full FE-I4 map (a) with entries in the HV2FEI4 position and a zoom into the region of the HV2FEI4(b). 7

Full FE-I4 Hit Map HVCMOS Hit Map

The HV2FEI4 chip works coupled with FE-‐I4 •  Seen signal from sources • Measured detector efficiency at tests-‐beam: 85-‐90% efficiency seen. Must understand if is missing collected charge at the pixel edge or Wming / threshold tuning


HV2FEI4 Chip: Timing Response One of the issues of the chip is the <ming response •  Not yet understood if it is a poor design (nmos amplifier and discriminator) •  Need to understand & improve…

Divided C09 in two regions:Col 2-11, Row 165-187: region with normal pixelsCol 2-11, Row 190-210: Region with radiation hard pixels

Example plots from runs 110-122 (high statistics, Threshold = 928 mV)

sumtot_20_matchLvl1

Entries 61630Mean 7.199RMS 1.379

lvl10 2 4 6 8 10 12 14 160

2000

4000

6000

8000

10000

12000

14000

16000

18000

20000

22000

sumtot_20_matchLvl1


(a) C09

sumtot_21_matchLvl1


lvl10 2 4 6 8 10 12 14 160

5000

10000

15000

20000

25000

30000

35000

40000

45000

sumtot_21_matchLvl1


(b) ref. plane

Some late hits for C0917.12.2013 Lars Graber November 2013 PPS Testbeam 3 / 12

Hit Timing Resolution Hit Timing Resolution

1bin=25ns 1bin=25ns


HV2FEI4 Chip: Radiation Tolerance Chips have been irradiated and annealed up to 860 Mrad. •  The amplifier recovers up to 90% their original gain •  The design uses circular transistors to withstand radia<on damage!Irradiation Studies – Electronics

Tento Workshop 2014 - 28/02/2014 Malte Backhaus 17

! Decrease of Preamplifier gain with irradiation ! Annealing periods observable ! Parameter tuning recovers to 90 % gain after ~ 900 Mrad

0"

20"

40"

60"

80"

100"

0" 200" 400" 600" 800" 1000" 1200"

Rela,ve"Am

plifier"Gain"(%

)"

Dose"(Mrad)"

Pixel"One"Pixel"Two"Pixel"Three"Pixel"Four"

10 days @ 22 C annealing Adjustment of

settings

2 hour @ 70 C annealing

every 100 Mrad


ATLAS Upgrade Cost

Comment: •  2014-‐17 devoted to RD •  2018-‐20 pre-‐produc<on – 2018-‐22 produc<on

ATLAS%%PHASE%II%upgrade%(LS3)it#will#happen

it#might#happen

[MCHF] [MCHF]

1 New#Inner#Detector 131.500 26.0002 LAr#upgrades 32.124 15.0963 Tiles#upgrades 7.483 2.5174 Muon#spectrometer#upgrades 19.632 0.5005 TDAQ#upgrades 23.315 0.9006 Infrastructure#items 16.280 0.000

TOTAL 230.334 45.013

Cost Time Profile

CORE costing

Phase-1 uses TDR costings

Phase-2 uses LoI costings, and includes

options 0"

10"

20"

30"

40"

50"

60"

70"

2012" 2013" 2014" 2015" 2016" 2017" 2018" 2019" 2020" 2021" 2022"

CORE

%PAY

MEN

TS%[M

CHF]%

YEAR%

ATLAS"Phase5II"ATLAS"Phase5I"

ATLAS Cost Time Profile •  Phase I use TDR CosWngs •  Phase-‐II uses LoI cosWngs, and includes opWons

R&D

pre-‐ / -‐ producWon

Sensors are 30% of total


ATLAS Technology Inventory

AMS H35 •  Early prototypes done in this process. High breakdown voltages (> 100V) – somewhat elevated power consumpWon

AMS H18/IBM 7HV • Currently the main development process: HV2FEI4 and other chips

GF 130nm HV • HV process by GlobalFoundries in even smaller feature size, used to implement the HV2FEI4_GF. Actual experimental breakdown voltage is ~30 V before irradiaWon.

TowerJazz 180 nm High Resis<vity Process • Bonn tesWng. Possibly a process for monolithic detectors

IBM 130 nm with Triple Well (T3) Process •  aqracWve as it is the process of the FE-‐I4 readout chip, it is not an HV/HR process and therefore does not allow high bias voltages leading to rather low signal-‐to-‐noise values.

TSMC 65 nm process • Process selected for future FE-‐I5 chip. Probably not for CCPD


Documentations

Talks: •  Ivan Peric, HV-‐CMOS Overview, at 9th Trento Workshop, Genova 26-‐28/02/2014hqp://indico.cern.ch/event/273880/session/5/contribuWon/64/material/slides/1.pdf

• Malte Backhaus, RadiaWon-‐hard AcWve Pixel Sensors for HL-‐LHC Detector Upgrades based on HV-‐CMOS Technology, at 9th Trento Workshop, Genova 26-‐28/02/2014: hqp://indico.cern.ch/event/273880/session/5/contribuWon/65/material/slides/0.pdf

Papers •  I. Peric, A novel monolithic pixelated parWcle detector implemented in high-‐voltage cmos technology, Nucl. Instr. and Meth. in Phy. Res. A 582(2007)876-‐885.

•  I. Peric, C. Kreidl, and P. Fischer. Hybrid pixel detector based on capaciWve chip to chip signal-‐ transmission. Nucl. Instr. and Meth. in Phy. Res. A 617(2010)576-‐581.

•  I. Peric. AcWve pixel sensors in high-‐voltage CMOS technologies for ATLAS. JINST 7(08):C08002, 2012.


Conclusions

•  For ATLAS applica<on we consider CCPD a good alterna<ve to passive silicon sensors – we expect this to be cheaper, easier to build, thinner and with be^er space resolu<on.

•  Process needs few tens of volt breakdown, few ohm resistance (80 Ωcm looks somewhat op<mal), triple well makes easier CMOS design.

•  Produc<on cost is O[10M€] for Pixel only (it may increase if the strip tracker also adopt this technology)

•  3 years R&D before produc<on

•  Plan to prepare an EU program (under Horizon 2020) to cover part of the R&D effort (part covered by INFN). This should be a joint venture with industrial partners and may bring to produc<on if successful.!

!


BACKUP SLIDES


HV-CMOS Hybridization

The Wny HV2FEI4p1 prototype glued on the large FE-‐I4

Combine 3 pixels together to fit one FE-‐I4 pixel (50×250μm2), with HV-‐CMOS pixels encoded by pulse height. CCPD: CapaciWvely coupled to pixel IC.

HV2FEI4 2.2 × 4.4 mm2.

60 columns × 24rows

FE-I4

Ac<ve sensor HV-‐CMOS coupled to FE: •  Capaci<ve coupling through bump pads •  Bump-‐pads are 18µm diameter •  Dielectric layer very thin (<5µm?) and well

aligned (<few µm)

Large chips (>2x2 cm2) or Wafer-‐Wafer bonding •  Uniformity of the dielectric layer •  Cheap process to be developed

HV-‐CMOS need signal/power •  Engineered solu<on for

module hybridiza<on: TSV?

Prototype HV2FEI4 •  AMS 180 nm process (H18)

Meeting with STM HV-CMOSdarbo/BO/14-03-04_GD_HV-CMOS_STM.pdf · G. Darbo – INFN / Genova HV-CMOS...

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