MANAGING POWER SYSTEM FAULTS
Transcript of MANAGING POWER SYSTEM FAULTS
MANAGING POWER SYSTEM FAULTS
Xianyong Feng, PhD Center for Electromechanics The University of Texas at Austin November 14, 2017
Outline 1. Overview
2. Methodology
3. Case Studies
4. Conclusion
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Power System Fault Management
Detection
• Real-time monitoring • Detect electrical abnormal • Fault type identification (permanent or temporary)
Location
• Quickly and accurately locate fault • Minimize system impact
Isolation
• Open protective device • Minimize load interruption
Restoration
• Quick recovery • Restore interrupted loads to normal
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Power System Protection Research • DC distribution system protection
1. Ultra-fast dc fault protection [1], [2] 2. Power converter fault current handling [3] 3. Meshed dc network short-circuit fault current analysis [4]
• Protection study for AC system with high penetration DERs 1. Intelligent sensor development 2. Fault type identification 3. Fault location 4. Islanding detection 5. Optimal sensor placement
1. X. Feng, et.al., "Fault inductance based protection for DC distribution systems,“ Proc. IET 13th Conference on Development of Power System Protection, March 2016.
2. X. Feng, et.al., “A novel fault location method for DC distribution protection,” IEEE Trans. Industrial Applications, vol. 53, no. 3, pp. 1834-1840, May-June, 2017.
3. L. Qi, J. Pan, X. Huang, and X. Feng, “Solid state fault current limiting for dc distribution protection,” Proc. of Electric Ship Technology Symposium, Aug. 2017, pp. 187-191.
4. X. Feng, et.al., “Estimation of short circuit currents in mesh DC networks,” Proc. IEEE PES General Meeting, July 2014.
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CEM Approach - Protection Control Simulation Test: • New protection strategies are initially implemented in modeling
software and verified in numerical environment Tools: 1. Matlab / Simulink 2. PSCAD 3. ETAP 4. OpenDSS • The protection algorithms are implemented numerically • The performance is evaluated and optimized offline
Control Hardware-in-the-Loop (CHIL) Simulation Test:
• Protection strategies are implemented in hardware controllers • The controller is validated in the HIL simulation environment
Numerical simulation environment
Simulated circuit
Simulated control block 1
Simulated control block N
Control signal
Measured signal...
Opal-RT SimulatorHigh speed
communication link
Simulated Distribution Network in Opal-RTSimulated switching devices in NI PXI simulator
Control and Protection HardwareNI controllers IED
I/O or other comm. Interfaces
Control Center SCADA System
Sensors
Tertiary Controls
Distributed control...
Advanced protection strategies
PXIe Real-Time/FPGA HIL System
Procedure: 1. Model the circuit 2. Implement
control strategy in hardware
3. Configure the interface
4. Perform HIL tests
Power Hardware-in-the-Loop (PHIL) Simulation Test: • Implement the interface between HIL simulator and real power
systems
Real Hardware Test and Field Demonstration: The protection strategy test in real microgrid.
Benefits: 1. Obtain validated engineering data 2. Demonstrate system performance in the real operation environment
I/OsCurrent signalVoltage signal
HIL simulator ......
Simulated network
~Controlled
voltage source Current
measurement
Hardware InterfaceReal Hardware
Microgrid SystemPower
AmplifierActive Source
MV bus
Features: 1. Network model in simulator 2. Power converters and
active sources serve as power interface
3. NI FPGA simulator enables the fast PE switching
MW-scale Microgrid
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2
3
4
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DC Distribution System Protection
AC fault current
DC fault current
=
L L
=~ =
DC Power Supply
...
...
Fault 1 Fault 2
Fault 3...
L L...
...
DC distribution system example
DC protection challenges 1. No fault current zero-crossing 2. Lower line impedance 3. High di/dt 4. Power electrics device can not
tolerate high fault current 5. Fast capacitor discharge
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Fast DC Fault Location Algorithm
Inductance-based dc fault location* 1. Estimate fault inductance with local
measured v(t) and i(t) 2. Use estimated L to locate fault
=
L L L
Zone 1 (20 m)
Zone 2 (65 m)
Zone 4 (1.5 m)
=~ =
DC UPS
...
...
Fault 1 Fault 2
Fault 3...
L L L...380 VDC
Zone 3 (10.2 m)...
...
Equivalent inductance
Distance
level 1 level 2 level 3
L1
L2
L3
Line inductance distribution
RF
LRi
v
+
-
Equivalent fault circuit
*X. Feng, et.al., “A novel fault location method for dc distribution protection,” IEEE Trans. Industrial Applications, vol. 53, no. 3, May-June, 2017.
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Protection Control Prototype Protection strategy design
1. Online moving-window least square method 2. Algorithm on embedded controller
ADC ADC ADC
v (1) i (1) di/dt (1)
PRUs read data sequentially and store
them in memory
Main program executes the fault detection and
location routine
Locate fault?
YSend tripping
Request new data once
finishing the previous cycle
N
v i di/dt
Processor (AM3358)
7 analog inputs with A/D converters
65 digital I/Os
Fault detection and location routine
PRUs
Start
Go to next time intervalFault detected?
Yes
No
if k < M
No
Yes
k = 0
No
k = k + 1
Read in measurements v(k), i(k), and di/dt(k)
⎥⎥⎥⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢⎢⎢⎢
⎣
⎡
=
)()(
)1()1(
)0()0(
kikdtdi
idtdi
idtdi
A!! ⎥
⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢
⎣
⎡
=
)(
)1()0(
kv
vv
B!
⎥⎥⎥⎥⎥⎥⎥
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⎤
⎢⎢⎢⎢⎢⎢⎢
⎣
⎡
+−+−
+−+−
=
)()(
)2()2(
)1()1(
kikdtdi
MkiMkdtdi
MkiMkdtdi
A!! ⎥
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)2()1(
kv
MkvMkv
B!
( ) BAAARR
L TT
F
1−=⎥
⎦
⎤⎢⎣
⎡
+
if 0 < L < Lth
Yes
Send tripping signal
End
if t < Tmax
Yes
No
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24 V 47uF
Simulated DC network
Analog outputs: current/voltage signal
Fault detection and location algorithm
A/D converters
Breaker Trip
command
Microcontroller
Ethernet Opal-RT simulator
User interface
Breaker status wired back to Opal-RT simulator
Protection Algorithm Test
Control-HIL test 1. Opal-RT simulator ‒ Simulated a 380 V dc system ‒ Convert v(t)/i(t) to analog ‒ Read in breaker status
2. Embedded controller ‒ Read in v(t)/i(t) signals ‒ Execute prot. algorithm ‒ Send a trip signal for internal
fault
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Protection Algorithm Test
Hardware test 1. Low voltage circuit ‒ 7.07 mF capacitor is charged to
12 V ‒ Inductors are used to emulate
lines ‒ Short-circuit fault is created by
closing a breaker 2. Embedded controller ‒ Read in v(t), i(t), di/dt ‒ Execute prot. algorithm ‒ Send a trip signal for internal
fault
Capacitor (7.07 mF)
Inductor (6 µH)
12 V DC
+
-
Switch Line (6-12 µH)
EmaxCurrent sensor
Volta
ge
Cur
rent
Analog circuit of di/dtcalculation
Tripping signal
BeagleBoneBlack board with fault detection & location
Diagram
Test Circuit
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Protection Algorithm Test Results Control-HIL test results 1. L estimation error < 8.4% 2. Fault detection/location time < 0.7 ms
tripping signal
current signal
current signal
voltage signal
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Protection Algorithm Improvement
=
L L L
Zone 1 (20 m)
Zone 2 (65 m)
Zone 4 (1.5 m)
=~ =
DC UPS
...
...
Fault 1 Fault 2
Fault 3...
L L L...380 VDC
Zone 3 (10.2 m)...
...
Level 1 Level 2 Level 3
Level 4
Zonal boundary inductors
ΔL1ΔL2
ΔL3
Distance
level 1 level 2 level 3level 4
L1
L2
L3
L4
Equivalent inductance
Inserted ΔL1
Inserted ΔL2
Inserted ΔL3
No boundary inductor
Equivalent inductance
Distance
level 1 level 2 level 3
L1
L2
L3
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Result Summary 1. The prot. method uses local measurements only to
locate fault ‒ Detection and location time < 0.7 ms ‒ L estimation error in HIL test < 8.4% ‒ L estimation error in hardware test < 20%
2. The prot. Method accurately locates short-circuit faults if: ‒ Voltage measurement error < 0.5% ‒ Current measurement error < 1%
3. Boundary inductors improve prot. selectivity
• Ongoing work: 1. Protection algorithm test on real MV dc microgrid
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MVDC Shipboard System Protection
850 V 1.2 MW60 Hz 3-ph
850 V 0.8 MW60 Hz 3-ph
M
1.1 kV 2 MW200 Hz
==
1.15 kVdc/1.0 kVdc
60 HzLoads
60 H
z A
CD
istr
ibut
ion
60 H
z A
CD
istr
ibut
ion
400 HzLoads
==
1.15 kVdc/1.0 kVdc
60 HzLoads
400 HzLoads
MISSION LOAD
PMM
PGM
PGM PCM1-A
PCM1-A
IPNC
IPNC
PCM
==
==
1.15 kVdc
1.15 kVdc
60 HzLoads
PFN
RailgunPROPULSON LOAD
System Description 1. Two PGMs ‒ FCL in dc-dc converters
2. One propulsion load ‒ VFD + motor
3. One pulse load ‒ High di/dt
4. DC circuit breakers ‒ Isolate fault
5. Protection strategy* ‒ FCL + diff. protection
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*S. Strank, et. al., “Experimental test bed to de-risk the navy advanced development model,” Proc. of Electric Ship Technology Symposium, Arlington, VA, Aug. 2017, pp. 352-358.
MVDC Shipboard System Protection • Main results
1. Fault: 10-25 ms, 20 mΩ, on dc bus 2. Prot. strategy: FCL + diff. prot.
• Ongoing work 1. Validate the protection method on
real dc microgrid
==
==
CB1
CB2
Reactor 1
Reactor 2PGM 2
PGM 1
Load 1
Load 2
0.6 MW
1 MW
0.39 mH0.39 mH
0.39 mH0.39 mH
5 mF
5 mF 0.5 mF
0.5 mF
9 mΩ
9 mΩ
80 µH
80 µH
Main dc bus
950 V 60 Hz 3-Ph ac
950 V 60 Hz 3-Ph ac 1150 V dc
Diff. prot. zone
0 5 10 15 20 25 30 35 40-500
0
500
1000
1500
2000
time (ms)
Volta
ge (V
)
0 5 10 15 20 25 30 35 400
500
1000
1500
2000
time (ms)
Cur
rent
(A)
Current differential: i1(t) + i2(t)
i1(t)
i2(t)
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AC Distribution System Protection • Supported by DOE • Fault type identification o Permanent or temporary
• Fault location • Islanding detection • Optimal sensor placement
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0.05 0.1 0.15 0.2 0.25-100
-50
0
50
Currents for a permanent fault
Time (Seconds)
Cur
rent
(p.
u.)
0.05 0.1 0.15 0.2 0.25-100
-50
0
50
100Currents for a transient fault
Time (Seconds)
Cur
rent
(p.
u.)
0.05 0.1 0.15 0.2 0.25-100
-50
0
50
Currents for a permanent fault
Time (Seconds)
Cur
rent
(p.
u.)
0.05 0.1 0.15 0.2 0.25-100
-50
0
50
100Currents for a transient fault
Time (Seconds)
Cur
rent
(p.
u.)
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Proposed intelligent sensors
Permanent fault
Transient fault
intelligent sensor
s1s2
s3
faultGPS signals
Legends
fuse
s4 t
s1
s2
s3
s4
Fault Fuse blow
AC Distribution System Protection
• Impedance fault location 1. Requirement ‒ Network model ‒ Fault waveforms
2. Benefit ‒ Locate fault segment ‒ Do not need synch.
• Traveling wave method 1. Requirement ‒ GPS synchronization ‒ High bandwidth sensor ‒ Fast processing speed
2. Benefit ‒ Incipient fault location (sub-
cycle fault) ‒ Simple algorithm
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Conclusion 1. Fault management is critical for power system safety
and reliability
2. Our dc prot. approach reduces fault clearing time and system recovery time
3. The fast prot. method significantly improves power system resilience
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Thanks for your attention
Contact information: Xianyong Feng, PhD Center for Electromechanics The University of Texas at Austin Email: [email protected] Phone: 1-512-232-1623
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