Design Specifications

The bottom-up design flow for a transistor-level circuit layout always starts with a set of design specifications. The "specs" typically describe the expected functionality (Boolean operations) of the designed block, as well as the maximum allowable delay times, the silicon area and other properties such as power dissipation. Usually, the design specifications allow considerable freedom to the circuit designer on issues concerning the choice of a specific circuit topology, individual placement of the devices, the locations of input and output pins, and the overall aspect ratio (width-to-height ratio) of the final design. Note that the limitations spelled out in the initial design specs typically require certain design trade-offs, such as increasing the dimensions of the transistors in order to reduce the delay times.

In a large-scale design, the initial design specifications may also evolve during the design process to accomodate other specs or limitations.

This implies that the designer(s) of individual blocks or modules must communicate clearly and frequently about the spec updates, in order to avoid later inconsistencies.

As an example, the initial design specs of a one-bit binary full adder circuit are listed below:

• Technology: 0.8 um twin-well CMOS • Propagation delay of "sum" and "carry_out" signals < 1.2 ns (worst case) • Transition times of "sum" and "carry_out" signals <1.2 ns (worst case) • Circuit area < 1500 um^2 • Dynamic power dissipation (at VDD=5 V and fmax=20 MHz) < 1 mW

It can be seen that one can design a number of different adders (with different topologies, different maximum delays, different total silicon areas, etc.), all of which essentially conform to the specs listed above. This indicates that the starting point of a typical bottom-up design process usually leaves the designer a considerable amount of design freedom.

Schematic Capture

Please follow the example link (button) for a detailed description of "Schematic Capture".

The traditional method for capturing (i.e. describing) your transistor-level or gate-level design is via the schematic editor. Schematic editors provide simple, intuitive means to draw, to place and to connect individual components that make up your design. The resulting schematic drawing must accurately describe the main electrical properties of all components and their interconnections. Also included in the schematic are the power supply and ground connections, as well as all "pins" for the input and output signals of your circuit. This information is crucial for generating the corresponding netlist, which is used in later stages of the design. The generation of a complete circuit schematic is therefore the first important step of the transistor-level design flow. Usually, some properties of the components (e.g. transistor dimensions) and/or the interconnections between the devices are subsequently modified as a result of iterative optimization steps. These later modifications and improvements on the circuit structure must also be accurately reflected in the most current version of the corresponding schematic.

Symbol Creation

Please follow the example link (button) for a detailed description of "Symbol Creation".

If a certain circuit design consists of smaller hierarchical components (or modules), it is usually very beneficial to identify such modules early in the design process and to assign each such module a corresponding symbol (or icon) to represent that circuit module. This step largely simplifies the schematic representation of the overall system. The "symbol" view of a circuit module is an icon that stands for the collection of all components within the module.

A symbol view of the circuit is also required for some of the subsequent simulation steps, thus, the schematic capture of the circuit topology is usually followed by the creation of a symbol to represent the entire circuit. The shape of the icon to be used for the symbol may suggest the function of the module (e.g. logic gates - AND, OR, NAND, NOR), but the default symbol icon is a simple rectangular box with input and output pins. Note that this icon can now be used as the building block of another module, and so on, allowing the circuit designer to create a system-level design consisting of multiple hierarchy levels.

Simulation

Please follow the example link (button) for a detailed description of "Simulation".

After the transistor-level description of a circuit is completed using the Schematic Editor, the electrical performance and the functionality of the circuit must be verified using a Simulation tool. The detailed transistor-level simulation of your design will be the first in-depth validation of its operation, hence, it is extremely important to complete this step before proceeding with the subsequent design optimization steps. Based on simulation results, the designer usually modifies some of the device properties (such as transistor width-to-length ratio) in order to optimize the performance.

The initial simulation phase also serves to detect some of the design errors that may have been created during the schematic entry step. It is quite common to discover errors such as a missing connection or an unintended crossing of two signals in the schematic.

The second simulation phase follows the "extraction" of a mask layout (post-layout simulation), to accurately assess the electrical performance of the completed design.

Mask Layout

• Manual Layout Example

• Automatic Layout Example (Device Level Placer)

The creation of the mask layout is one of the most important steps in the full-custom (bottom-up) design flow, where the designer describes the detailed geometries and the relative positioning of each mask layer to be used in actual fabrication, using a Layout Editor. Physical layout design is very tightly linked to overall circuit performance (area, speed and power dissipation) since the physical structure determines the transconductances of the transistors, the parasitic capacitances and resistances, and obviously, the silicon area which is used to realize a certain function. On the other hand, the detailed mask layout of logic gates requires a very intensive and time-consuming design effort.

The physical (mask layout) design of CMOS logic gates is an iterative process which starts with the circuit topology and the initial sizing of the transistors. It is extremely imporant that the layout design must not violate any of the Layout Design Rules, in order to ensure a high probability of defect-free fabrication of all features described in the mask layout.

Please follow this example link for a detailed description of the main procedures in "Mask Layout Design".

Another alternative of generating the mask layout is to make use of automated tools. Please follow this example link for a detailed description of generating a layout from a schematic using the device level placer.

Design Rule Check (DRC)

Please follow this example link for a description of how to run DRC on a layout.

The created mask layout must conform to a complex set of design rules, in order to ensure a lower probability of fabrication defects. A tool built into the Layout Editor, called Design Rule Checker, is used to detect any design rule violations during and after the mask layout design. The detected errors are displayed on the layout editor window as error markers, and the corresponding rule is also displayed in a separate window. The designer must perform DRC (in a large design, DRC is usually performed frequently - before the entire design is completed), and make sure that all layout errors are eventually removed from the mask layout, before the final design is saved.

Circuit Extraction

Please follow the example link (button) for a detailed description of "Circuit Extraction".

Circuit extraction is performed after the mask layout design is completed, in order to create a detailed net-list (or circuit description) for the simulation tool. The circuit extractor is capable of identifying the individual transistors and their interconnections (on various layers), as well as the parasitic resistances and capacitances that are inevitably present between these layers. Thus, the "extracted net-list" can provide a very accurate estimation of the actual device dimensions and device parasitics that ultimately determine the circuit performance. The extracted net-list file and parameters are subsequently used in Layout-versus-Schematic comparison and in detailed transistor-level simulations (post-layout simulation).

Layout versus Schematic Check

Please follow the example link (button) for a detailed description of "Layout versus Schematic Check".

After the mask layout design of the circuit is completed, the design should be checked against the schematic circuit description created earlier. The design called "Layout-versus-Schematic (LVS) Check" will compare the original network with the one extracted from the mask layout, and prove that the two networks are indeed equivalent. The LVS step provides an additional level of confidence for the integrity of the design, and ensures that the mask layout is a correct realization of the intended circuit topology. Note that the LVS check only guarantees topological match: A successful LVS will not guarantee that the extracted circuit will actually satisfy the performance requirements. Any errors that may show up during LVS (such as unintended connections between transistors, or missing connections/devices, etc.) should be corrected in the mask layout - before proceeding to post-layout simulation. Also note that the extraction step must be repeated every time you modify the mask layout.

Post-layout Simulation

Please follow the example link (button) for a detailed description of "Post-Layout Simulation".

The electrical performance of a full-custom design can be best analyzed by performing a post-layout simulation on the extracted circuit net-list. At this point, the designer should have a complete mask layout of the intended circuit/system, and should have passed the DRC and LVS steps with no violations. The detailed (transistor-level) simulation performed using the extracted net-list will provide a clear assessment of the circuit speed, the influence of circuit parasitics (such as parasitic capacitances and resistances), and any glitches that may occur due to signal delay mismatches.

If the results of post-layout simulation are not satisfactory, the designer should modify some of the transistor dimensions and/or the circuit topology, in order to achieve the desired circuit performance under "realistic" conditions, i.e., taking into account all of the circuit parasitics. This may require multiple iterations on the design, until the post-layout simulation results satisfy the original design requirements.

Finally, note that a satisfactory result in post-layout simulation is still no guarantee for a completely successful product; the actual performance of the chip can only be verified by testing the fabricated prototype. Even though the parasitic extraction step is used to identify the realistic circuit conditions to a large degree from the actual mask layout, most of the extraction routines and the simulation models used in modern design tools have inevitable numerical limitations. This should always be one of the main design considerations, from the very beginning.

After all, there is no substitute for the "real silicon" !

Example :

Example : Postlayout Simulation (CMOS Inverter)

Step 1 : Extracting from the Layout

The mask layout only contains physical data. In fact it just contains coordinates of rectangles drawn in different colors (layers). The extraction process identifies the devices and generates a netlist associated with the layout.

Make sure you have a layout window with a finished design ready. Make sure that the design does not contain any DRC errors.

1. From the Verify menu select the option Extract( verify --> Extract )

A new window with extraction options will appear. The default options will only extract ideal devices. This ideal case would reasult in a list much similar to the schematic. For a more accurate representation, however, we will have to take the parasitic effects into account. To enable the extraction of parasitic devices, a selection parameter called a switch has to be specified. You can type the switch into the designated box, or you can select it from a menu using the Set Switches option.

The switch specified in the example (above) to enable extracting the parasitic capacitances is called Extract_parasitic_caps.

Check the Command Interpreter Window (the main window when you start Cadence) for errors after extraction.

Following a successfull extraction you will see a new cell view called extracted for your cell in the library manager. See the following section for accessing the extracted view.

Example : Postlayout Simulation (CMOS Inverter)

Step 2 : The Extracted Cell View

Following the extraction step a new cellview is generated in your library. This cell view is called extracted view.

Try loading the cellview. It will open up a layout that looks almost identical to the layout you have extracted. You will notice that only the I/O pins appear as solid blocks and all other shapes appear as outlines.

The red rectangles indicate that there are a number of instances within this hierarchy. Try pressing Shift-F to see all of the hierarchy.

This will reveal a number of symbols. If you zoom in you will be able to identify individual elements, such as transistors and capacitors. You will notice that the parameters (e.g. channel dimensions) of these devices represent the values they were drawn in the layout view.

Apart from your actual devices you will notice a number of elements, mainly capacitors in your extracted cell view. These are not actual devices, they are parasitic capacitances, side effects formed by different layers you used for your layout.

The next step will be to correpond the extracted netlist to that of the schematic. This is called the Layout Versus Schematic checking. This will ensure that the schematic that we have drawn and the layout are identical.

Example : Postlayout Simulation (CMOS Inverter)

Step 3 : Layout Versus Schematic

In this step we are going to compare the schematic and the extracted layout to see if they are identical.

1. From the Verify menu select the option LVS.

If you had previously run a LVS check, this would pop-up a small warning box. Make sure that the option Form Contents is selected in this box.

The top half of the LVS options window is split into two parts. The part on the left corresponds to the schematic cell view and the right part corresponds to the extracted cell view that are to be compared. Make sure that the entries in these boxes represent the values for your circuit.

Although there are a number of options for LVS, the default options will be enough for basic operations, select Run to start the comparison.

The comparison algorithm will run in the background, the result of the LVS run will be displayed in a message box. Be patient, even for a very small design the LVS run can take some time (minutes).

The succeeded message in the above message box, indicates that the LVS program has finished comparing the netlists, NOT THAT THE CIRCUITS MATCH. It might be the case that the LVS was successful in comparing the netlists and came up with the result that both circuits were different.

To see the actual result of an LVS run you have to examine the output of the LVS run. The Output option is right next to the Run command

You can take a look at the complete LVS result here. The most important part of the report can be found in the figure above. It states that the netlists did indeed match. If you discover that there is a mismatch, you must go back to the layout view and correct the error(s).

Most of the other options on the LVS form, are for finding mismatches between two netlists and to generate netlists that include only parasitic effects relevant to one part of the circuit.

Example : Postlayout Simulation (CMOS Inverter)

Step 4 : Summary of the Cell Views.

So far you have created a number of cell views corresponding to the same circuit. In this section we want to review all of these cellviews and discuss why they are used.

1. Schematic view

For any design, the schematic should be the first cell view to be created. The schematic will be the basic reference of your circuit.

2. Symbol view

After you are done with the schematic, you will need to simulate your design. The proper way of doing this is to create a seperate test schematic and include your circuit as a block. Therefore you will need to create a symbol.

3. Layout view

This is the actual layout mask data that will be fabricated. It can be generated by automated tools or manually.

4. Extracted view

After the layout has been finalized, it is extracted, devices and parasitic elements are identified and a netlist is formed.

5. Test Schematic

A separate cell is used to as a test bench. This test bench includes sources, loads and the circuit to be tested. The test cell usually consists of a single schematic only.

Example : Postlayout Simulation (CMOS Inverter)

Step 5 : Simulating the Extracted Cell View

After a successful LVS you will have two main cell views for the same circuit. The first one is the schematic, which is your initial (ideal) design, the second is the extracted, that is based on the layout and in addition to the basic circuit includes all the layout associated parasitic effects. Since both of these views refer to the same circuit they can be interchanged.

In this example we are going to re-run the simulation example, but we will make the simulator to use the extracted cell view instead of the schematic cell view.

Make sure that you are in the test schematic, that you used to simulate your design earlier.

1. Start Analog Artist using Tools --> Analog Artist

The Analog Artist window will pop-up.

2. From the Setup menu choose the Environment option.

A new dialog box controlling various parameters of Analog Artist will pop-up.

The line that we will have to alter is called the Switch View List. This entry is an ordered list of cell views that contain information that can be simulated. The simulator (in fact the netlister) will search until it finds one of these cellviews. The default entry does not contain an extracted cellview. We will simply add an entry for extracted cellview in front of the schematic cellview.

As a result of this modification, the simulator will use the extracted cell view of the cell, if one is available.

3. Choose analyses

In the simulation example a transient analysis was used, this time we will use a DC simulation. In a DC simulation the value of any voltage or current source is varied over a specified range. It is used to obtain input/output characteristics of circuits.

The basic options of the DC analysis are not very straight-forward. The first step is to determine what parameter will be swept.

Choose Component Parameter as the Sweep Variable.

You can select the parameter from the schematic window after you click on Select Component.

As each component has a number of parameters, you will be given a list of parameters associated with the component you select.

In the example given above we have selected the DC voltage of the voltage source as the sweep variable.

After we have selected the variable we can decide, the range where the variable will change.

This example changes the DC voltage source connected to the input from 0 Volts to 3.3 Volts.

The last parameter determines how the sweep will be performed. A linear sweep will increment the value of the sweep variable by a fixed amount. The example below uses a step size of 10 millivolts.

From this point on the simulation will continue just as it has been described in the Simulation Tutorial, except for the fact that the results will now include parasitic effects from the actual layout.

This site contains a complete on-line tutorial for a typical bottom-up design flow using CADENCE Custom IC Design Tools (version 97A). The examples were generated using the HP 0.6 um CMOS14TB process technology files, prepared at North Carolina State University (NCSU) and made available through MOSIS.

Please click on any box in the design flow (below) to see a detailed description of the corresponding design step, and to view the design examples.