Ltm 4601

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LTM4601/LTM4601-1

1

4601fc

12A µModule Regulatorswith PLL, Output Tracking

and Margining

n Telecom and Networking Equipmentn Serversn Industrial Equipmentn Point o Load Regulation

n Complete Switch Mode Power Supplyn Wide Input Voltage Range: 4.5V to 20Vn 12A DC Typical, 14A Peak Output Currentn 0.6V to 5V Output Voltagen Output Voltage Tracking and Marginingn Parallel Multiple µModule Regulators or Current

Sharingn Dierential Remote Sensing or Precision

Regulation (LTM4601 Only)n PLL Frequency Synchronizationn

±1.5% Regulationn Current Foldback Protection (Disabled at Start-Up)n RoHS Compliant with Pb-Free Finish

Gold Finish LGA (e4) or SAC 305 BGA (e1)n UltraFast™ Transient Responsen Current Mode Controln Up to 95% Eciency at 5VIN, 3.3VOUTn Programmable Sot-Startn Output Overvoltage Protectionn Small Footprint, Low Prole

(15mm × 15mm × 2.82mm) Surace Mount LGA and(15mm × 15mm × 3.42mm) BGA Packages

1.5V/12A Power Supply with 4.5V to 20V Input

Efciency and Power Lossvs Load Current

The LTM®4601 is a complete 12A step-down switch modeDC/DC power supply with onboard switching controller,MOSFETs, inductor and all support components. TheµModule® regulator is housed in small surace mount15mm × 15mm × 2.82mm LGA and 15mm × 15mm × 3.42mm BGA packages. Operating over an input voltagerange o 4.5V to 20V, the LTM4601 supports an outputvoltage range o 0.6V to 5V as well as output voltagetracking and margining. The high eciency design deliv-ers 12A continuous current (14A peak). Only bulk input

and output capacitors are needed to complete the design.The low prole and light weight package easily mountsin unused space on the back side o PC boards or highdensity point o load regulation. The µModule regulatorcan be synchronized with an external clock or reducingundesirable requency harmonics and allows PolyPhase® operation or high load currents.

A high switching requency and adaptive on-time currentmode architecture deliver a very ast transient responseto line and load changes without sacricing stability. Anonboard dierential remote sense amplier can be usedto accurately regulate an output voltage independent oload current. The onboard remote sense amplier is notavailable in the LTM4601-1.L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule and PolyPhase are registeredtrademarks and UltraFast and LTpowerCAD are trademarks o Linear Technology Corporation.All other trademarks are the property o their respective owners. Protected by U.S. Patentsincluding 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210.

TYPICAL APPLICATION

FEATURES DESCRIPTION

APPLICATIONS

VOUT

VFB

MARG0

MARG1

VOUT_LCL

DIFFVOUT

VOSNS+

VOSNS–

PGOOD

RUN

COMP

INTVCC

DRVCC

MPGM

TRACK/SSPLLIN

LTM4601

ON/OFF

R1392k RSET

40.2k

MARGINCONTROL COUT

4601 TA01a

VOUT1.5V12A

CLOCK SYNC

TRACK/SS CONTROL

100pF

CIN

VIN

fSETPGNDSGND

5% MARGIN

VIN

4.5V TO 20V

LOAD CURRENT (A)

050

E F F I C I E N C Y ( % )

P O WE R L O S S ( W )

55

65

70

75

95

4601 TA01b

60

2 4 6 8 10 12 14

80

85

90

0.5

1.0

2.0

4.0

1.5

2.5

3.0

3.5

12VIN

12VIN

5VIN

5VIN

EFFICIENCY

POWER LOSS

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LTM4601/LTM4601-1

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INTVCC, DRVCC, VOUT_LCL, VOUT (VOUT ≤ 3.3V withDIFFVOUT) .................................................... –0.3V to 6V

PLLIN, TRACK/SS, MPGM, MARG0, MARG1,PGOOD, SET ..............................–0.3V to INTVCC + 0.3VRUN (Note 5) ............................................... –0.3V to 5VVFB, COMP ................................................ –0.3V to 2.7V

(Note 1)ABSOLUTE MAXIMUM RATINGS

ORDER INFORMATION

LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE (NOTE 2)

LTM4601EV#PBF LTM4601EV#PBF LTM4601V 118-Lead (15mm × 15mm × 2.82mm) LGA –40°C to 85°C

LTM4601IV#PBF LTM4601IV#PBF LTM4601V 118-Lead (15mm × 15mm × 2.82mm) LGA –40°C to 85°C

LTM4601EV-1#PBF LTM4601EV-1#PBF LTM4601V-1 118-Lead (15mm × 15mm × 2.82mm) LGA –40°C to 85°C

LTM4601IV-1#PBF LTM4601IV-1#PBF LTM4601V-1 118-Lead (15mm × 15mm × 2.82mm) LGA –40°C to 85°C

LTM4601EY#PBF LTM4601EY#PBF LTM4601Y 118-Lead (15mm × 15mm × 3.42mm) BGA –40°C to 85°C

LTM4601IY#PBF LTM4601IY#PBF LTM4601Y 118-Lead (15mm × 15mm × 3.42mm) BGA –40°C to 85°C

Consult LTC Marketing or parts specied with wider operating temperature ranges. *The temperature grade is identied by a label on the shipping container.

For more inormation on lead ree part marking, go to: http://www.linear.com/leadree/ This product is only oered in trays. For more inormation go to: http://www.linear.com/packaging/

VIN ............................................................. –0.3V to 20VVOSNS

+, VOSNS–..........................–0.3V to INTVCC + 0.3V

Operating Temperature Range (Note 2)....–40°C to 85°CJunction Temperature ........................................... 125°CStorage Temperature Range .................. –55°C to 125°C

MARG1

DRVCC

VFB

PGOOD

SGND

VOSNS+ /NC2*

DIFFVOUT /NC3*

VOUT_LCL

VOSNS– /NC1*

VIN

PGND

VOUT

fSET

MARG0

R U N

C O M P

M P G M

P L L I N

I N T V C C

T R A C K / S S

LGA PACKAGE118-LEAD (15mm × 15mm × 2.82mm)

TOP VIEW

TJMAX = 125°C, θJA = 15°C/W, θJC = 6°C/W,

θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERSWEIGHT = 1.7g

*LTM4601-1 ONLY

MARG1

DRVCC

VFB

PGOOD

SGND

VOSNS+

DIFFVOUT

VOUT_LCL

VOSNS–

VIN

PGND

VOUT

fSET

MARG0

R U N

C O M P

M P G M

P L L I N

I N T V C C

T R A C K / S S

BGA PACKAGE118-LEAD (15mm × 15mm × 3.42mm)

TOP VIEW

TJMAX = 125°C, θJA = 15.5°C/W, θJC = 6.5°C/W,

θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERSWEIGHT = 1.9g

PIN CONFIGURATION

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ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN(DC) Input DC Voltage l 4.5 20 V

VOUT(DC) Output Voltage CIN = 10µF ×3, COUT = 200µF, RSET = 40.2kVIN = 5V, VOUT = 1.5V, IOUT = 0AVIN = 12V, VOUT = 1.5V, IOUT = 0A

l

l

1.4781.478

1.51.5

1.5221.522

VV

Input Specifcations

VIN(UVLO) Undervoltage Lockout Threshold IOUT = 0A 3.2 4 V

IINRUSH(VIN) Input Inrush Current at Start-Up IOUT = 0A. VOUT = 1.5VVIN = 5VVIN = 12V

0.60.7

AA

IQ(VIN,NOLOAD) Input Supply Bias Current VIN = 12V, No SwitchingVIN = 12V, VOUT = 1.5V, Switching ContinuousVIN = 5V, No SwitchingVIN = 5V, VOUT = 1.5V, Switching ContinuousShutdown, RUN = 0, VIN = 12V

3.8382.54222

mAmAmAmAµA

IS(VIN) Input Supply Current VIN = 12V, VOUT = 1.5V, IOUT = 12AVIN = 12V, VOUT = 3.3V, IOUT = 12AVIN = 5V, VOUT = 1.5V, IOUT = 12A

1.813.634.29

AAA

INTVCC VIN = 12V, RUN > 2V No Load 4.7 5 5.3 V

Output Specifcations

IOUTDC Output Continuous Current Range VIN = 12V, VOUT = 1.5V (Note 6) 0 12 A

ΔVOUT(LINE)

VOUT

Line Regulation Accuracy VOUT = 1.5V, IOUT = 0A, VIN rom 4.5V to 20V l 0.3 %

ΔVOUT(LOAD)

VOUT

Load Regulation Accuracy VOUT = 1.5V, 0A to 12A (Note 6)VIN = 12V, with Remote Sense AmplierVIN = 12V (LTM4601-1)

l

l

0.25

1

%%

VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 2× 100µF X5R Ceramic

VIN = 12V, VOUT = 1.5VVIN = 5V, VOUT = 1.5V

2018

mVP-PmVP-P

S Output Ripple Voltage Frequency IOUT = 5A, VIN = 12V, VOUT = 1.5V 850 kHz

ΔVOUT(START) Turn-On Overshoot COUT = 200µF, VOUT = 1.5V, IOUT = 0A,TRACK/SS = 10nF

VIN = 12VVIN = 5V

2020

mVmV

tSTART Turn-On Time COUT = 200µF, VOUT = 1.5V, TRACK/SS = Open,IOUT = 1A Resistive Load

VIN = 12VVIN = 5V

0.50.5

msms

ΔVOUTLS Peak Deviation or Dynamic Load Load: 0% to 50% to 0% o Full Load,COUT = 2 × 22µF Ceramic, 470µF 4V Sanyo

POSCAPVIN = 12VVIN = 5V

3535

mVmV

tSETTLE Settling Time or Dynamic Load Step Load: 0% to 50%, or 50% to 0% o Full LoadVIN = 12V

25

µs

IOUTPK Output Current Limit COUT = 200µF CeramicVIN = 12V, VOUT = 1.5VVIN = 5V, VOUT = 1.5V

1717

AA

The l denotes the specifcations which apply over the –40°C to 85°Ctemperature range (Note 2), otherwise specifcations are at TA = 25°C, VIN = 12V, per typical application (ront page) confguration.

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Remote Sense Amp (Note 3) (LTM4601 Only, Not Supported in the LTM4601-1)

VOSNS+, VOSNS– CM Range

Common Mode Input Voltage Range VIN = 12V, RUN > 2V 0 INTVCC – 1 V

DIFFVOUT Range Output Voltage Range VIN = 12V, DIFFVOUT Load = 100k 0 INTVCC – 1 V

VOS Input Oset Voltage Magnitude 1.25 mV

AV Dierential Gain 1 V/V

GBP Gain Bandwidth Product 3 MHz

SR Slew Rate 2 V/µs

RIN Input Resistance VOSNS+ to GND 20 kW

CMRR Common Mode Rejection Mode 100 dB

Control Stage

VFB

Error Amplier Input VoltageAccuracy

IOUT

= 0A, VOUT

= 1.5V l 0.594 0.6 0.606 V

VRUN RUN Pin On/O Threshold 1 1.5 1.9 V

ITRACK/SS Sot-Start Charging Current VTRACK/SS = 0V –1.0 –1.5 –2.0 µA

tON(MIN) Minimum On Time (Note 4) 50 100 ns

tOFF(MIN) Minimum O Time (Note 4) 250 400 ns

RPLLIN PLLIN Input Resistance 50 kW

IDRVCC Current into DRVCC Pin VOUT = 1.5V, IOUT = 1A, DRVCC = 5V 18 25 mA

RFBHI Resistor Between VOUT_LCL and VFB 60.098 60.4 60.702 kW

VMPGM Margin Reerence Voltage 1.18 V

VMARG0, VMARG1 MARG0, MARG1 Voltage Thresholds 1.4 V

PGOOD Output

ΔVFBH PGOOD Upper Threshold VFB Rising 7 10 13 %

ΔVFBL PGOOD Lower Threshold VFB Falling –7 –10 –13 %

ΔVFB(HYS) PGOOD Hysteresis VFB Returning 1.5 %

Note 1: Stresses beyond those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. Exposure to any AbsoluteMaximum Rating condition or extended periods may aect devicereliability and lietime.

Note 2: The LTM4601 is tested under pulsed load conditions such thatTJ ≈ TA. The LTM4601E/LTM4601E-1 are guaranteed to meet perormancespecications rom 0°C to 85°C. Specications over the –40°C to 85°C

operating temperature range are assured by design, characterization andcorrelation with statistical process controls. The LTM4601I/LTM4601I-1are guaranteed over the –40°C to 85°C operating temperature range.

Note 3: Remote sense amplier recommended or ≤3.3V output.

Note 4: 100% tested at waer level only.

Note 5: Limit current into RUN pin to less than 1mA.

Note 6: See output current derating curves or dierent VIN, VOUT and TA.

ELECTRICAL CHARACTERISTICS The l denotes the specifcations which apply over the –40°C to 85°Ctemperature range (Note 2), otherwise specifcations are at TA = 25°C, VIN = 12V, per typical application (ront page) confguration.

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Efciency vs Load Currentwith 5VIN



1.2V Transient Response 1.5V Transient Response

2.5V Transient Response



TYPICAL PERFORMANCE CHARACTERISTICS (See Figure 18 or all curves)

VOUT50mV/DIV

20µs/DIV 4601 G04

0A TO 6ALOAD STEP

1.2V AT 6A/µs LOAD STEP

COUT = 3 • 22µF 6.3V CERAMICS470µF 4V SANYO POSCAPC3 = 100pF

VOUT50mV/DIV

20µs/DIV 4601 G05

0A TO 6ALOAD STEP



VOUT50mV/DIV

20µs/DIV 4601 G06

0A TO 6ALOAD STEP



VOUT50mV/DIV

20µs/DIV 4601 G07

0A TO 6ALOAD STEP

2.5V AT 6A/µs LOAD STEPCOUT = 3 • 22µF 6.3V CERAMICS470µF 4V SANYO POSCAPC3 = 100pF

VOUT50mV/DIV

20µs/DIV 4601 G08

0A TO 6ALOAD STEP

3.3V AT 6A/µs LOAD STEPCOUT = 3 • 22µF 6.3V CERAMICS470µF 4V SANYO POSCAPC3 = 100pF

LOAD CURRENT (A)

0


75

80

85

15

4601 G01

70

65

605 10

90

95

100

0.6VOUT1.2VOUT1.5VOUT2.5VOUT3.3VOUT

LOAD CURRENT (A)

050


55

65

70

75

100

85

5 10

4601 G02

60

90

95

80

15

0.6VOUT1.2VOUT1.5VOUT2.5VOUT3.3VOUT5VOUT

LOAD CURRENT (A)

0

100

90

95

85

80

75

70

65

60

4601 G03

5 10 15


1.2VOUT1.5VOUT2.5VOUT3.3VOUT5.0VOUT

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Start-Up, IOUT = 12A(Resistive Load)Start-Up, IOUT = 0A

VIN to VOUT Step-Down Ratio

Short-Circuit Protection, IOUT = 0A Short-Circuit Protection, IOUT = 12A

Track, IOUT = 12A

TYPICAL PERFORMANCE CHARACTERISTICS (See Figure 18 or all curves)

VOUT0.5V/DIV

5ms/DIV 4601 G09

IIN0.5A/DIV

VIN = 12VVOUT = 1.5VCOUT = 470µF, 3 × 22µFSOFT-START = 10nF

VOUT0.5V/DIV

2ms/DIV 4601 G10

IIN1A/DIV


INPUT VOLTAGE (V)

0

O U T P U T

V O L T A G E

( V )

3.0

4.0

5.5

5.0

16

4601 G11

2.0

1.0

2.5

3.5

4.5

1.5

0.5

042 86 12 14 1810 20

3.3V OUTPUT WITH130k FROM VOUT TO ION

5V OUTPUT WITH100k RESISTORADDED FROM fSET TO GND

5V OUTPUT WITHNO RESISTOR ADDEDFROM fSET TO GND

2.5V OUTPUT

1.8V OUTPUT1.5V OUTPUT

1.2V OUTPUT

VOUT0.5V/DIV

50µs/DIV 4601 G13

IIN1A/DIV


VFB0.5V/DIV

TRACK/SS0.5V/DIV

2ms/DIV 4601 G12

VOUT1V/DIV

VIN = 12V

VOUT = 1.5VCOUT = 470µF, 3 × 22µFSOFT-START = 10nF

VOUT0.5V/DIV

50µs/DIV 4601 G14

IIN1A/DIV


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PIN FUNCTIONS (See Package Description or Pin Assignment)

VIN (Bank 1): Power Input Pins. Apply input voltage be-tween these pins and PGND pins. Recommend placinginput decoupling capacitance directly between VIN pins

and PGND pins.

VOUT (Bank 3): Power Output Pins. Apply output loadbetween these pins and PGND pins. Recommend placingoutput decoupling capacitance directly between these pinsand PGND pins. See Figure 15.

PGND (Bank 2): Power ground pins or both input andoutput returns.

VOSNS– (Pin M12): (–) Input to the Remote Sense Ampli-

er. This pin connects to the ground remote sense point.The remote sense amplier is used or V

OUT≤3.3V. Tie to

INTVCC i not used.

NC1 (Pin M12): No internal connection on the LTM4601-1.

VOSNS+ (Pin J12): (+) Input to the Remote Sense Ampli-

er. This pin connects to the output remote sense point.The remote sense amplier is used or VOUT ≤3.3V. Tie toground i not used.

NC2 (Pin J12): No internal connection on the LTM4601-1.

DIFFVOUT (Pin K12): Output o the Remote Sense Ampli-er. This pin connects to the VOUT_LCL pin. Leave foating

i not used.

NC3 (Pin K12): No internal connection on the LTM4601-1.

DRVCC (Pin E12): This pin normally connects to INTVCC or powering the internal MOSFET drivers. This pin can bebiased up to 6V rom an external supply with about 50mAcapability, or an external circuit as shown in Figure 16.This improves eciency at the higher input voltages byreducing power dissipation in the module.

INTVCC (Pin A7): This pin is or additional decoupling othe 5V internal regulator.

PLLIN (Pin A8): External Clock Synchronization Inputto the Phase Detector. This pin is internally terminatedto SGND with a 50k resistor. Apply a clock with a highlevel above 2V and below INTVCC. See the ApplicationsInormation section.

TRACK/SS (Pin A9): Output Voltage Tracking and Sot-Start Pin. When the module is congured as a masteroutput, then a sot-start capacitor is placed rom this pin

to ground to control the master ramp rate. A sot-startcapacitor can also be used or sot-start turn-on o a standalone regulator. Slave operation is perormed by puttinga resistor divider rom the master output to the ground,and connecting the center point o the divider to this pin.See the Applications Inormation section.

MPGM (Pin A12): Programmable Margining Input. A re-sistor rom this pin to ground sets a current that is equalto 1.18V/R. This current multiplied by 10kW will equal avalue in millivolts that is a percentage o the 0.6V reer-

ence voltage. See the Applications Inormation section.To parallel LTM4601s, each requires an individual MPGMresistor. Do not tie MPGM pins together.

SET (Pin B12): Frequency Set Internally to 850kHz. Anexternal resistor can be placed rom this pin to groundto increase requency. See the Applications Inormationsection or requency adjustment.

VFB (Pin F12): The Negative Input o the Error Amplier.Internally, this pin is connected to VOUT_LCL pin with a60.4k precision resistor. Dierent output voltages can be

programmed with an additional resistor between VFB andSGND pins. See the Applications Inormation section.

MARG0 (Pin C12): This pin is the LSB logic input or themargining unction. Together with the MARG1 pin it willdetermine i margin high, margin low or no margin stateis applied. The pin has an internal pull-down resistor o50k. See the Applications Inormation section.

MARG1 (Pin D12): This pin is the MSB logic input or themargining unction. Together with the MARG0 pin it willdetermine i margin high, margin low or no margin stateis applied. The pin has an internal pull-down resistor o50k. See the Applications Inormation section.

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SGND (Pin H12): Signal Ground. This pin connects toPGND at output capacitor point. See Figure 15.

COMP (Pin A11): Current Control Threshold and ErrorAmplier Compensation Point. The current comparatorthreshold increases with this control voltage. The voltageranges rom 0V to 2.4V with 0.7V corresponding to zerosense voltage (zero current).

PGOOD (Pin G12): Output Voltage Power Good Indicator.Open-drain logic output that is pulled to ground when theoutput voltage is not within ±10% o the regulation point,ater a 25µs power bad mask timer expires.

RUN (Pin A10): Run Control Pin. A voltage above 1.9Vwill turn on the module, and when below 1V, will turno the module. A programmable UVLO unction can be

accomplished by connecting to a resistor divider romVIN to ground. See Figure 1. This pin has a 5.1V Zener toground. Maximum pin voltage is 5V. Limit current into theRUN pin to less than 1mA.

VOUT_LCL (Pin L12): VOUT connects directly to this pinto bypass the remote sense amplier, or DIFFVOUT con-nects to this pin when the remote sense amplier is used.VOUT_LCL can be connected to VOUT on the LTM4601-1,VOUT is internally connected to VOUT_LCL with 50W in theLTM4601-1.

PIN FUNCTIONS (See Package Description or Pin Assignment)

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Figure 1. Simplifed LTM4601/LTM4601-1 Block Diagram

SIMPLIFIED BLOCK DIAGRAM


CIN External Input Capacitor Requirement (VIN =4.5V to 20V, VOUT = 1.5V)

IOUT = 12A, 3× 10µF Ceramics 20 30 µF

COUT External Output Capacitor Requirement (VIN

= 4.5V to 20V, VOUT = 1.5V)

IOUT = 12A 100 200 µF

TA = 25°C, VIN = 12V. Use Figure 1 confguration.DECOUPLING REQUIREMENTS

+

INTERNALCOMP

SGND

COMP

PGOOD

RUN

VOUT_LCLVIN

>1.9V = ON<1V = OFF

MAX = 5V

MARG1

MARG0

MPGM

PLLINCSS

INTVCC

DRVCC

TRACK/SS

VFB

fSET

50k

39.2k

RSET40.2k

50k

R2

60.4k

VOUT

1M(50Ω, LTM4601-1)

5.1VZENER

POWER CONTROLQ1

VIN4.5V TO 20V

VOUT1.5V12A

Q2

10k

0.47µH

10k

10k

NOT INCLUDEDIN THE LTM4601-1

VOSNS– = NC1

VOSNS+ = NC2

DIFFVOUT = NC3

50k

10kINTVCC

2.2k

R1

UVLOFUNCTION

+

–

22µF

1.5µF CIN

+COUT

PGND

VOSNS–

VOSNS+

DIFFVOUT

4601 F01

4.7µF

= SGND

= PGND

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Power Module Description

The LTM4601 is a standalone nonisolated switching mode

DC/DC power supply. It can deliver up to 12A o DC outputcurrent with some external input and output capacitors.This module provides a precisely regulated output voltageprogrammable via one external resistor rom 0.6VDC to5.0VDC over a 4.5V to 20V wide input voltage. The typicalapplication schematic is shown in Figure 18.

The LTM4601 has an integrated constant on-time currentmode regulator, ultralow RDS(ON) FETs with ast switch-ing speed and integrated Schottky diodes. The typicalswitching requency is 850kHz at ull load. With currentmode control and internal eedback loop compensation,

the LTM4601 module has sucient stability margins andgood transient perormance under a wide range o operat-ing conditions and with a wide range o output capacitors,even all ceramic output capacitors.

Current mode control provides cycle-by-cycle ast currentlimit. Besides, oldback current limiting is provided in anovercurrent condition while VFB drops. Internal overvolt-age and undervoltage comparators pull the open-drainPGOOD output low i the output eedback voltage exits a±10% window around the regulation point. Furthermore,

in an overvoltage condition, internal top FET Q1 is turnedo and bottom FET Q2 is turned on and held on until theovervoltage condition clears.

Pulling the RUN pin below 1V orces the controller into itsshutdown state, turning o both Q1 and Q2. At low loadcurrent, the module works in continuous current mode by

deault to achieve minimum output ripple voltage.

When DRVCC pin is connected to INTVCC an integrated5V linear regulator powers the internal gate drivers. I a5V external bias supply is applied on the DRVCC pin, thenan eciency improvement will occur due to the reducedpower loss in the internal linear regulator. This is especiallytrue at the high end o the input voltage range.

The LTM4601 has a very accurate dierential remotesense amplier with very low oset. This provides orvery accurate output voltage sensing at the load. The

MPGM pin, MARG0 pin and MARG1 pin are used to sup-port voltage margining, where the percentage o marginis programmed by the MPGM pin, and the MARG0 andMARG1 select margining.

The PLLIN pin provides requency synchronization o thedevice to an external clock. The TRACK/SS pin is usedor power supply tracking and sot-start programming.

OPERATION

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The typical LTM4601 application circuit is shown in Fig-ure 18. External component selection is primarily deter-mined by the maximum load current and output voltage.

Reer to Table 2 or specic external capacitor requirementsor a particular application.

VIN to VOUT Step-Down Ratios

There are restrictions in the maximum VIN to VOUT stepdown ratio that can be achieved or a given input voltage.These constraints are shown in the Typical PerormanceCharacteristics curves labeled VIN to VOUT Step-DownRatio. Note that additional thermal derating may apply. Seethe Thermal Considerations and Output Current Derating

section o this data sheet.

Output Voltage Programming and Margining

The PWM controller has an internal 0.6V reerence voltage.As shown in the Block Diagram, a 1M and a 60.4k 0.5%internal eedback resistor connects VOUT and VFB pinstogether. The VOUT_LCL pin is connected between the 1Mand the 60.4k resistor. The 1M resistor is used to protectagainst an output overvoltage condition i the VOUT_LCL pin is not connected to the output, or i the remote senseamplier output is not connected to VOUT_LCL. In these

cases, the output voltage will deault to 0.6V. Adding aresistor RSET rom the VFB pin to SGND pin programsthe output voltage:

VOUT = 0.6V •60.4k+RSET

RSET

Table 1. RSET Standard 1% Resistor Values vs VOUT

RSET (kW)

Open 60.4 40.2 30.1 25.5 19.1 13.3 8.25

VOUT (V)

0.6 1.2 1.5 1.8 2 2.5 3.3 5

The MPGM pin programs a current that when multipliedby an internal 10k resistor sets up the 0.6V reerence ±oset or margining. A 1.18V reerence divided by the

RPGM resistor on the MPGM pin programs the current.Calculate VOUT(MARGIN):

VOUT(MARGIN)=

%VOUT100

•VOUT

where %VOUT is the percentage o VOUT you want tomargin, and VOUT(MARGIN) is the margin quantity in volts:

RPGM =VOUT0.6V

•1.18V

VOUT(MARGIN)•10k

where RPGM is the resistor value to place on the MPGMpin to ground.

The margining voltage, VOUT(MARGIN), will be added orsubtracted rom the nominal output voltage as determinedby the state o the MARG0 and MARG1 pins. See the truthtable below:

MARG1 MARG0 MODE

LOW LOW NO MARGIN

LOW HIGH MARGIN UP

HIGH LOW MARGIN DOWN

HIGH HIGH NO MARGIN

Input Capacitors

LTM4601 module should be connected to a low AC imped-ance DC source. Input capacitors are required to be placedadjacent to the module. In Figure 18, the 10µF ceramic inputcapacitors are selected or their ability to handle the largeRMS current into the converter. An input bulk capacitoro 100µF is optional. This 100µF capacitor is only neededi the input source impedance is compromised by long

inductive leads or traces.

APPLICATIONS INFORMATION

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For a buck converter, the switching duty-cycle can beestimated as:

D= VOUT

VIN

Without considering the inductor ripple current, the RMScurrent o the input capacitor can be estimated as:

ICIN(RMS) =

IOUT(MAX)

η%• D• 1–D( )

In the above equation, η% is the estimated eciency othe power module. CIN can be a switcher-rated electrolyticaluminum capacitor, OS-CON capacitor or high value ce-

ramic capacitor. Note the capacitor ripple current ratingsare oten based on temperature and hours o lie. Thismakes it advisable to properly derate the input capacitor,or choose a capacitor rated at a higher temperature thanrequired. Always contact the capacitor manuacturer orderating requirements.

In Figure 18, the 10µF ceramic capacitors are togetherused as a high requency input decoupling capacitor. In atypical 12A output application, three very low ESR, X5R orX7R, 10µF ceramic capacitors are recommended. These

decoupling capacitors should be placed directly adjacentto the module input pins in the PCB layout to minimizethe trace inductance and high requency AC noise. Each10µF ceramic is typically good or 2A to 3A o RMS ripplecurrent. Reer to your ceramics capacitor catalog or theRMS current ratings.

Multiphase operation with multiple LTM4601 devices inparallel will lower the eective input RMS ripple currentdue to the interleaving operation o the regulators. Appli-cation Note 77 provides a detailed explanation. Reer toFigure 2 or the input capacitor ripple current reduction as

a unction o the number o phases. The gure providesa ratio o RMS ripple current to DC load current as unc-tion o duty cycle and the number o paralleled phases.

Pick the corresponding duty cycle and the number o phasesto arrive at the correct ripple current value. For example,the 2-phase parallel LTM4601 design provides 24A at 2.5V

output rom a 12V input. The duty cycle is DC = 2.5V/12V= 0.21. The 2-phase curve has a ratio o ~0.25 or a dutycycle o 0.21. This 0.25 ratio o RMS ripple current to aDC load current o 24A equals ~6A o input RMS ripplecurrent or the external input capacitors.

Output Capacitors

The LTM4601 is designed or low output ripple voltage.The bulk output capacitors dened as COUT are chosenwith low enough eective series resistance (ESR) to meet

the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, a low ESR polymercapacitor or a ceramic capacitor. The typical capacitance is200µF i all ceramic output capacitors are used. Additionaloutput ltering may be required by the system designeri urther reduction o output ripple or dynamic transientspikes is required. Table 2 shows a matrix o dierentoutput voltages and output capacitors to minimize thevoltage droop and overshoot during a 5A/µs transient.The table optimizes total equivalent ESR and total bulkcapacitance to maximize transient perormance.

Figure 2. Normalized Input RMS Ripple Currentvs Duty Cycle or One to Six Modules (Phases)


DUTY CYCLE (VOUT /VIN)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

0.6

0.5

0.4

0.3

0.2

0.1

0

4601 F02

R M S I N P U T R I P P L E C U R R E N T

D C L O A D C U R R E N T

6-PHASE4-PHASE

12-PHASE

3-PHASE2-PHASE1-PHASE

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Multiphase operation with multiple LTM4601 devices inparallel will lower the eective output ripple current due tothe interleaving operation o the regulators. For example,

each LTM4601’s inductor current in a 12V to 2.5V multi-phase design can be read rom the Inductor Ripple Currentvs Duty Cycle graph (Figure 3). The large ripple current

at low duty cycle and high output voltage can be reducedby adding an external resistor rom SET to ground whichincreases the requency. I the duty cycle is DC = 2.5V/12V

= 0.21, the inductor ripple current or 2.5V output at 21%duty cycle is ~6A in Figure 3.

Figure 4 provides a ratio o peak-to-peak output ripple cur-rent to the inductor current as a unction o duty cycle andthe number o paralleled phases. Pick the correspondingduty cycle and the number o phases to arrive at the correctoutput ripple current ratio value. I a 2-phase operation ischosen at a duty cycle o 21%, then 0.6 is the ratio. This0.6 ratio o output ripple current to inductor ripple o 6Aequals 3.6A o eective output ripple current. Reer to

Application Note 77 or a detailed explanation o outputripple current reduction as a unction o paralleled phases.

The output ripple voltage has two components that arerelated to the amount o bulk capacitance and eectiveseries resistance (ESR) o the output bulk capacitance.

Figure 4. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI, Dlr = Each Phase’s Inductor Current

Figure 3. Inductor Ripple Current vs Duty Cycle


DUTY CYCLE (VOUT /VIN)

00

I L

( A )

2

4

6

8

10

12

0.2 0.4 0.6 0.8

4601 F03

2.5V OUTPUT

5V OUTPUT

1.8V OUTPUT

1.5V OUTPUT

1.2V OUTPUT

3.3V OUTPUT WITH130k ADDED FROMVOUT TO fSET

5V OUTPUT WITH100k ADDED FROMfSET TO GND

DUTY CYCLE (VO /VIN)

0.1 0.15 0.2 0.25 0.350.3 0.4 0 .45 0.5 0 .55 0 .6 0 .65 0.7 0 .75 0 .8 0.85 0.9

1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.40

0.35

0.30

0.250.20

0.15

0.10

0.05

0

4601 F04

6-PHASE

4-PHASE3-PHASE

2-PHASE1-PHASE

P E A K - T O - P E A K

O U T P U T

R I P P L E

C U R R E N T

D I r

R A

T I O =

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Thereore, the output ripple voltage can be calculated withthe known eective output ripple current. The equation:ΔVOUT(P-P) ≈ (ΔIL /(8 • f • m • COUT) + ESR • ΔIL), where

is requency and m is the number o parallel phases. Thiscalculation process can be easily accomplished by usingLTpowerCAD™.

Fault Conditions: Current Limit and OvercurrentFoldback

LTM4601 has a current mode controller, which inher-ently limits the cycle-by-cycle inductor current not only insteady-state operation, but also in response to transients.

To urther limit current in the event o an overload condi-

tion, the LTM4601 provides oldback current limiting. I theoutput voltage alls by more than 50%, then the maximumoutput current is progressively lowered to about one sixtho its ull current limit value.

Sot-Start and Tracking

The TRACK/SS pin provides a means to either sot-startthe regulator or track it to a dierent power supply. Acapacitor on this pin will program the ramp rate o theoutput voltage. A 1.5µA current source will charge up theexternal sot-start capacitor to 80% o the 0.6V internalvoltage reerence plus or minus any margin delta. This willcontrol the ramp o the internal reerence and the outputvoltage. The total sot-start time can be calculated as:

tSOFTSTART = 0.8 • 0.6V ±VOUT(MARGIN)( ) •

CSS1.5µA

When the RUN pin alls below 1.5V, then the TRACK/SSpin is reset to allow or proper sot-start control when theregulator is enabled again. Current oldback and orcedcontinuous mode are disabled during the sot-start pro-

cess. The sot-start unction can also be used to controlthe output ramp up time, so that another regulator canbe easily tracked to it.

Output Voltage Tracking

Output voltage tracking can be programmed externally

using the TRACK/SS pin. The output can be tracked up anddown with another regulator. The master regulator’s outputis divided down with an external resistor divider that is thesame as the slave regulator’s eedback divider. Figure 5shows an example o coincident tracking. Ratiometricmodes o tracking can be achieved by selecting dierentresistor values to change the output tracking ratio. Themaster output must be greater than the slave output orthe tracking to work. Figure 6 shows the coincident outputtracking characteristics.

Figure 5. Coincident Tracking Schematic

Figure 6. Coincident Output Tracking Characteristics

OUTPUT

VOLTAGE

TIME4601 F06

MASTER OUTPUT

SLAVE OUTPUT


VOUT

VFB

MARG0

MARG1

VOUT_LCL

DIFFVOUT

VOSNS+

VOSNS–

PGOOD

MPGM

RUN

COMP

INTVCC

DRVCC

TRACK/SS

TRACK CONTROL

PLLIN

LTM4601

RSET40.2k

100k

R1

40.2k

MASTER

OUTPUT

R2

60.4k

COUT

SLAVE OUTPUT

4601 F05

CIN

VIN

fSETPGNDSGND

VIN

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Run Enable

The RUN pin is used to enable the power module. The

pin has an internal 5.1V Zener to ground. The pin can bedriven with a logic input not to exceed 5V.

The RUN pin can also be used as an undervoltage lock out(UVLO) unction by connecting a resistor divider rom theinput supply to the RUN pin:

VUVLO =

R1+R2

R2•1.5V

See Figure 1, Simplied Block Diagram.

Power Good

The PGOOD pin is an open-drain pin that can be used tomonitor valid output voltage regulation. This pin monitorsa ±10% window around the regulation point and trackswith margining.

COMP Pin

This pin is the external compensation pin. The modulehas already been internally compensated or most outputvoltages. Table 2 is provided or most application require-ments. LTpowerCAD is available or other control loop

optimization.

PLLIN

The power module has a phase-locked loop comprisedo an internal voltage controlled oscillator and a phasedetector. This allows the internal top MOSFET turn-onto be locked to the rising edge o an external clock. Therequency range is ±30% around the operating requencyo 850kHz. A pulse detection circuit is used to detect aclock on the PLLIN pin to turn on the phase-locked loop.The pulse width o the clock has to be at least 400ns andat least 2V in amplitude. The PLLIN pin must be drivenrom a low impedance source such as a logic gate locatedclose to the pin. During the start-up o the regulator, thephase-locked loop unction is disabled.

INTVCC and DRVCC Connection

An internal low dropout regulator produces an internal

5V supply that powers the control circuitry and DRVCC or driving the internal power MOSFETs. Thereore, ithe system does not have a 5V power rail, the LTM4601can be directly powered by VIN. The gate driver currentthrough the LDO is about 20mA. The internal LDO powerdissipation can be calculated as:

PLDO_LOSS = 20mA • (VIN – 5V)

The LTM4601 also provides the external gate driver volt-age pin DRVCC. I there is a 5V rail in the system, it isrecommended to connect DRVCC pin to the external 5V

rail. This is especially true or higher input voltages. Donot apply more than 6V to the DRVCC pin. A 5V output canbe used to power the DRVCC pin with an external circuitas shown in Figure 16.

Parallel Operation o the Module

The LTM4601 device is an inherently current mode con-trolled device. Parallel modules will have very good currentsharing. This will balance the thermals on the design. Thevoltage eedback equation changes with the variable N asmodules are paralleled:

VOUT = 0.6V

60.4k

N+RSET

RSET

N is the number o paralleled modules.

Figure 19 shows an LTM4601 and an LTM4601-1 used in aparallel design. The 2nd LTM4601 device does not requirethe remote sense amplier, thereore, the LTM4601-1 deviceis used. An LTM4601 device can be used without the diamp. VOSNS

+ can be tied to ground and the VOSNS– can be

tied to INTVCC. DIFFVOUT can foat. When using multipleLTM4601-1 devices in parallel with an LTM4601, limit thenumber to ve or a total o six modules in parallel.


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Figure 7. 1.5V Power Loss Figure 8. 3.3V Power Loss

Figure 9. No Heat Sink 5VIN Figure 10. BGA Heat Sink 5VIN


Thermal Considerations and Output Current Derating

The power loss curves in Figures 7 and 8 can be used

in coordination with the load current derating curves inFigures 9 to 14 or calculating an approximate θJA or themodule with various heat sinking methods. Thermal modelsare derived rom several temperature measurements atthe bench and thermal modeling analysis. Thermal Ap-plication Note 103 provides a detailed explanation o theanalysis or the thermal models and the derating curves.Tables 3 and 4 provide a summary o the equivalent θJA or the noted conditions. These equivalent θJA parametersare correlated to the measured values, and are improvedwith air fow. The case temperature is maintained at 100°C

or below or the derating curves. The maximum casetemperature o 100°C is to allow or a rise o about 13°Cto 25°C inside the µModule with a thermal resistance θJC

rom junction to case between 6°C/W to 9°C/W. This willmaintain the maximum junction temperature inside theµModule regulator below 125°C.

Saety Considerations

The LTM4601 modules do not provide isolation romVIN to VOUT. There is no internal use. I required, aslow blow use with a rating twice the maximum inputcurrent needs to be provided to protect each unit romcatastrophic ailure.

LOAD CURRENT (A)

00

P O W E R L O S S ( W )

1.0

2.0

3.0

2 4 6 8

4601 F07

10

4.0

5.0

0.5

1.5

2.5

3.5

4.5

12

5VIN

20VIN

12VIN

LOAD CURRENT (A)

00

P O W E R L O S S ( W )

1

2

3

4

6

2 4 6 8

4601 F08

10 12

5

20VIN

12VIN

AMBIENT TEMPERATURE (°C)

500

M A X I M U M L O

A D C U R R E N T ( A )

2

4

6

8

10

12

60 70 80 90

4600 F09

100

5VIN, 1.5VOUT 0LFM5VIN, 1.5VOUT 200LFM5VIN, 1.5VOUT 400LFM


500

M A X I M U M L O

A D C U R R E N T ( A )

2

4

6

8

10

12

60 70 80 90

4601 F10

100


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Figure 11. No Heat Sink 12VIN Figure 12. BGA Heat Sink 12VIN

Figure 13. 12VIN, 3.3VOUT, No Heat Sink Figure 14. 12VIN, 3.3VOUT, BGA Heat Sink



500

M A X I M U M L

O A D C U R R E N T ( A )

2

4

6

8

10

12

60 70 80 90

4601 F11

100



500

M A X I M U M L


2

4

6

8

10

12

60 70 80 90

4601 F12

100



400

M A X I M

U M L


2

4

6

8

10

12

60 80

4601 F13

100

0LFM200LFM400LFM


400

M A X I M

U M L


2

4

6

8

10

12

60 80

4601 F14

100

0LFM200LFM400LFM

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Table 2. Output Voltage Response Versus Component Matrix (Reer to Figure 18), 0A to 6A Load Step

TYPICAL MEASURED VALUES

COUT1 VENDORS PART NUMBER COUT2 VENDORS PART NUMBER

TDK C4532X5R0J107MZ (100µF, 6.3V) SANYO POS CAP 6TPE330MIL (330µF, 6.3V)TAIYO YUDEN JMK432BJ107MU-T ( 100µF, 6.3V) SANYO POS CAP 2R5TPE470M9 (470µF, 2.5V)

TAIYO YUDEN JMK316BJ226ML-T501 ( 22µF, 6.3V) SANYO POS CAP 4TPE470MCL (470µF, 4V)

VOUT (V)

CIN (CERAMIC)

CIN (BULK)

COUT1 (CERAMIC)

COUT2 (BULK)

CCOMP

C3

VIN (V)

DROOP(mV)

PEAK TOPEAK (mV)

RECOVERYTIME (µs)

LOAD STEP(A/µs)

RSET(kW)

1.2 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE 47pF 5 70 140 30 6 60.4

1.2 2 × 10µF 25V 150µF 35V 1 × 100µF 6.3V 470µF 2.5V NONE 100pF 5 35 70 20 6 60.4


1.2 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 100pF 5 40 93 30 6 60.4




1.2 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 100pF 12 49 98 20 6 60.41.5 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE 100pF 5 48 100 35 6 40.2












1.8 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE 100pF 12 60 120 30 6 30.11.8 2 × 10µF 25V 150µF 35V 1 × 100µF 6.3V 470µF 2.5V NONE 100pF 12 60 120 30 6 30.1





2.5 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE NONE 5 57 116 30 6 19.1



2.5 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE NONE 12 51 102 30 6 19.1











5 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 22pF 15 188 375 25 6 8.25

5 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 22pF 20 159 320 25 6 8.25


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Table 3. 1.5V Output at 12A

DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK θJA (°C/W) LGA θJA (°C/W) BGA

Figures 9, 11 5, 12 Figure 7 0 None 15.2 15.7

Figures 9, 11 5, 12 Figure 7 200 None 14 14.5

Figures 9, 11 5, 12 Figure 7 400 None 12 12.5

Figures 10, 12 5, 12 Figure 7 0 BGA Heat Sink 13.9 14.4



Table 4. 3.3V Output at 12A

DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK θJA (°C/W) LGA θJA (°C/W) BGA

Figure 13 12 Figure 8 0 None 15.2 15.7



Figure 14 12 Figure 8 0 BGA Heat Sink 13.9 14.4



Heat Sink Manuacturer

Aavid Thermalloy Part No: 375424B00034G Phone: 603-224-9988


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Layout Checklist/Example

The high integration o LTM4601 makes the PCB board

layout very simple and easy. However, to optimize its electri-cal and thermal perormance, some layout considerationsare still necessary.

• Use large PCB copper areas for high current path, in-cluding VIN, PGND and VOUT. It helps to minimize thePCB conduction loss and thermal stress.

• Place high frequency ceramic input and output capaci-tors next to the VIN, PGND and VOUT pins to minimizehigh requency noise.

• Place a dedicated power ground layer underneath the

unit. Reer requency synchronization source to powerground.

• To minimize the via conduction loss and reduce modulethermal stress, use multiple vias or interconnectionbetween top layer and other power layers.

• Do not put vias directly on pads unless they are capped.

• Use a separated SGND copper area for components

connected to signal pins. Connect the SGND to PGNDunderneath the unit.

Figure 15 gives a good example o the recommended layout.

Frequency Adjustment

The LTM4601 is designed to typically operate at 850kHzacross most input conditions. The SET pin is normallylet open. The switching requency has been optimizedor maintaining constant output ripple noise over mostoperating ranges. The 850kHz switching requency andthe 400ns minimum o time can limit operation at higherduty cycles like 5V to 3.3V, and produce excessive induc-tor ripple currents or lower duty cycle applications like20V to 5V. The 5VOUT and 3.3VOUT drop out curves aremodied by adding an external resistor on the SET pin toallow or lower input voltage operation, or higher inputvoltage operation.

SIGNAL

GND

VOUT

VIN

GND

COUT

CIN CIN

COUT

4601 F15

Figure 15. Recommended Layout (LGA and BGA PCB Layouts Are Identicalwith the Exception o Circle Pads or BGA, See Package Description.)


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Example or 5V Output

LTM4601 minimum on-time = 100ns

tON = ((VOUT • 10pF)/ISET), or VOUT > 4.8V use 4.8V.LTM4601 minimum o-time = 400nstOFF = t – tON, where t = 1/Frequency

Duty Cycle = tON /t or VOUT /VIN

Equations or setting requency:

ISET = (VIN /(3 • RSET)), or 20V operation, ISET = 170µA,tON = ((4.8 • 10pF)/ISET), tON = 282ns, where the internalRSET is 39.2k. Frequency = (VOUT /(VIN • tON)) = (5V/(20• 282ns)) ~ 886kHz. The inductor ripple current beginsto get high at the higher input voltages due to a largervoltage across the inductor. This is noted in the InductorRipple Current vs Duty Cycle graph (Figure 3) where IL ≈10A at 25% duty cycle. The inductor ripple current can belowered at the higher input voltages by adding an externalresistor rom SET to ground to increase the switchingrequency. An 8A ripple current is chosen, and the totalpeak current is equal to 1/2 o the 8A ripple current plusthe output current. The 5V output current is limited to 8A,so the total peak current is less than 12A. This is below the14A peak specied value. A 100k resistor is placed romSET

to ground, and the parallel combination o 100k and39.2k equates to 28k. The ISET calculation with 28k and20V input voltage equals 238µA. This equates to a tON o200ns. This will increase the switching requency rom~886kHz to ~1.25MHz or the 20V to 5V conversion. Theminimum on-time is above 100ns at 20V input. Sincethe switching requency is approximately constant overinput and output conditions, then the lower input voltagerange is limited to 10V or the 1.25MHz operation due tothe 400ns minimum o-time. Equation: tON = (VOUT /VIN)• (1/Frequency) equates to a 400ns on-time, and a 400ns

o-time. The VIN to VOUT Step-Down Ratio curve refectsan operating range o 10V to 20V or 1.25MHz operationwith a 100k resistor to ground, and an 8V to 16V operationor SET foating. These modications are made to providewider input voltage ranges or the 5V output designs whilelimiting the inductor ripple current, and maintaining the400ns minimum o-time.

Example or 3.3V Output

LTM4601 minimum on-time = 100ns

tON = ((VOUT • 10pF)/ISET)LTM4601 minimum o-time = 400nstOFF = t – tON, where t = 1/Frequency

Duty Cycle (DC) = tON /t or VOUT /VIN

Equations or setting requency:

ISET = (VIN /(3 • RSET)), or 20V operation, ISET = 170µA,tON = ((3.3 • 10pf)/ISET), tON = 195ns, where the internalRSET is 39.2k. Frequency = (VOUT /(VIN • tON)) = (3.3V/ (20 • 195ns)) ~ 846kHz. The minimum on-time and mini-mum o-time are within specication at 195ns and 980ns.The 4.5V minimum input or converting 3.3V output willnot meet the minimum o-time specication o 400ns.tON = 868ns, Frequency = 850kHz, tOFF = 315ns.

Solution

Lower the switching requency at lower input voltages toallow or higher duty cycles, and meet the 400ns minimumo-time at 4.5V input voltage. The o-time should be about500ns, which includes a 100ns guard band. The duty cycleor (3.3V/4.5V) = ~73%. Frequency = (1 – DC)/tOFF or

(1 – 0.73)/500ns = 540kHz. The switching requencyneeds to be lowered to 540kHz at 4.5V input. tON = DC/ requency, or 1.35µs. The SET pin voltage is 1/3 o VIN, andthe ISET current equates to 38µA with the internal 39.2k.The ISET current needs to be 24µA or 540kHz opera-tion. A resistor can be placed rom VOUT to SET to lowerthe eective ISET current out o the SET pin to 24µA.The SET pin is 4.5V/3 =1.5V and VOUT = 3.3V, thereore130k will source 14µA into the SET node and lower theISET current to 24µA. This enables the 540kHz operationand the 4.5V to 20V input operation or down converting to

3.3V output. The requency will scale rom 540kHz to 1.1MHz over this input range. This provides or an eectiveoutput current o 8A over the input range.


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Figure 16. 5V at 8A Design Without Dierential Amplifer


Figure 17. 3.3V at 10A Design

VOUT

VFB

MARG0

MARG1

VOUT_LCL

NC3

NC1

NC2

PGOOD

MPGM

RUN

COMP

INTVCC

DRVCC

TRACK/SSPLLIN

LTM4601-1

R1392k

1%

RfSET100k

RSET8.25k

COUT1100µF6.3VSANYO POSCAP

4601 F16

VOUT5V8A

TRACK/SS CONTROL

REVIEW TEMPERATUREDERATING CURVE

C3 100pF

REFER TOTABLE 2

CIN10µF25V×2

IMPROVEEFFICIENCY

FOR ≥12V INPUT

R4100k

R2100k VIN

VOUT

fSETPGND

MARGIN CONTROL

SGND

5% MARGIN

VIN10V TO 20V

DUALCMSSH-3C3

SOT-323

+

VOUT

VFB

MARG0

MARG1

VOUT_LCL

DIFFVOUT

VOSNS+

VOSNS–

PGOOD

MPGM

RUN

COMP

INTVCC

DRVCC

TRACK/SSPLLIN

LTM4601

R1392k

R4100k

R2100k

RSET13.3k

RfSET130k

MARGIN CONTROL

COUT1100µF6.3VSANYO POSCAP

4601 F17

VOUT

3.3V10A

TRACK/SS CONTROL

C3 100pF

CIN10µF25V×3

VIN

VOUT

fSETPGNDSGND

5% MARGIN

VIN4.5V TO 16V

REVIEW TEMPERATUREDERATING CURVE

+

PGOOD

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Figure 19. 2-Phase Parallel, 1.5V at 24A Design


Figure 18. Typical 4.5V to 20V, 1.5V at 12A Design

VOUT

VFB

MARG0

MARG1

VOUT_LCL

DIFFVOUT

VOSNS+

VOSNS–

PGOOD

MPGM

RUN

COMP

INTVCC

DRVCC

TRACK/SSPLLIN

LTM4601

R1392k

R4

100k

R2

100k

RSET40.2k

COUT1100µF6.3V

C50.01µF

COUT2470µF6.3V

MARGINCONTROL

4601 F18

VOUT1.5V12A

CLOCK SYNC

C3 100pF

REFER TOTABLE 2 FORDIFFERENT

OUTPUTVOLTAGE

CINBULK

OPT CIN10µF25V×3 CER

VIN

VOUT

fSETPGNDSGND

5% MARGIN

VIN4.5V TO 20V

REVIEW TEMPERATURE

DERATING CURVE

+

+

PGOOD

ON/OFF

VOUT

VFB

MARG0

MARG1

VOUT_LCL

DIFFVOUT

VOSNS

+

VOSNS–

PGOOD

MPGM

RUN

COMP

INTVCC

DRVCC

TRACK/SSPLLIN

LTM4601

R1392k

392k

R4100k

R2100k

VOUT

RSET20k

C322µF6.3V

C4470µF

6.3V

VOUT1.5V24A

CLOCK SYNC0° PHASE

CLOCK SYNC180° PHASE

C6 220pF

MARGINCONTROL

TRACK/SS CONTROL

TRACK/SS CONTROL

REFER TOTABLE 2

REFER TOTABLE 2

C5*100µF

25V

C1

0.1µFC2

10µF25V×2

VIN

fSETPGNDSGND

VOUT

VFBMARG0

MARG1

VOUT_LCL

NC3

NC2

NC1

PGOOD

MPGMRUN

COMP

INTVCC

DRVCC

TRACK/SSPLLIN

LTM4601-1

VIN

fSETPGNDSGND

5%MARGIN

LTC6908-1

VIN4.5V TO 20V

4.5V TO 20V

PGOOD

2-PHASEOSCILLATOR

100pF

C3

22µF6.3V

4601 F19

C70.033µF

C810µF25V×2

*C5 OPTIONAL TO REDUCE ANY LC RINGING.NOT NEEDED FOR LOW INDUCTANCE PLANE CONNECTION

+

C4

470µF6.3V

+

+

V+

GND

SET

6

5

4

1

2

3

OUT1

OUT2

MOD

VOUT = 0.6VRSET

60.4k

N+ RSET

N = NUMBER OF PHASES

118k1%

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4 -

P h a s e ,

F o u r O u t p

u t s ( 3

. 3 V

, 2

. 5 V

, 1

. 8 V a n d 1

. 5 V ) w i t h C o i n c i d e n t T r a c k i n g

TYPICAL APPLICATIONS

V O U T

V F B

M A R G 0

M A R G 1

V O U T_

L C L

D I F F V O U T

V O S N S +

V O S N S –

P G O O D

M P G M

R U N

C O M P

I N T V C C

D R V C C

T R A C K / S S

P L L I N

L T M 4 6 0 1

R 9 3 9 2 k

R 1 1

1 0 0 k

R 1 0

1 0 0 k

R 1 8

1 9 . 1

k

C 1 6

2 2 µ F

6 . 3

V

C 1 4

1 0 µ F

2 5 V

× 3

3 . 3

V2 . 5

V A T 1 2

A

R 2 3

6 0 . 4

k

C 1 5

4 7 0 µ F

6 . 3

V

M A R G I N

C O N T R O L

C L O C K S

Y N C 2

C 1 8 1 0 0 p F

R E F E R T O

T A B L E 2

V I N

f S E T

P G N D

S G N

D

5 % M

A R G I N

+

P G O O D

8 V T O 1 6 V

O N / O F F

V O U T

V F B

M A R G 0

M A R G 1

V O U T_

L C L

D I F F V O U T

V O S N S +

V O S N S –

P G O O D

M P G M

R U N

C O M P

I N T V C C

D R V C C

T R A C K / S S

P L L I N

L T M 4 6 0 1

R 1 4

3 9 2 k

R 1 6

1 0 0 k

R 1 5

1 0 0 k

R 1 3

4 0 . 2

k

C 1 6

2 2 µ F

6 . 3

V

C 1 4

1 0 µ F

2 5 V

× 3

3 . 3

V

R 2 5

6 0 . 4

k

C 1 5

4 7 0 µ F

6 . 3

V

M A R G I N

C O N T R O L

1 . 5

V A T 1 2

A

C L O C K S

Y N C 4

C 2 4 1 0 0 p F

R E F E R T O

T A B L E 2

V I N

f S E T

P G N D

S G N

D

5 % M

A R G I N

+

P G O O D

8 V T O 1 6 V

O N / O F F

V O U T

V F B

M A R G 0

M A R G 1

V O U T_

L C L

D I F F V O U T

V O S N S +

V O S N S –

P G O O D

M P G M

R U N

C O M P

I N T V C C

D R V C C

T R A C K / S S

P L L I N

L T M 4 6 0 1

R 1 3 9 2 k

R 3

1 0 0 k

R 2

1 0 0 k

R 1 2

3 0 . 1

k

C 3 2 2 µ F

6 . 3

V

C 2 1 0 µ F

2 5 V

× 3

3 . 3

V

R 2 1

6 0 . 4

k

R 1 9

3 0 . 1

k

C 4 4 7 0 µ F

6 . 3

V

M A R G I N

C O N T R O L

1 . 8

V A T 1 2 A

C L O C K S Y N C 3

C 8 1 0 0 p F

R E F E R T O

T A B L E 2

V I N

f S E T

P G N D

S G N D

5 % M

A R G I N

+

P G O O D

8 V T O 1 6 V

O N / O F F

R 1 7 5 9 k

C 2 6

0 . 1 µ F

L T C 6 9 0 2

4 - P H A S E

O S C I L L A T O R 3

. 3 V A T 1 0 A

V +

D I V P H O U T 1

O U T 2

S E T

M O D

G N D

O U T 4

O U T 3

V O U T

V F B

M A R G 0

M A R G 1

V O U T_

L C L

D I F F V O U T

V O S N S +

V O S N S –

P G O O D

M P G M

R U N

C O M P

I N T V C C

D R V C C

T R A C K / S S

P L L I N

L T M 4 6 0 1

R 2 7

3 9 2 k

R 7

1 0 0 k

R 6

1 0 0 k

R 8 1 3 . 3

k

C 9 2 2 µ F

6 . 3

V

C 7 0 . 1 5 µ F

C 8 1 0 µ F

2 5 V

× 3

C 1 1

1 0 0 µ F

3 5 V

O P T

C 1 0

4 7 0 µ F

6 . 3

V

M A R G I N

C O N T R O L

T R A C K / S S

C O N T R O L

C L O C K S Y N C 1

C 1 2 1 0 0 p F

R E F E R T O

T A B L E 2

V I N

3 . 3

V

f S E T

P G N D

S G N D

5 % M

A R G I N

+

P G O O D

8 V T O 1 6 V

8 V T O 1 6 V

O N / O F F

+

I N T E R M E D I A T E

B U S

– 4 8 V

I N P U T

R 2 4

1 9 . 1

k

R 2 6

4 0 . 2

k

3 . 3

V

3 . 3

V

3 . 3

V

4 6 0 1 T A 0 2

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PACKAGE DESCRIPTIONPlease reer to http://www.linear.com/designtools/packaging/ or the most recent package drawings.

N O

T E S :

1 .

D I M E N S I O N I N G A N D T O L E R A N C I N G P E R A S M E Y 1 4 . 5

M - 1 9 9 4

2 .

A L L D I M E N S I O N S A R E I N M I L L I M E T E R S

B A L L D E S I G N A T I O N P E R J E S D M S - 0 2 8 A N D J E P 9 5

5 .

P R I M A R Y D A T U M - Z - I S S E A T I N G P L A N E

4 3

D E T A I L S O F P I N # 1 I D E N T I F I E R A R E O P T I O N A L ,

B U T M U S T B E L O C A T E D W I T H I N T H E Z O N E I N D I C A T E D .

T H E P I N # 1 I D E N T I F I E R M A Y B E E I T H E R A M O L D O R

M A R K E D F E A T U R E

P A C K A G E T O

P V I E W

4

P I N “ A 1 ”

C O R N E R

X Y

a a a Z

a a a Z

P A C K A G E B O T T O M V I E W

C ( 0 . 3

0 )

P A D

1

3

S E E N O T E S

S U G G E S T E D P C B L A Y O U T

T O P V I E W

L G A 1 1 8 1 0 1 1 R E V A

L T M X X X X X X

µ M o d u l e

T R A Y P I N

1

B E V

E L

P A C K A G E I N T R A Y L O A D I N G O R I E N T A T I O N

C O M P O N E N T

P I N “ A

1 ”

D E T A I L A

0 . 0 0 0 0

0 . 0

0 0 0

D

0 . 6

3 0 ± 0 . 0

2 5 Ø 1 1 8 x

E

b

e

e

b

F

G

0 . 6

3 5 0

0 . 6

3 5 0

1 . 9

0 5 0

1 . 9

0 5 0

3 . 1 7 5 0

3 . 1 7 5 0

4 . 4

4 5 0

4 . 4

4 5 0

5 . 7

1 5 0

5 . 7

1 5 0

6 . 9

8 5 0

6 . 9 8 5 0

6 . 9 8 5 0

5 . 7 1 5 0

5 . 7 1 5 0

4 . 4 4 5 0

4 . 4 4 5 0

3 . 1 7 5 0

3 . 1 7 5 0

1 . 9 0 5 0

1 . 9 0 5 0

0 . 6 3 5 0

0 . 6 3 5 0

6 . 9

8 5 0

F

G

H

M

L

J

K

E

A

B

C

D

2 1 4 3 5 6 7 1 2

8 9 1 0

1 1

D E T A I L A

0 . 6

3 0 ± 0 . 0

2 5 S Q . 1 1

8 x

L G A P a c

k a g e

1 1 8

- L e a d

( 1 5 m m × 1

5 m m

× 2

. 8 2 m m

)

( R e f e r e n c e

L T C D W G # 0 5 - 0 8 - 1 8 0 1 R e v A )

D E T A I L B

P A C K A G E S I D E V I E W

b b b Z

S

Y

X

e e e

S Y M B O L

A b D E e F G H 1

H 2

a a a b b b

e e e

M I N

2 . 7

2

0 . 6

0

0 . 2 7

2 . 4 5

N O M

2 . 8

2

0 . 6

3

1 5 . 0

0

1 5 . 0

0

1 . 2 7

1 3 . 9 7

1 3 . 9 7

0 . 3

2

2 . 5

0

M A X

2 . 9

2

0 . 6

6

0 . 3 7

2 . 5 5

0 . 1 5

0 . 1

0

0 . 0 5

N O T E S

D I M E N S I O N S

T O T

A L N U M B E R O F L G A P A D S : 1 1 8

D E T A I L B

S U B S T R A T E

M O L D

C A P

Z

H 2

H 1

A

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PACKAGE DESCRIPTIONPlease reer to http://www.linear.com/designtools/packaging/ or the most recent package drawings.

N O T E S :

1 .

D I M E N S I O N I N G A N D T O L E R A N C I N G P E R A S M E Y 1 4 . 5

M - 1 9 9 4

2 .

A L L D I M E N S I O N S A R E I N M I L L I M E T E R S

B A L L D E S I G N A T I O N P E R J E S D M S - 0 2 8 A N D J E P 9 5

5 .

P R I M A R Y D A T U M - Z - I S S E A T I N G P L A N E

6 .

S O L D E R B A L L C O M P O S I T I O N I S 9 6 . 5

% S

n / 3 . 0

% A

g / 0 . 5

% C u

4 3

D E T A I L S O F P I N # 1 I D E N T I F I E R A R E O P T I O N A L ,

B U T M U S T B E L O C A T E D W I T H I N T H E Z O N E I N D I C A T E D .

T H E P I N # 1 I D E N T I F I E R M A Y B E E I T H E R A M O L D O R

M A R K E D F E A T U R E

P A C K A G E T

O P V I E W

4

P I N “ A 1 ”

C O R N E R

X Y

a a a Z

a a a Z

P A C K A G E B O T T O M V I E W

P I N 1

3

S E E N O T E S

S U G G E S T E D P

C B L A Y O U T

T O P V

I E W

B G A 1 1 8 0 1 1 2 R E V A

L T M X X X X X X

µ M o d u l e

T R A Y P I N 1

B E V

E L

P A C K A G E I N T R A Y L O A D I N G O R I E N T A T I O N

C O M P O N E

N T

P I N “ A

1 ”

D E T A I L A

0 . 0 0 0 0

0 . 0

0 0 0

D E T A

I L A

Ø b ( 1 1 8 P L A C E S

)

D E T A

I L B

S U B S T R A T E

0 . 2

7 –

0 . 3

7

2 . 4

5 –

2 . 5

5

/ / b b b Z

D

A

A 1

b 1

c c c Z

D E T A I L B

P A C K A G E S I D E V I E W

M O L

D

C A P

Z

M

X

Y

Z

d d d

M

Z

e e e

0 . 6

3 0 ± 0 . 0

2 5 Ø 1 1 8 x

S Y M B O L

A A 1

A 2 b b

1 D E e F G a a a

b b b

c c c

d d d

e e e

M I N

3 . 2

2

0 . 5

0

2 . 7

2

0 . 6

0

0 . 6

0

N O M

3 . 4

2

0 . 6

0

2 . 8

2

0 . 7 5

0 . 6

3

1 5 . 0

1 5 . 0

1 . 2 7

1 3 . 9 7

1 3 . 9 7

M A X

3 . 6

2

0 . 7

0

2 . 9

2

0 . 9

0

0 . 6

6

0 . 1 5

0 . 1

0

0 . 2

0

0 . 3

0

0 . 1 5

N O T E S

D I M E N S I O N S

T O T A L N U M B E R O F B A L L S : 1 1 8

E

b

e

e

b

A 2

F

G

B G A P a c k a g e

1 1 8 - L e a d ( 1 5 m m × 1

5 m m × 3 . 4

2 m m )

( R e f e r e n c e L T C D W G # 0 5 - 0 8 - 1 9 0 3 R e v A )

0 . 6

3 5 0

0 . 6

3 5 0

1 . 9

0 5 0

1 . 9

0 5 0

3 . 1

7 5 0

3 . 1

7 5 0

4 . 4

4 5 0

4 . 4

4 5 0

5 . 7

1 5 0

5 . 7

1 5 0

6 . 9

8 5 0

6 . 9 8 5 0

6 . 9 8 5 0

5 . 7 1 5 0

5 . 7 1 5 0

4 . 4 4 5 0

4 . 4 4 5 0

3 . 1 7 5 0

3 . 1 7 5 0

1 . 9 0 5 0

1 . 9 0 5 0

0 . 6 3 5 0

0 . 6 3 5 0

6 . 9

8 5 0

F

G

H

M

L

J

K

E

A

B

C

D

2 1 4 3 5 6 7 1 2

8 9 1 0

1 1

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PACKAGE DESCRIPTION

Table 5. Pin Assignment (Arranged by Pin Number)

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION

A1 VIN

B1 VIN

C1 VIN

D1 PGND E1 PGND F1 PGND

A2 VIN B2 VIN C2 VIN D2 PGND E2 PGND F2 PGND





A7 INTVCC B7 – C7 – D7 – E7 PGND F7 PGND

A8 PLLIN B8 – C8 – D8 – E8 – F8 PGND

A9 TRACK/SS B9 – C9 – D9 – E9 – F9 PGND

A10 RUN B10 – C10 – D10 – E10 – F10 –

A11 COMP B11 – C11 – D11 – E11 – F11 –

A12 MPGM B12 SET C12 MARG0 D12 MARG1 E12 DRVCC F12 VFB

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION

G1 PGND H1 PGND J1 VOUT K1 VOUT L1 VOUT M1 VOUT









G10 – H10 – J10 VOUT K10 VOUT L10 VOUT M10 VOUT

G11 – H11 – J11 – K11 VOUT L11 VOUT M11 VOUT

G12 PGOOD H12 SGND J12 VOSNS+ K12 DIFFVOUT L12 VOUT_LCL M12 VOSNS–

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PIN NAME

A1A2A3A4A5A6

VINVINVINVINVINVIN

B1B2B3B4B5B6

VINVINVINVINVINVIN

C1C2C3C4C5C6

VINVINVINVINVINVIN

Table 6. Pin Assignment (Arranged by Pin Function)

PIN NAME

D1D2D3D4D5D6

PGNDPGNDPGNDPGNDPGNDPGND

E1E2E3E4E5E6E7

PGNDPGNDPGNDPGNDPGNDPGNDPGND

F1F2F3F4F5F6F7F8F9

PGNDPGNDPGNDPGNDPGNDPGNDPGNDPGNDPGND

G1G2G3G4G5G6G7G8G9


H1H2H3H4H5H6H7H8H9


PIN NAME

J1J2J3J4J5J6J7J8J9J10

VOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUT

K1K2K3K4K5

K6K7K8K9K10K11

VOUTVOUTVOUTVOUTVOUT

VOUTVOUTVOUTVOUTVOUTVOUT

L1L2L3L4L5L6L7L8L9

L10L11

VOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUT

VOUTVOUT

M1M2M3M4M5M6M7M8M9M10M11

VOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUT

PIN NAME

A7A8A9A10A11A12

INTVCCPLLINTRACK/SSRUNCOMPMPGM

B12 SET

C12 MARG0

D12 MARG1

E12 DRVCC

F12 VFB

G12 PGOOD

H12 SGNDJ12 VOSNS

+

K12 DIFFVOUT

L12 VOUT_LCL

M12 VOSNS–

PIN NAME

B7B8B9B10B11

-----

C7C8C9C10C11

-----

D7D8D9D10D11

-----

E8E9E10E11

----

F10F11

--

G10G11

--

H10H11

--

J11 -

PACKAGE DESCRIPTION

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Inormation urnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed or its use. Linear Technology Corporation makes no representa-tion that the interconnection o its circuits as described herein will not inringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

B 01/10 Added Note 5 2, 4

C 03/12 Revised entire data sheet to include the BGA package. 1–30

(Revision history begins at Rev B)

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PACKAGE PHOTO

PART NUMBER DESCRIPTION COMMENTS

LTM4628 26V, Dual 8A, DC/DC Step-Down μModule Regulator 4.5V ≤ VIN ≤ 26.5V, 0.6V ≤ VOUT ≤ 5V, Remote Sense Amplier, InternalTemperature Sensing Output, 15mm × 15mm × 4.32mm LGA

LTM4627 20V, 15A DC/DC Step-Down μModule Regulator 4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5V, PLL Input, VOUT Tracking, Remote SenseAmplier, 15mm × 15mm × 4.32mm LGA

LTM4611 1.5VIN(MIN), 15A DC/DC Step-Down μModuleRegulator

1.5V ≤ VIN ≤ 5.5V, 0.8V ≤ VOUT ≤ 5V, PLL Input, Remote Sense Amplier,VOUT Tracking, 15mm × 15mm × 4.32mm LGA

LTM4613 8A EN55022 Class B DC/DC Step-Down μModuleRegulator

5V ≤ VIN ≤ 36V, 3.3V ≤ VOUT ≤ 15V, PLL Input, VOUT Tracking and Margining,15mm × 15mm × 4.32mm LGA

LTM4601AHV 28V, 12A DC/DC Step-Down μModule Regulator 4.5V ≤ VIN ≤ 28V, 0.6V ≤ VOUT ≤ 5V, PLL Input, Remote Sense Amplier,VOUT Tracking and Margining, 15mm × 15mm × 2.82mm LGA or15mm × 15mm × 3.42mm BGA

LTM4601A 20V, 12A DC/DC Step-Down μModule Regulator 4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5V, PLL Input, Remote Sense Amplier,VOUT Tracking and Margining, 15mm × 15mm × 2.82mm LGA or15mm × 15mm × 3.42mm BGA

LTM8027 60V, 4A DC/DC Step-Down μModule Regulator 4.5V ≤ VIN ≤ 60V, 2.5V ≤ VOUT ≤ 24V, CLK Input, 15mm × 15mm × 4.32mm LGA

LTM8032 36V, 2A EN55022 Class B DC/DC Step-DownμModule Regulator

3.6V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V, Synchronizable,9mm × 15mm × 2.82mm LGA or 9mm × 15mm × 3.42mm BGA

LTM8061 32V, 2A Step-Down μModule Battery Charger withProgrammable Input Current Limit

Compatible with Single Cell or Dual Cell Li-Ion or Li-Poly Battery Stacks(4.1V, 4.2V, 8.2V, or 8.4V), 4.95V ≤ VIN ≤ 32V, C/10 or Adjustable Timer ChargeTermination, NTC Resistor Monitor Input, 9mm × 15mm × 4.32mm LGA

RELATED PARTS

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15mm

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Ltm 4601

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