Low-Power CMOS Optical Interconnect Transceivers RX with equalization (additional power & area)...

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Computer Systems Laboratory Stanford University Low-Power CMOS Optical Interconnect Transceivers Samuel Palermo* *Now at Intel Corp., Hillsboro, OR

Transcript of Low-Power CMOS Optical Interconnect Transceivers RX with equalization (additional power & area)...

Page 1: Low-Power CMOS Optical Interconnect Transceivers RX with equalization (additional power & area) Chip-to-Chip Electrical Interconnects Sophisticated equalization circuitry required

Computer Systems LaboratoryStanford University

Low-Power CMOS Optical Interconnect Transceivers

Samuel Palermo*

*Now at Intel Corp., Hillsboro, OR

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Outline

Introduction

Optical transmitters

Optical receiver

Clock and data recovery

Optical link system performance

Conclusion

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High Speed Links

Increasing computation power and today’s networked society requires chip-to-chip I/O bandwidth to increase

Routers, Processor – Memory Interface

*2006 International Technology Roadmap for Semiconductors

ITRS Projections*

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Chip-to-Chip Electrical Interconnects

Electrical channel characteristics limit performance

Electrical Backplane Channel

*V. Stojanovic and M. Horowitz, “Modeling and Analysis of High-Speed Links," CICC, 2003.

Channel Responses*

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5Gb/s data at RX

with equalization (additional power & area)

Chip-to-Chip Electrical Interconnects

Sophisticated equalization circuitry requiredTypical commercial electrical I/O xcvr

~20mW/Gb/s at 10Gb/s

5Gb/s data at TX

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Chip-to-Chip Optical Interconnects

Optical interconnects remove many channel limitationsReduced complexity and power consumptionPotential for high information density with wavelength-division multiplexing (WDM)

negligible frequency dependent loss

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Optical Sources & Detectors

Sources

VCSELMQW Electroabsorption

Modulator

p-i-n Detector

Detector Integration

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CMOS Optical Link Issues

VCSEL bandwidthInherent device RCOptical bandwidth requires high average current density

Modulator voltage swing limited by CMOS reliability constraints

Reduced gain/headroom in scaled technologiesMotivates use of integrating RX vs traditional TIA

Dealing with mismatchOffset compensation (voltage & timing)

Power and area reduction

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90nm CMOS 16Gb/s Optical Transceiver Architecture

1. S. Palermo et al, “A 90nm CMOS 16Gb/s Transciever for Optical Interconnects," ISSCC, 2007.2. J. Roth, S. Palermo et al, “1550nm Optical Interconnect Transceiver with Low Voltage Electroabsorption

Modulators Flip-Chip Bonded to 90nm CMOS," OFC, 2007.

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Outline

Introduction

Optical transmittersVCSEL TXMQWM TX

Optical receiver

Clock and data recovery

Optical link system performance

Conclusion

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VCSEL Bandwidth vs Reliability

THavg IIBW −∝

Mean Time to Failure (MTTF) is inversely proportional to current density squared

[2]

Steep trade-off between bandwidth and reliability

⎟⎟⎠

⎞⎜⎜⎝

⎛−⎟

⎠⎞

⎜⎝⎛

= 37311

2j

ATk

E

ejAMTTF

10Gb/s VCSEL Frequency Response [1]

4

1BW

MTTF ∝

1. D. Bossert et al, "Production of high-speed oxide confined VCSEL arrays for datacom applications," Proceedings of SPIE, 2002.2. M. Teitelbaum and K. Goossen, "Reliability of Direct Mesa Flip-Chip Bonded VCSEL’s," LEOS, 2004.

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VCSEL TX Equalization

( ) desTT

ls YPPPH 1−=

TX Currenth(n)=I-1(-1) + I0(0) + I1(1) + I2(2)

Received Optical Powery(n)

Channel Pulse Responsep(n)

Measured pulse responses at 17Gb/s w/ Iavg=6.7mA

4-tap FIR filter – 1 precursor, 1 main, and 2 postcursor is a good compromise between power and performance

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Multiplexing FIR Circuit Implementation

S. Palermo and M. Horowitz, “High-Speed Transmitters in 90nm CMOS for High-Density Optical Interconnects," ESSCIRC, 2006.

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Tap Mux & Output Stage

5:1 multiplexing predriver uses 5 pairs of complementary clock phases spaced by a bit time

Tunable delay predriver compensates for static phase offsets and duty cycle error

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VCSEL TX Optical Testing

Wirebonded10Gb/s VCSEL

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VCSEL 16Gb/s Optical Eye Diagrams

Iavg=6.2mA, ER=3dB

w/ Equalization

IDC = 4.37mAIMOD = 3.66mA

IDC = 3.48mAI−1 = -0.70mAI0 = 4.36mAI1 = -0.19mAI2 = 0.19mA

Equalization increases vertical eye opening

45% at 16Gb/s

No Equalization

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External Modulation with MQWM

Absorption edge shifts with changing bias voltage due to the “quantum-confined Stark effect” and modulation occurs

Maximizing voltage swing allows for good contrast ratio over a wide wavelength range

QWAFEM Modulator*

*N. Helman et al, “Misalignment-Tolerant Surface-Normal Low-Voltage Modulator for Optical Interconnects," JSTQE, 2005.

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High-Voltage Output Stage Issues

☺ Cascode driver has potential for 2x Vdd drive at high speed

Static-biased cascode suffers from Vds stress during transients

*T. Woodward et al, “Modulator-Driver Circuits for Optoelectronic VLSI," IEEE Photonics Technology Letters, 1997.

Cascode Driver*

Vds stress on MN2 > 45% Vdd

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Pulsed-Cascode Output Stage

Preserves two-transistor stack configuration for maximum speed

Cascode transistors’ gates pulsed during transitions to prevent Vds overstress

S. Palermo and M. Horowitz, “High-Speed Transmitters in 90nm CMOS for High-Density Optical Interconnects," ESSCIRC, 2006.

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Output Stage Waveforms

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Output Stage Waveforms

Vds stress < 10% Vdd

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Modulator TX with Level-Shifting Multiplexer

Level-shifter combined with multiplexerActive inductive shunt peaking compensates multiplexer self-loading (reduces transition times by 37%)Slightly lower fan-out ratio in “high” signal path to compensate for level-shifting delayDelay Tracking

“High” path inverter nMOS in separate p-wellMetal fringe coupling capacitors perform skew compensation

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MQWM TX Testing

3R

R

sclk

sclk_b

cclk

Vcalib toscope

x1 x10

Vddsamp

x10 x50

Sampler

Mbias

MQWM

ModulatorTX

Electrical sampler at modulator transmitter output

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Modulator Driver Electrical Eye Diagram

16Gb/s data subsampled at modulator driver output nodeExperimental full optical link operation at 1.8Gb/s*

Limited by excessively high contact resistance *J. Roth, S. Palermo et al, “An optical interconnect transceiver at 1550nm using low voltage electroabsorption modulators directly integrated to CMOS," JLT, 2007.

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Outline

Introduction

Optical transmitters

Optical receiver

Clock and data recovery

Optical link system performance

Conclusion

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Optical RX Scaling Issues

☺ Traditionally, TIA has high RT and low Rin

⎟⎠⎞

⎜⎝⎛

+=

AARR FT 1

INFdB CR

A+≈

13ω

Headrooom/Gain issues in 1V CMOS

A ≈ 2 – 3

Power/Area Costs( ) 4

32 TIA dBINTD fCRI ∝

23 LA dBD fI ∝

VDDVVV GSGSA *8.021 ≈+=

( ) ( )VOD

VDDVOD

VVDDRgA ADm

*2.01

αα≈

−=≈

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Integrating Receiver Block Diagram

A. Emami-Neyestanak et al, “A 1.6Gb/s, 3mW CMOS receiver for optical communication," VLSI, 2002.

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Demultiplexing Receiver

Demultiplexing with multiple clock phases allows higher data rate

Data Rate = #Clock Phases x Clock FrequencyGives sense-amp time to resolve dataAllows continuous data resolution

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Clocked Sense Amplifier

Offset cancelled with digitally adjustable PMOS capacitorsStep=2.3mV, Range=±70mV

Kickback charge can corrupt adjacent samplesNeed high common-mode input for adequate speed

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1V Modified Integrating Receiver

Differential Buffer☺ Fixes sense-amp common-mode input for improved

speed and offset performance☺ Reduces kickback charge

Cost of extra power and noiseInput Range = 0.6 – 1.1V

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Receiver Sensitivity Analysis

mVC

kT

sampsamp 92.02

==σmVbuffer 03.1=σ mVSA 45.0=σ

Residual SA Offset = 1.15mV

Max ΔVin(ΔIAVG) = 0.6mV

16Gb/sat 65.0 NoiseJitter Clock mVvT b

b

jclk ≈Δ⎟⎟

⎠

⎞⎜⎜⎝

⎛=

σσ

mVclkSAbuffersamptot 59.1 NoiseInput Total 2222 =+++= σσσσσ

ΔVb for BER = 10-10 = 6.4σtot + Offset = 11.9mV

( )b

inpdbavg T

CCVP

ρ+Δ

=

Gb/s Pavg(dBm)

10 -9.8

16 -7.8

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Outline

Introduction

Optical transmitters

Optical receiver

Clock and data recovery

Optical link system performance

Conclusion

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Conventional Dual-Loop CDR

☺ 2 degrees of freedom to filter VCO noise & erroneous phase updates

Input demultiplexingreceiver requires multiple phase muxes& interpolators

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Dual-Loop CDR w/ Feedback Interpolation

Extends [Larsson:99] to input demultiplexingreceiver

Only one phase mux/interpolator pair

Filtering of interpolator switching

Path from VCO to samplers

Minimal DelayStatic – allows offset cancellation

5:1

MU

X

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Dual-Loop CDR w/ Feedback Interpolation

5:1

MU

X

Frequency loop bandwidth = 40MHz to minimize VCO noise

Phase loop bandwidth < 4MHz to minimize input noise

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Baud-Rate Phase Detection

For certain 4-bit patterns compare Vin(n) with Vin(n-2) [Emami:04]

☺ No “quadrature” phases requiredReduces net update rate to 18.75%Valid 4-Bit Patterns

0011, 1100, 0010, 0100, 1011, 1101

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Clock Recovery Performance

RX clock frequency = 3.2GHz (16Gb/s)Jitter increases only marginally when CDR activated

1.74psrms, 12.9pspp » » 1.90psrms, 15.1pspp

Sufficient filtering of input noise

CDR Disabled CDR Activated

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Phase Correction Circuitry

Static phase offset corrected with tunable delay clock buffers

Digitally-adjustable capacitive loadsPhase range at 16Gb/s is ±12% UI

Phase Correction PerformanceTunable Delay Clock Buffers

Page 39: Low-Power CMOS Optical Interconnect Transceivers RX with equalization (additional power & area) Chip-to-Chip Electrical Interconnects Sophisticated equalization circuitry required

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Outline

Introduction

Optical transmitters

Optical receiver

Clock and data recovery

Optical link system performanceVCSEL link

Conclusion

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Optical Transceiver Testing

RX Input NodeTransmitted Bits

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Receiver Sensitivity

Test Conditions8B/10B data patterns (variance of 6 bits)Long runlength data (variance of 10 bits)

BER < 10-10

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Transceiver Power Consumption

Power at 16Gb/s = 129mW (8.1mW/Gb/s)Power scales with data rate

Mostly CMOS circuitryIntegrating RX sensitivity improves at lower data rates

Power Breakdown at 16Gb/s

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Transceiver Performance Summary

Technology 90nm CMOS

Supply Voltages Vdd=1V, LVdd=2.8V, PDBias=2.5V

Data Rate 5 - 16Gb/s

Extinction Ratio 3dB

Average Optical Launch Power 3.1dBm

RX Input Capacitance 440fF

RX Sensitivity (BER=10-10)10Gb/s16Gb/s

12.5mV (-9.6dBm)20.2mV (-5.4dBm)

Area 0.105mm2

Power at 16Gb/s 129mW (8.1mW/Gb/s)

Page 44: Low-Power CMOS Optical Interconnect Transceivers RX with equalization (additional power & area) Chip-to-Chip Electrical Interconnects Sophisticated equalization circuitry required

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Optical vs Electrical XCVRPerformance Comparisons

Compares favorably due to simple equalization circuitryShould scale well

Better VCSEL technologyLower capacitance photodetectorsHigher data rates ⇒ More equalization for electrical channels

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Conclusion

Optical interconnects provide a path to reducing the I/O bandwidth problem

Proposed optical interconnect architecture is suitable for large scale integration in current/future CMOS technologies

VCSEL TX equalizer allows low current operationReliable MQWM TX capable of 2*Vdd voltage driveLow voltage integrating receiverBaud-rate clock recovery

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Acknowledgments

Profs Mark Horowitz, Azita Emami, and David Miller

Jon Roth for optics/device design of modulator link

CMP and STMicroelectronics for chip fabrication

ULM Photonics for VCSELs

Albis Optoelectronics for photodetectors

MARCO-IFC for funding support

Sh. Palermo for encouragement and support

Page 47: Low-Power CMOS Optical Interconnect Transceivers RX with equalization (additional power & area) Chip-to-Chip Electrical Interconnects Sophisticated equalization circuitry required

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Backup Slides

Page 48: Low-Power CMOS Optical Interconnect Transceivers RX with equalization (additional power & area) Chip-to-Chip Electrical Interconnects Sophisticated equalization circuitry required

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Equalization Performance

Maximum data rate vs average currentMin 80% eye opening & <40% overshoot

Equalization allows lower average current for a given data rate

Linear equalizer limited by VCSEL nonlinearity

ER=3dB ER=6dB

14Gb/s35% less Iavg ⇒

138% increase in MTTF4Tap Eq

No Eq

4Tap Eq

No Eq

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13Gb/s Power w/ different tap #

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VCSEL TX Power vs Data Rate & Tap #

FCB Channel Wirebond Channel

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Modulator Driver Reliability Simulations

Transient with random data

Corner simulations show no output stage voltages exceed 11% of nominal Vdd

Monte Carlo simulations show tight distributions (σ < 15mV)

Maximum nMOS Voltages Maximum pMOS Voltages

MN1 VDS Distribution

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Coupling Capacitor Skew Compensation Performance


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