Long Channel MOSFET 4

8/11/2019 Long Channel MOSFET 4

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Department of Electrical and Computer Engineering, National University of Singapore

Sub-Threshold Region Behavior of Long Channel MOSFET

Sub-threshold CurrentObservation

- Sub-threshold current has an exponential relationship with V gs


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Sub-threshold Current- Unlike the strong inversion region, in which

the drift current dominates, sub-thresholdconduction is dominated by the diffusionconduction mechanism

- Because Vg is below Vt, almost noelectrons inverted at the surface, so thesurface potential is determined by thedepletion region under that gate and hasthe nearly same value along the channel.Thus, the electric field along the channeldirection is approaching zero, which makes

almost no drift current

- Besides, it is also clear from the simulationresult of Charge-Sheet Model that diffusioncurrent dominates at sub-threshold region.



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Sub-threshold Current


- Since the sub-threshold current is dominated by diffusion current. Then,

- Integrating from y=0 to y=L

where, Qi(y=0) and Qi(y=L) are the inversion charge density at sourceand drain at sub-threshold region (or weak inversion)

- Recall: from MOS-C part, the inversion charge density at weak inversion

dy

dQ

q

kT W

dy

dQWD y I ieff

inds ==)(

)]0()([)(

)0(

==== =

= yQ L yQ

qkT

LW

dQq

kT LW

I iieff L yQ

yQieff ds

i

i

kT q

S

Si Ai BS eq

kT qN Q

/)2(

2

2

=


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- Then, with source grounded and drain bias of Vds, the Qi source and drainends of the channel in a MOSFET under weak inversion can be written asfollows:

Here, S0 is the surface potential at source end of the channel

- The drain current can be solved as

)1()(2

//)(2

0

0 kT qV kT q

S

oxeff

ds

ds BS eeq

kT C

L

W I =




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- Re-arranging the above equation and replacing the B term, we have

- Inside above equation, S0 can be calculated as below

here we assume that Q S=Qd due to weak inversion. Then

- For each Vg, we are able to calculate S0 , and then drain current I ds .

)1()()(2

//22

0

0 kT qV kT q

A

i

S

oxeff ds

dsS ee N n

qkT C

LW

I =



ox

d S fb

S S fboxS fb g C

QV

CoxQ

V V V V ||

000 +++=++=

ox

S ASiS fb g C

qN V V 00

2 ++=


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Discussion of Sub-threshold Current

Gate voltage dependence

- Sub-threshold current has an exponential relationship with S0 , which iscorresponding to Vg, so the sub-threshold current increases exponentiallywith gate voltage Vg.



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Discussion of Sub-threshold Current

Drain voltage dependence

- Sub-threshold current depends on Vds when Vds is small by

- Sub-threshold current independent with Vds when Vds larger than a few kT/q.


)1(/ kT qV

ds

ds

e I


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Sub-threshold Swing (S) Alternating sub-threshold current form:

- introducing two parameters:(i) depletion region capacitance C d

Cd Q b/ s = Cox/(2 s)(ii) factor :

as s is linearly related with V gs , we introduce by: s - 2 B = (V gs V t)/

- physical view of :capacitive coupling between the gate and silicon surface

If there is a significant trap density (C it: surface state capacitance)

- sub-threshold current:

where, I pf = (C d/C ox)(kT/q) 2 = (-1)(kT/q) 2, is a pre-factor term.

Cd = 1 + = 1 + 2 2 BCox

Vg

s

Cox

CdC it

C it = 1 + +Cox

CdCox

Ids = Ipf exp[ ](1 e -qVds /kT), Vgs


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Sub-threshold Swing (S)

- Sub-threshold swing is another importantdevice characteristics in the sub-thresholdregion

- defined as the change in the gate voltageVgs required to reduce sub-threshold currentIds by one decade

S=dV gs /d(logI ds )- after detailed calculation, sub-threshold

swing (S)S= (kT/q)ln10 2.3(kT/q)

- smaller value of S, better turn-onperformance of device

- minimum swing S min isS min = 2.3(kT/q)= 60 mV/decat 300K when when the oxide thicknessapproaches to zero

- S is a convenient measure of the importance

of the interface traps on device performance

Ids (log)

Vgs (linear)

Subthreshold swing (S)= 1/slope



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Key dependences of sub-threshold swing (S)

- Gate oxide thicknesstox Cox sharper sub-threshold

- Substrate dopingN A Cd softer sub-threshold

- Substrate bias|Vbs| Cd sharper sub-threshold

- TemperatureT softer sub-threshold

++==

ox

it

ox

d

C

C

C

C

qkT

qkT

S 13.23.2

reflect electrostatic competition between the top gate andbody (bottom gate

)


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Substrate doping dependence- Lower substrate doping can have a thicker depletion layer, a lower depletion

capacitance, and a smaller S.- This also reflects that it is easier for the gate electrode to control the lower

doping substrate.


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Temperature dependence- At room temperature (300K), the ideal limit of S is 60mV/dec- Normally, devices always work in a higher temperature ambient due to heat

dissipation; the S at higher temperature will be higher than room temperature

- S at low temperature can be lowered down significantly- This is due to that the sub-threshold drain current vs. gate voltage curve is

indeed proportional to 1/T


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Substrate bias dependence

- Since the depletion thickness increases when a substrate bias is applied, thesub-threshold swing decreases also

St=83 S

t=67 S

t=63mV/dec


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Off current

- Sub-threshold region is important since it determines the off current

- To achieve I off

(i) L Performance

(ii) Vt Performance

(iii) N A short channel effect tox field on gate oxide reliability issue

- Ioff is a critical design goal in logic devices since it contributes to DC powerdissipation in CMOS

)/exp()()0( 2 kT qV q

kT

L

W V V I I

t eff gsdsoff ==


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Gate Induced Drain Leakage (GIDL) CurrentObservation

- it was observed that the excess drain

current exist when gate bias further reducebelow V t and move to negative side, whichis called Gate Induced Leakage (GIDL)current

- The GIDL current dominates at a negativebias of Vgs and positive bias of Vds. Thelarger difference between Vds and Vgs (i.e.,Vds-Vgs), the higher GIDL current will have.

- Since the GIDL current can generateexcessive heat dissipation, it needs to bemaintained below some specified value, forexample, 10pA/ m.



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Gate Induced Drain Leakage (GIDL) Current


Depletion regions at MOS gated diode

Case (a): Vds>0, Vgs>>0: channel InversionCase (b): Vds>0, Vgs0, Vgs>0

p-sub

N+

Vds >0

Vgs


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Analysis of GIDL Current

- Tunneling creates electron and hole pairs- Electron will tunnel through the barrier

height and collected by the n+ drain,which positive biased.

- Hole will be collected by substrate since itis grounded

- A lot of mechanisms may involve duringthe electron tunneling, such as band-to-band direct tunneling, trap assistedtunneling, etc, depending on the biases ofVgs and Vds.

JH Chen, et al, An analytic three-terminal band-to-band tunneling model on GIDL in MOSFET,IEEE TED, Vol. 48, pp. 1400, 2001.


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Analysis of GIDL Current

- For the same Vgs, higher Vds (morepositive) will make the barrier moresteeper and cause the tunneling easierto happen, so leads to a higher GIDLcurrent.

- For the same Vds, a more negativeVgs will also make the barrier moresteeper and causes the tunnelingeasier to happen, so also leads to ahigher GIDL current

- When a lot of impurities are involved inthe drain region, more traps will beintroduced, make the trap-assistedtunneling easier to happen, and hencea higher GIDL current.




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How to reduce GIDL Current

- Increase the oxide thickness tox to reduce the electric field

- Using LDD (lightly doped drain: LDD) structure to reducethe electric field near the drain side

- Decrease the trap density

- Increase the doping concentration of the drain to decreasethe depletion layer width


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Channel Length Modulation (CLM)

Beyond Saturation Behavior of Long Channel MOSFET

As V ds increase and beyond V dssat

- Vds -Vdssat effective channel length (L L- L) drain current no more

staurated


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Channel Length Modulation (CLM)


- Considering CLM, the drain currentin saturation region becomes

- Introducing an empirical relation

we can obtain

where is defined as ChannelLength Modulation Parameter,representing small influence of drain voltage on drain current.

- The can be determined by extrapolating the Ids-Vds curves backward, as shown

in the figure above.

)1( dsdssat ds V I I +=

+

= L L

I

L L

I I dssat

dssat ds 1

1

dsV L L

+=+ 11


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MOSFET Breakdown- impact of high channel field high field leads to energetic (hot) electrons hot electrons cause impact ionization and leading electrons go to drain and holes go to substrate

to form the substrate current

high Efield

energeticelectrons

impactionization(E>1.5eV)

avalanche breakdown- substrate current- bipolar breakdown



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MOSFET Breakdown

- MOSFET breakdown as I sub flows to the body terminal, a body potential of I sub R sub isdeveloped

when I sub R sub < 0.6 V (the turn-on voltage of a PN junction), theincrease in body potential reduces V th (same as applying a body bias)and leading to drain current increase

when I sub R sub > 0.6 V, source/body junction turns on and electronsinjected from source to body

these injected electrons diffuse through the substrate and collected atthe reverse biased drain/body junction (in fact, leading parasitic bipolartransistor npn action)

thus, the maximum drain voltage is limited



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Different Types of MOSFET

Classification of MOSFETs- Enhancement mode normally off channel doping is same as substrate doping type

always called inversion mode

- Depletion mode normally on channel doping is opposite of the substrate doping type


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Different Types of MOSFET

Classification of MOSFETs

Long Channel MOSFET 4

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