Logic Design Styles for High Performance or Low...

UC Berkeley EE241 Jan M. Rabaey

Logic Design Styles for HighPerformance or Low Energy

Jan Rabaey


Logic Design Styles


CMOS Logic Styles (1)

PUN

PDN

ABC

OUT

VDD

GND

ABC

Complementary

robustscales

large and slow

LOGICNETWORK

ABC

OUT

Pass Transistor Logic

simple and fastnot always very efficientversatile


CMOS Logic Styles (2)

LOAD

ABC PDN

OUTGND

GND

VDD

Ratioed Logic

small & faststatic power

RPDN <<RLOAD

VDD

PDN

φ

In1In2In3

Out

φ

CL

Dynamic Logic

Small & fastest!Noise issuesScales?


Differential Logic


DCVSL


Karnaugh Map Technique

10 tors


0

1

00 01 11 10x1

x2x3

0

0

0 01

1 1 1

Idea: find shared expressions

Build sharescubes first!

LOAD

x1

x3

x1

x3

x2 x2

Q Q

LOAD

x1

x3

x1

x3

x2 x2

Q Q

x1 x2

Add othercubes next.


Example: Q = x1x2x3x4 + x1(x2+x3+x4)


Using Ordered BDDs


DSL Differential Split Logic


But … Consumes Static Power


Simulation Results for Different Adders


Pass Transistor Logic

Advantages:versatile - programmable through interconnectcan be extended to low voltage swingnot gate based - rather multiplexer oriented

Issues:choice of basic cellswitch selectionperformance issuessynthesis


Conditional Sum Adder

Rothermel (JSSC 89) tp ~ 1 + log2N


Evolutions in Pass-transistor

Double pass-transistor logic


Impact of Vdd on Delay


NMOS-only Pass Transistor Networks

Similar to DCVSL


Level-Restoring Schemes

Cross-coupledPMOS

Sense AmplifyingLatch

FeedbackRestorer


Level Restoring Schemes

Vdd = 1.5 V


(2) Modify Thresholds


Leakage Currents

Simulated for 0.6 micron technology


Important : Biasing of output Inverters


CPL


CMOS versus CPL

Reduced swing at internal nodes: Vtp=Vtn=0.4 V; Vtpass = 0


Performance and Power Dissipation


Control thresholds dynamically

(Assaderaghi 94): DTMOS

Example: VT = 0.4V at 0 V; 0.17V at 0.5 V


Impact of Forward Biasing


Impact of forward biasing


0.5V CPL (ISSCC 96)


Lean Cell Library


Various Logic functions of the Lean cell library


Sample Circuits


Comparison


Comparisons per Cell


Performance versus supply voltage


Swing-Restored Pass-Transistor Logic


L-DPTL: A Low Power Logic Family

Latched Differential Pass-transistor Logic


Adder circuit in SRPL


SRPL Delay Model

Extra Cap.

Not enough drive


L-DPTL Versus Static CMOS (SPICE)


SAPL


SA-F/F Circuits


Discrete Cosine Transform(DCT) in SAPL

1.5 ns 20b carry-skip adder(x1.5 speed, 30% area, 50% power reduction)


DCT MAC Simulated Waveforms


A Comparison[Zimmerman and Fichtner - July 97]


CMOS and Pass-Transistor Logic

Beware: no low-threshold devices considered!


Full Adders


Generic Gates


Configurable Logic

input

out

vdd

LUT Tree

LUTConfigMem

input mux

lut inputs

3-input LUT


Comparison for 3-input LUT

Logic Design Styles for High Performance or Low...

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