1. CHAPTER 5 Digital Combinational Logic

2. Contents Introduction Decoders Encoders Demultiplexers Multiplexers Digital Combinational Logic2 3. INTRODUCTION Four common and useful MSI circuits: Decoder Demultiplexer Encoder MultiplexerBlock-level outlines of MSI circuits: codeinpu tdecode rmuxselec tentit ydataentit ydataDigital Combinational Logicencode rdemu x selec tcodeoutp ut3 4. DECODERS (1/5) Codes are frequently used to represent entities, eg: your name is a code to denote yourself (an entity!).These codes can be identified (or decoded) using a decoder. Given a code, identify the entity.Convert binary information from n input lines to (maximum of) 2n output lines.Known as n-to-m-line decoder, or simply n:m or n n m decoder (m 2 ).May be used to generate 2n minterms of n input variables. 4 5. DECODERS (2/5) Example: If codes 00, 01, 10, 11 are used to identify four light bulbs, we may use a 2-bit decoder. 2x4 F0 X Dec F 1 F2 Y F32-bit codeBulb Bulb Bulb Bulb0 1 2 3This is a 2 4 decoder which selects an output line based on the 2-bit code supplied. Truth table: X Y F F F F 00 0 1 10 1 0 11 0 0 010 1 0 020 0 1 030 0 0 1 5 6. DECODERS (3/5) X 0 0 1 1From truth table, circuit for 2 4 decoder is: Note: Each output is a 2-variable minterm (X' Y', X' Y, X Y' or X Y)Y 0 1 0 1F0 1 0 0 0F1 0 1 0 0F2 0 0 1 0F3 0 0 0 1F0 = X' Y'F1 = X' Y F2 = X Y' F3 = XY 6XY 7. DECODERS (4/5) F0 = x' y' z' F1 = x' y' z F2 = x' y z' F3 = x' y zDesign a 3 8 decoder. x 0 0 0 0 1 1 1 1y 0 0 1 1 0 0 1 1z 0 1 0 1 0 1 0 1F0 F1 F2 F3 F4 F5 F6 F7 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1F4 = x y' z' F5 = x y' z F6 = x y z' F7 = xyz xyz 7 8. DECODERS (5/5) In general, for an n-bit code, a decoder n could select up to 2 lines: n-bit code:n to 2n decoder:up to 2n output lines8 9. DECODERS: IMPLEMENTING FUNCTIONS (1/5) A Boolean function, in sum-of-minterms form a decoder to generate the minterms, and an OR gate to form the sum.Any combinational circuit with n inputs and m outputs can be implemented with an n:2n decoder with m OR gates.Good when circuit has many outputs, and each function is expressed with few minterms.9 10. DECODERS: IMPLEMENTING FUNCTIONS (2/5) xExample: Full adder S(x, y, z) = C(x, y, z) =m(1,2,4,7) m(3,5,6,7)3x8 Dec xS2yS1zS00 1 2 3 4 5 6 7yzCS0 0 0 0 1 1 1 10 0 1 1 0 0 1 10 1 0 1 0 1 0 10 0 0 1 0 1 1 10 1 1 0 1 0 0 1SC10 11. DECODERS: IMPLEMENTING FUNCTIONS (3/5) 3x8 Dec0 x 0 yS10 zS2S00 1 2 3 4 5 6 7xSCyzCS0 0 0 0 1 1 1 10 0 1 1 0 0 1 10 1 0 1 0 1 0 10 0 0 1 0 1 1 10 1 1 0 1 0 0 111 12. DECODERS: IMPLEMENTING FUNCTIONS (4/5) 3x8 Dec0 x 0 yS11 zS2S00 1 2 3 4 5 6 7xSCyzCS0 0 0 0 1 1 1 10 0 1 1 0 0 1 10 1 0 1 0 1 0 10 0 0 1 0 1 1 10 1 1 0 1 0 0 112 13. DECODERS: IMPLEMENTING FUNCTIONS (5/5) 3x8 Dec1 x 1 yS11 zS2S00 1 2 3 4 5 6 7xSCyzCS0 0 0 0 1 1 1 10 0 1 1 0 0 1 10 1 0 1 0 1 0 10 0 0 1 0 1 1 10 1 1 0 1 0 0 113 14. DECODERS WITH ENABLE (1/2) Decoders often come with an enable control signal, so that the device is only activated when the enable, E = 1. Truth table: F E X Y F 01 1 1 1 00 0 1 1 X0 1 0 1 X1 0 0 0 0F0 = E X' Y'10 1 0 0 0F2F30 0 1 0 00 0 0 1 0F1 = E X' Y F2 = E X Y' F3 = E X YCircuit of a 2 4 decoder with enable: XYE 14 15. DECODERS WITH ENABLE (2/2) In the previous slide, the decoder has a oneenable control signal, i.e. the decoder is enabled with E=1.In most MSI decoders, enable signal is zeroenable, usually denoted by E' or . The decoder is enabled when the signal is zero (low). EXYF0F1F2F3E'XYF0F1F2F31 1 1 1 00 0 1 1 X0 1 0 1 X1 0 0 0 00 1 0 0 00 0 1 0 00 0 0 1 00 0 0 0 10 0 1 1 X0 1 0 1 X1 0 0 0 00 1 0 0 00 0 1 0 00 0 0 1 0Decoder with 1enableDecoder with 0enable 15 16. LARGER DECODERS (1/4) Larger decoders can be constructed from smaller ones.Example: A 3 8 decoder can be built from two 2 4 decoders (with oneenable) and an inverter.w x yw x yS2 S1 S03x8 DecS1 S0S1 S02x4 Dec E2x4 DecEF0 = w' x' y' F1 = w' x' y : : F7 = w x y0 1 : : 70 1 2 3F0 = w' x' y' F1 = w' x' y F2 = w' x y' F3 = w' x y0 1 2 3F4 = w x' y' F5 = w x' y F6 = w x y' F7 = w x y 16 17. LARGER DECODERS (2/4) w x yw x yS1 S0S1 S02x4 Dec E2x4 Dec E0 1 2 3S2 S1 S03x8 Dec0 1 : : 7F0 = w' x' y' F1 = w' x' y : : F7 = w x yF0 = w' x' y' F1 = w' x' y F2 = w' x y' F3 = w' x y F4 = w x' y' F5 = w x' y F6 = w x y' F7 = w x y17 18. LARGER DECODERS (3/4) Construct a 4 16 decoder from two 3 8 decoders with one-enable. w x y z4x16 Decw x y zS2 S1 S0S2 S1 S03x8 DecE3x8 DecES3 S2 S1 S00 1 : 7F0 F1 : : F15F0 F1 : F70 1 : 70 1 : : 1 5F8 F9 : F15 18 19. LARGER DECODERS (4/4) Note: The input, w and its complement, w', are used to select either one of the two smaller decoders.Decoders may also have zero-enable and/or negated outputs. Normal outputs = active high Negated outputs = active lowExercise: What modifications should be made to provide an ENABLE input for the 3 8 decoder and the 4 16 decoder created in the previous two slides?Exercise: How to construct a 4 16 decoder using five 2 4 decoders with enable? 19 20. STANDARD MSI DECODER (1/2) 74138 (3-to-8 decoder)74138 decoder module. (a) Logic circuit. (b) Package pin configuration.20 21. STANDARD MSI DECODER (2/2)74138 decoder module. (c) Function table. (c)74138 decoder module. (d) Generic symbol. (e) IEEE standard logic symbol. Source:The Data Book Volume 2, Texas Instruments Inc.,1985 21 22. DECODERS: IMPLEMENTING FUNCTIONS REVISIT (1/2) Example: Implement the following function using a 3 8 decoder and appropriate logic gate f(Q,X,P) = m(0,1,4,6,7) = M(2,3,5)We may implement the function in several ways: Using a decoder with active-high outputs with an OR gate: f(Q,X,P) = m0 + m1 + m4 + m6 + m7Using a decoder with active-low outputs with a NAND gate: f(Q,X,P) = (m0' m1' m4' m6' m7' )'Using a decoder with active-high outputs with a NOR gate: f(Q,X,P) = (m2 + m3 + m5 )' [ = M2 M3 M5 ]Using a decoder with active-low outputs with an AND gate: f(Q,X,P) = m2' m3' m5'22 23. DECODERS: IMPLEMENTING FUNCTIONS REVISIT (2/2) 3x8 DecQ X PA B C0 1 2 3 4 5 6 7f(Q,X,P) = m(0,1,4,6,7) f(Q,X,P)(a) Active-high decoder with OR gate. 3x8 Dec Q X PA B C0 1 2 3 4 5 6 7f(Q,X,P)(c) Active-high decoder with NOR gate.Q X P3x8 Dec A B C0 1 2 3 4 5 6 7f(Q,X,P)(b) Active-low decoder with NAND gate. 3x8 Dec Q X PA B C0 1 2 3 4 5 6 7f(Q,X,P)(d) Active-low decoder with AND gate.23 24. ENCODERS (1/4) Encoding is the converse of decoding. Given a set of input lines, of which exactly one is high, the encoder provides a code that corresponds to that input line. Contains 2n (or fewer) input lines and n output lines. Implemented with OR gates. Example: Select via switchesF0F1 F2 F3D4-to-2 Encode r0D2-bits code124 25. ENCODERS (2/4) Truth table: With K-map, we obtain: D0 = F1 + F3 D1 = F2 + F3Circuit:F0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1F1 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1F2 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 1F3 0 0 0 1 0 1 1 0 1 1 0 1 0 1 0 1D1 0 0 1 1 X X X X X X X X X X X XD0 0 1 0 1 X X X X X X X X X X X X 25 26. ENCODERS (3/4) Example: Octal-to-binary encoder. At any one time, only one input line has a value of 1. Otherwise, we need priority encoder (to be discussed in tutorial). In p u tsO u tp u tsD0 D1 D2 D3 D4 D5 D6 D7 1 0 0 0 0 0 0 00 1 0 0 0 0 0 00 0 1 0 0 0 0 00 0 0 1 0 0 0 00 0 0 0 1 0 0 00 0 0 0 0 1 0 00 0 0 0 0 0 1 00 0 0 0 0 0 0 1xyz0 0 0 0 1 1 1 10 0 1 1 0 0 1 10 1 0 1 0 1 0 1 26 27. ENCODERS (4/4) Example: Octal-to-binary encoder. D0D1x = D4 + D5 + D6 + D7D2 D3y = D2 + D3 + D6 + D7D4 D5D6z = D1 + D3 + D5 + D7D7An 8-to-3 encoder Exercise: Can you design a 2n-to-n encoder without using K-map? 27 28. DEMULTIPLEXERS (1/2) Given an input line and a set of selection lines, a demultiplexer directs data from the input to one selected output line. Example: 1-to-4 demultiplexer. OutputsY0 = DS1'S0' Data Ddemu xS1SoY0 Y1 Y2 Y3Y1 = DS1'S00 0 1 10 1 0 1D 0 0 0Y2 = DS1S0' Y3 = DS1S00 D 0 00 0 D 00 0 0 DS1 S0 selec t 28 29. DEMULTIPLEXERS (2/2) It turns out that the demultiplexer circuit is actually identical to a decoder with enable.S1 S02 4 0 Decode 1 A r B 2Y0 = ?3Y3 = ?EY1 = ? Y2 = ?DELC224CDigital Combinational Logic29 30. MULTIPLEXERS (1/5) A multiplexer is a device which has A number of input lines A number of selection lines One output lineIt steers one of 2n inputs to a single output line, using n selection lines. Also known as a data selector. ninput s:2 :1 Multiplexe routp ut.. .selectELC224CDigital Combinational Logic30 31. MULTIPLEXERS (2/5) Truth table for a 4-to-1 multiplexer: I00I1 I2 I3I2I3S1 S0YS1 S0Yd0 d0 d0 d0Input sII1 d1 d1 d1 d1d2 d2 d2 d2d3 d3 d3 d30 0 1 1d0 d1 d2 d30 0 1 1I0 I1 I2 I30 1 0 1Inputs 0 4:1 1 MUX Y 2 3 S1 S0I0 I1 Outpu tI2 I34:1 mu xYS1 S0 selecselec t ELC224C0 1 0 1t Digital Combinational Logic31 32. MULTIPLEXERS (3/5) Output of multiplexer is sum of the (product of data lines and selectionS1 S0Y0 0 0 1 1 0 1 1 lines)I0 I1 I2 I3Example: Output of a 4-to-1 multiplexer is: Y=?A 2n-to-1-line multiplexer, or simply 2n:1 MUX, is made from an n:2n decoder by adding to it 2n input lines, one to each AND gate.ELC224CDigital Combinational Logic32 33. MULTIPLEXERS (4/5) A 4:1 multiplexer circuit: I0I0I1I1 YI2I3I3 0 3122-to-4 DecoderS1S1 S0ELC224CYI2Digital Combinational LogicS033 34. MULTIPLEXERS (5/5) An application:Helps share a single communication line among a number of devices. At any time, only one source and one destination can use the communication line. ELC224CDigital Combinational Logic34 35. MULTIPLEXER IC PACKAGE Some IC packages have a few multiplexers in each package (chip). The selection and enable inputs are common to all multiplexers within the package.A0 Y0A1Y1A2Y2A3Y3B0 B1E 1 0 0B2SB3(select)E'ELC224C(enable )S X 0 1O u tp u t Y a ll 0 s s e le c t A s e le c t BQuadruple 2:1 multiplexer Digital Combinational Logic35 36. LARGER MULTIPLEXERS (1/4) Larger multiplexers can be constructed from smaller ones. An 8-to-1 multiplexer can be constructed from smaller multiplexers like this (note placement of selector lines): I0 S S S Y I1 I2 I324:1 MUX S1 S0I4 I5 I6 I72:1 MUX4:1 MUXS2Y0 0 0 0 1 1 1 110 0 1 1 0 0 1 100 1 0 1 0 1 0 1I0 I1 I2 I3 I4 I5 I6 I7S1 S0 ELC224CDigital Combinational Logic36 37. LARGER MULTIPLEXERS (2/4) I0 I1 I2 I34:1 MUXI I I2:1 MUXS 1 S0 I4 I5 I6 I74:1 MUXS2 S1 S00 1 2YI I I 016I I I 4 5 6S2S 1 S0 I0 I1 I2 I3 I4 I5 I6 I70 0 1 1 0 0 1 10 1 0 1 0 1 0 1When S2S1S0 = 0010 0 0 0 1 1 1 1When S2S1S0 = 000YWhen S2S1S0 = 110ELC224CDigital Combinational Logic37 38. LARGER MULTIPLEXERS (3/4) Another implementation of an 8-to-1 multiplexer using smaller multiplexers: I0 I1 I2 I32:1 MUXI22:1 MUXI04:1 MUX2:1 I4 MUX S 0 I6 I7I0YY0 0 0 0 1 1 1 1I0 I1 I2 I3 I4 I5 I6 I70 0 1 1 0 0 1 10 1 0 1 0 1 0 1S2 S1 2:1 MUX S0ELC224CS2 S1 S0S0S0 I4 I5When S2S1S0 = 000I6Q: Can we use only 2:1 multiplexers?Digital Combinational Logic38 39. LARGER MULTIPLEXERS (4/4) A 16-to-1 multiplexer can be constructed from five 4-to-1 multiplexers:ELC224CDigital Combinational Logic39 40. STANDARD MSI MULTIPLEXER (1/2)(b)74151A 8-to-1 multiplexer. (a) Package configuration. (b) Function table. ELC224CDigital Combinational Logic40 41. STANDARD MSI MULTIPLEXER (2/2)(c)74151A 8-to-1 multiplexer. (c) Logic diagram. (d) Generic logic symbol. (e) IEEE standard logic symbol. Source: The TTL Data Book Volume 2. Texas Instruments Inc.,1985. ELC224CDigital Combinational Logic41 42. IMPLEMENTING FUNCTIONS (1/3) Boolean functions can be implemented using multiplexers. A 2n-to-1 multiplexer can implement a Boolean function of n input variables, as follows: 1. Express in sum-of-minterms form. Example: F(A,B,C) = A' B' C + A' B C + A B' C + A B C' = m(1,3,5,6) 2. Connect n variables to the n selection lines. 3. Put a 1 on a data line if it is a minterm of the function, or 0 otherwise.ELC224CDigital Combinational Logic42 43. IMPLEMENTING FUNCTIONS (2/3) F(A,B,C) = 0 1 0 1 0 1 1 00 1 2 3 mux 4 5 6 7A B Cm(1,3,5,6) This method works because: FOutput = m0 I0 + m1 I1 + m2 I2 + m3 I3 + m4 I4 + m5 I5 + m6 I6 + m7 I7Supplying 1 to I1,I3,I5,I6 , and 0 to the rest: Output = m1 + m3 + m5 + m6ELC224CDigital Combinational Logic43 44. IMPLEMENTING FUNCTIONS (3/3) Example: Use a 74151A to implement f(x1,x2,x3) = m(0,2,3,5)Realization of f(x1,x2,x3) = m(0,2,3,5). (a) Truth table. (b) Implementation with 74151A.ELC224CDigital Combinational Logic44 45. USING SMALLER MULTIPLEXERS (1/6) Earlier, we saw how a 2n-to-1 multiplexer can be used to implement a Boolean function of n (input) variables. However, we can use a single smaller 2(n-1)-to-1 multiplexer to implement a Boolean function of n (input) variables. Example: The function F(A,B,C) = m(1,3,5,6) can be implemented using a 4-to-1 multiplexer (rather than an 8-to-1 multiplexer).ELC224CDigital Combinational Logic45 46. USING SMALLER MULTIPLEXERS (2/6) Lets look at this example: F(A,B,C) = A B C' 1 1 0 1 0 0 1 0m(0,1,3,6) = A' B' C' + A' B' C + A' B C +0 1 2 3 mux 4 5 6 7F1 C 0 C'A B C0 1 2muxF3A BNote: Two of the variables, A and B, are applied as selection lines of the multiplexer, while the inputs of the multiplexer contain 1, C, 0 and C'.ELC224CDigital Combinational Logic46 47. USING SMALLER MULTIPLEXERS (3/6) Procedure 1. Express Boolean function in sum-of-minterms form. Example: F(A,B,C) =m(0,1,3,6)2. Reserve one variable (in our example, we take the least significant one) for input lines of multiplexer, and use the rest for selection lines. Example: C is for input lines; A and B for selection lines.ELC224CDigital Combinational Logic47 48. USING SMALLER for function, by grouping inputs MULTIPLEXERS (4/6) 3. Draw the truth tableby selection line values, then determine multiplexer inputs by comparing input line (C) and function (F) for corresponding selection line values. AF0001101000111100010101101111MUX input10ELC224CC0B0? ? ? ?01 2muxF3A BDigital Combinational Logic48 49. USING SMALLER MULTIPLEXERS (5/6) Alternative: What if we use A for input lines, and B, C for selector lines? ABCF00010011010001111000101011011110? ? ? ?M ux In p u tABCF000100110100011110001010110111101 C 0 C0 1 2muxA' (when BC = 00)F3B C ELC224CDigital Combinational Logic49 50. USING SMALLER MULTIPLEXERS (6/6) Example: Implement the function below with 74151A: f(x1,x2,x3,x4) = m(0,1,2,3,4,9,13,14,15)ELC224CDigital Combinational Logic50