Aravind Aakash

Introduction

LNS Basics

LNS & Power dissipation

Conclusion

Power dissipation has evolved into an instrumental design optimization objective due to growing demand for portable electronics equipment as well as due to excessive heat generation in high-performance systems.

The dominant component of power dissipation for well-designed CMOS circuits is dynamic power dissipation given by

P = a2 f (a)

Where a is activity factor, is the switchingcapacitance, f is the clock frequency, and Vdd is thesupply voltage.

A variety of design techniques are commonlyemployed to reduce the factors of product withoutdegrading the system.

The reduction of the various factors, whichdetermine power dissipation is sought at all levels ofdesign abstraction.

Higher design abstraction levels aim to reduce thecomputational load and the number of memoryaccesses required to perform a certain task, and tointroduce parallelism and pipelining in the system.

At circuit and process levels, minimal feature sizecircuits are preferred capable of operating atminimal supply voltages, while leakage currents anddevice threshold voltages are minimized.

The application of computer arithmetic techniquesnamely the LNS and RNS can reduce powerdissipation by minimizing particular factors.

Where LNS and RNS are the two classes oftransformation namely the Logarithmic NumberSystem and Residue Number System.

The LNS and RNS techniques reduces the dataactivity, the strength of the operators, or the numberof operations required to perform certaincomputational task.

The particular choice of number system thatis the way numbers are represented in adigital system can reduce power dissipation.

In particular power dissipation reduction dueto appropriate selection of the numbersystem stems from

1) The reduction of the number ofoperations.

2) The reduction of the strength ofoperators.

3) The reduction of the activity of data.

Power dissipation can be reduced by usinglow-power arithmetic circuit architectures.

The application of LNS aims reducing the strength ofparticular operations and to reduce the switchingactivity.

LNS has been employed in the design of low-powerDSP devices, such as a digital hearing aid and toreduce power dissipation in adaptive filteringprocessors.

The LNS maps a linear number X to a triplet as follows

X

(, , = log ) (1) Where z is a single-bit flag which, when asserted, denotes that

X is zero, s is the sign of X, and b is the base of the logarithmic representation.

The organization of an LNS word is shown in figure.

The inverse mapping of a logarithmic triple (z, s, x) to a linear number X is defined by

Mapping (1) is of practical interest because it can simplifycertain arithmetic operations, i.e., it can reduce theimplementation complexity of several operators.

For example, due to the properties of logarithm function, themultiplication of two linear numbers X = and = , isreduced to the addition of their logarithmic images, x and y.

, ,

: = (2)

The basic arithmetic operations and their LNS counterparts are summarized in table.

The zero flag z and the sign flag s are omitted for simplicity.

The table reveals that the complexity of most operations is reduced, the complexity of LNS addition and subtraction is significant.

In particular, LNS addition requires the computation of the nonlinear function

= log(1 + ) (3)

which substantially limits the data word lengths for which LNS can offer efficient VLSI implementations.

LNS arithmetic example: Let X=3.25, y=6.72 and b=2.Perform

the operations X.Y,X+Y, ,2 using the LNS. Initially the data are transferred to the logarithmic domain, as implied by (1):

(, , = log2 ) = 0,0, = log2 3.25 = (0,0,1.70044)(4)

,, = log2 = 0,0, = log2 6.72 = (0,0,2.74846)(5)

Using the LNS images (4) and (5), the required arithmeticoperations are performed as follows: The logarithmic image zof the product Z = X.Y is given by

= + = 1.70044 + 2.74846 = 4.44890 (6)

As both operands are of the same sign, i.e., = 0, = 0,thesign of the product is = 0. Also 1, 1since, and theresult is non-zero, i.e., = 0.

To retrieve the actual result Z from (6),inverse conversion (2) isused as follows:

= 1 12 = 24.44890 = 21.83998 (7)

By directly multiplying X and Y it is found that Z = 21.84. Thedifference is due to round-off error during the conversion fromlinear to the LNS domain.

The calculation of the logarithmic image z of = isperformed as follows:

=

=

. = . (8)

The actual result is retrieved as follows:

= 20.85022 = 1.80278 (9)

The calculation of the logarithmic image z of = 2 can bedone as :

= . = . = . (10)

Again, the actual result is obtained as

= 23.40088 = 10.56520 11

The operation of logarithmic addition is rather awkward and itsrealization is usually based on a memory look-up tableoperation.The logarithmic image z of the sum Z = X+Y is

= max , + log2 1 + 2min , max , (12)

= 2.74846 + log2 1 + 21.04802 (13)

= 3.31759 (14)

The actual value of the sum Z = X+Y, is obtained as

= 23.31759 = 9.96999 15

The organization of the realization of an LNS adder is shown in figure2.

It is noted that in order to implement LNS subtraction, i.e., theaddition of two quantities of opposite sign, a different memory Look-Up Table (LUT) is required.

The LNS subtraction LUT contains samples of the function

The main complexity of an LNS processor is the implementation ofthe LUTs for storing the values of the functions () (). Astraight-forward implementation is only feasible for small wordlengths.

A different technique can be used for larger word lengths,based on the partitioning of a LUT into an assortment of smallerLUTs.

The particular partitioning becomes possible due to thenonlinear behavior of the functionslog( 1 +

) log(1 )

The functions , the approximation of which is required for LNS addition and subtraction

Figure 3

By exploiting the different minimal word length required by groups of function samples, the overall size of the LUT is compressed, leading to the organization of figure 4.

In order to utilize the benefits of LNS , a conversion overhead isrequired in most cases, to perform the forward LNS mappingdefined by eqn (1).

Since all arithmetic operations can be performed in thelogarithmic domain , only an initial conversion is imposed;therefore, as the amount of processing implemented in LNSgrows, the contribution of the conversion overhead to powerdissipation and to area-time complexity becomes negligiblesince it remains constant.

In particular, the LNS forward and inverse mapping overheadcan be mitigated by employing logarithmic A/D and D/Aconverters instead of linear converters, followed by digitalconversion circuitry.

LNS is applicable for low-power design because itreduces the strength of certain arithmetic operatorsand the bit activity.

The operator strength reduction by LNS reduces theswitching capacitance, i.e., it reduces the CL factor ofeqn (a).

A performance comparison of the variousimplementations, reveals that LNS offers accuracycomparable to floating-point, but only at a fraction ofswitched capacitance per iteration of the algorithm.

LNS can affect power dissipation in an additionalway, the bit activity, i.e., the a factor of eqn (a).

A design parameter, which is often neglected, although it plays a key role in an LNS-based processor performance, is the base of the logarithm, b as demonstrated in the following figure (5).

fig(5). Probability P01 per bit for 2s complement & LNS encoding for p=-0.99

The choice of base has a substantial impact on the average bit activity.

Figure (5) shows activity per bit position, i.e., theprobability of a transition from low to high in aparticular bit position, for a twos complement wordand several LNS words, each of a different base b.

Departing from the traditional choice b=2 cansubstantially reduce the signal activity incomparison to the twos-complement representation.

Since multiplication-additions are important in DSPapplications, the power requirements of an LNS and alinear fixed-point adder-multiplier have beencompared.

The results show that two times reduction in powerdissipation is possible for operations with word sizeof 8 to 14 bits.

Given a sufficient number of multiplication-additions, the LNS implementation becomes moreefficient from the low-power dissipation viewpoint,even when a constant conversion overhead is takeninto consideration.