LIC Lab Manual

LIST OF EXPERIMENTS

DESIGN OF INVERTING, NON-INVERTING AND DIFFERENTIAL AMPLIFIERS

AIM:To design and construct a non inverting, inverting amplifier, comparator and adder circuit

using op-amp and obtain their output.APPARATUS REQUIRED :

S.No Apparatus Range Quantity

1.2.3.4.5.6.7.

ResistorOp-ampDual RPSAFOCROBread boardConnecting wires

10kΩIC741(0-30)v

----

511211

DESIGN:

LINEAR INTEGRATED CIRCUITS LAB MANUAL

SI.no. Experiment name Page no.

1 Design of Inverting, Non-Inverting and Differential amplifiers 1

2 Integrator and Differentiator

3 Design of an Instrumentation amplifier

4 Design and Construction of Astable, Mono stable Multivibrators using Op-Amp

5 Characteristics of PLL and its use as Frequency Multiplier

6 Design and Construction of Astable , Mono stable Multivibrators using NE555 timer

7

8

9

Inverting amplifier: A = -Rf/R1 Take A = 1 Rf = R1 Choose Rf = 10kΩ, R1=10kΩ

Non inverting amplifier: A = 1+ Rf/R1 Take A = 2 Rf = R1 Choose Rf = 10kΩ, R1=10kΩ

Adder: Inverting Adder:

Vo= -(Rf/R1)V1-(Rf/R2)V2-(Rf/R3)V3 Take A = 1 Rf = R1 Choose Rf = 10kΩ, R1=10kΩ

Non-Inverting Adder: Vo= (1+ Rf/R1)V1 +(1+ Rf/R2)V2+(1+ Rf/R3)V3 Take A = 2 Rf = R1 Choose Rf = 10kΩ, R1=10kΩ

Comparator: Vo= +Vsat if V2>V1

Vo= -Vsat if V1>V2

PROCEDURE:

Inverting and Non-inverting amplifier:1. Connections are made as per the circuit diagram.2. Apply the input voltage using AFO or RPS.3. The output is noted and plot the graph.4. Then calculate the gain value.

Adder:1. Connections are made as per the circuit diagram.2. Apply the input voltage v1, v2, v3using RPS, the output is noted.3. This is repeated for different values of v1, v2, v3.4. The results are tabulated.

Comparator:1. Connections are made as per the circuit diagram.


2. Apply the two periodic signal using AFO.3. Note the output square wave form and plot the graph.


CIRCUIT DIAGRAM

NON INVERTING AMPLIFIERINVERTING AMPLIFIER

+3

-2

V+7

V-4

O U T6

O S 11

O S 25

U1

uA741

0

R1

1k

R2

1k

AFOCRO

+3

-2

V+7

V-4

O U T6

O S 11

O S 25

U2

uA741

0

R3

1k

R4

1k

CROAFO

ADDER COMPARATOR

+3

-2

V +7

V-

4

O U T6

O S 11

O S 25

U 1

uA 741

R 1

1k

R 2

1k

R 31k

R 41k

V0V3

V2

V1

+3

-2

V+

7

V -4

O U T6

O S 11

O S 25

U 2

uA 741

R 5

1k

R 6

1kVref

VinV0

RESULT:

Thus the non-inverting, inverting, adder and comparator circuits are designed and constructed using op-amp and their outputs are obtained.


2. INTEGRATOR AND DIFFERENTIATOR

AIM: To construct and test the integrator and differentiator circuit. Draw the waveforms

APPARATUS REQUIRED:


1.2.

3.4.5.6.7.8.

ResistorCapacitor

Op-ampDual RPSAFOCROBread boardConnecting wires

10kΩ,1kΩ470pF, .1n

F,1μFIC741(0-30)v

----

2,21

1,111211-

DESIGN:

Integrator:Vo= -(1/R1*Cf) *∫Vin dt

Differentiator:Vo= -R1Cf * dv/dt

PROCEDURE:Integrator:1. Connections are made as per the circuit diagram.2. Apply the square or sine input signal at high frequency using AFO.3. Note the corresponding output waveforms and plot the graph.

Differentiator:1. Connections are made as per the circuit diagram.2. Apply the square or sine input signal at low frequency using AFO.3. Note the corresponding output waveforms and plot the graph.


CIRCUIT DIAGRAM

+3

-2

V+7

V-4

O U T6

O S 11

O S 25

U 3

uA 741R 1

1k

C 2

1n

C 1

1n

+3

-2

V+7

V-4

O U T6

O S 11

O S 25

U 4

uA 741R 2

1k

C 3

1n

C 4

1n

R 3

1k

CRO CROAFOAFO

INTEGRATOR DIFFERENTIATOR

RESULT:Thus the integrator and differentiator circuits are constructed and tested. The wave forms

are drawn.


3. MULTIVIBRATOR USING 555 TIMER

AIM:

To design and construct the astable and mono stable multivibrator using 555 timer. Draw the waveform.

APPARATUS REQUIRED:


1.

2.

3.

4.

5.

6.

7.

8.

Resistor

Capacitor

Timer IC

RPS

AFO

CRO

Bread board

Connecting wires

6.8kΩ,10kΩ

470Ω

470pF, .1nF,1μF

NE555

-

-

(0-30)v

-

-

1,2

1

1,1

1

1

1

1

1

1

-

DESIGN:

Astable multivibrator:

For 50% duty cycle:

Tc= 0.69(Ra+Rb)*C

Td= 0.69Rb* C

T = Tc+Td

T = 0.69(Ra+2Rb)*C

f = 1/T = 1.45/(Ra+2Rb)*C

% Duty cycle D = Td/T*100

D = Ra/(Ra+2Rb)*C


Let Tc = Td = 0.05 msec

Choose C = 10nf

0.05*10-3 = 0.69(Ra+Rb)*10n

Therefore Ra+Rb = 7.215k

Choose Ra=470Ω

Rb=6.8kΩ

Monostable Multivibrator:

Tp = 1.1 RC

For Tp = 0.1ms

Choose C= 0.01μF

To Find R

R =Tp/1.1C=10KΩ

PROCEDURE:

Astable multivibrator:

1. Connections are made as per the circuit diagram.

2. The output waveforms are viewed through CRO.

3. The voltage across the capacitor and that at the output terminal is measured and the waveforms are drawn.

Monostable multivibrator:


2. A low frequency trigger pulse is applied.

3. The output waveforms are viewed through CRO.

4. The voltage across the capacitor and that at the output terminal is measured and the waveforms are drawn.


ASTABLE MULTIVIBRATOR:

R 11k

R 21k

C 11n C 2

1n

21

8 4

3

6

7

5

555

v c c

o/p

MONOSTABLE MULTIVIBRATOR:


R2

1k

C1

1n C2

1n

2

1

4

3

7

5

8

6

vcc

555

o/p

C3

1n

R3

1k

D1

DIODE

I/P

RESULT:

Thus the astable and mono stable multivibrator using 555 timer are designed and the waveforms are drawn.

5. CHARACTERISTICS OF PLL

AIM:

To design a PLL circuit and determine the lock in range and capture range.

APPARATUS REQUIRED:


1.

2.

3.

4.

5.

6.

7.

Resistor

Capacitor

PLL IC

Dual RPS

AFO

Bread board

Connecting wires

6.8kΩ

1nF,1μF

IC565

±15v

-

-

1

2,1

1

1

1

1


PROCEDURE:


2. Measure the free running frequency of VCO at pin 4, with the input signal vin

set equal to zero. Compare it with the calculated value = 0.25/RtCt.

3. Now apply the input signal of 1V square wave at a 1khz to pin 2. Connect one

channel of the scope to pin 2 and display this signal on the scope.

4. Gradually increase the input frequency till the PLL is locked to the input

frequency. This frequency f1 gives the lower end of the capture range. Go on increasing the input frequency, till PLL tracks the input signal, say, to a

frequency f2. This frequency f2 gives the upper end of the lock range. If input

frequency is increased further, the loop will get unlocked.

5. Now gradually decrease the input frequency till the PLL is again locked. This is

the frequency f3, the upper end of the capture range. Keep on decreasing the

input frequency until the loop is unlocked. This frequency f4 gives the lower

end of the lock in range.

6. The lock range fL = (f2-f4). Compare it with the calculated value of 7.8f0/12.

Also the capture range is fC = (f3-f1).Compare it with the calculated values of

Capture range.

∆Fc=± [fl/ (2) (3.6) (103)*C] 1/2

PHASE LOCKED LOOP:


RESULT:

Thus the characteristics of PLL are studied and the capture range& lock in range are determined.

6. FREQUENCY MULTIPIER USING PLL

AIM:

To construct a frequency multiplier circuit using PLL.

APPARATUS REQUIRED:


1. Resistor 2,10,4.7 kΩ 1


R16.8k

C1

0.001uF

C21nF

C30.01uF

IC 565

INPUT

810

2

3

1 9 5

4

7

OUTPUT

+VCC

-VCC

2.

3.

4.

5.

6.

7.

8.

9.

10.

Potentiometer

Capacitor

4-BitBinaryCounter

PLL IC

Transistor

Dual RPS

AFO

Bread board

Connecting wires

20k

1,10nF,1pF

IC7490

IC565

2N2222

±15v

-

-

1

1,1,1

1

1

1

1

PROCEDURE:


2. Set the input signal at 1volt square wave at 500 Hz.

3. Vary the VCO frequency by adjusting the 20kΩ potentiometer till the PLL is locked. Measure the output frequency. It should be 5 times the input frequency.

4. Repeat the steps 2, 3 for different input frequency.

FREQUENCY MULTIPLIER USING PLL:


C 1

0 . 001uF

C 21nF

C 30 . 01uF

IC 565

INPUT

3

1

810

2

4

7

9 5

+VCC

OUTPUT

-VCC

R 120k

Q 12N 2222A

+VCC

R 21k

13 6

115

11072

R 31k

RESULT:

Thus the frequency multiplier is constructed using PLL and checked for various frequencies


LIC Lab Manual

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