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Transcript of Lic Lab Manual 2013
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Department of Electrical and Electronics Engineering
Lab Manual
131452 LINEAR AND DIGITAL INTEGRATED CIRCUITS
LABORATORY
Class: 2 EEE
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Exp No. 1a STUDY OF LOGIC GATES
AIM:
To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR gates.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408 1
3. OR gate IC 7432 1
4. NOT gate IC 7404 1
5. NAND gate IC 7400 1
6. NOR gate IC 7402 1
7. EX-OR gate IC 7486 1
8. Connecting wires As required
THEORY:
a. AND gate:
An AND gate is the physical realization of logical multiplication operation. It is an
electronic circuit which generates an output signal of ‘1’ only if all the input signals
are ‘1’.
b. OR gate:
An OR gate is the physical realization of the logical addition operation. It is an
electronic circuit which generates an output signal of ‘1’ if any of the input signal is
‘1’.
c. NOT gate:
A NOT gate is the physical realization of the complementation operation. It is an
electronic circuit which generates an output signal which is the reverse of the input
signal. A NOT gate is also known as an inverter because it inverts the input.
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AND GATE
LOGIC DIAGRAM:
PIN DIAGRAM OF IC 7408 :
CIRCUIT DIAGRAM:
TRUTH TABLE:
S.No INPUT OUTPUT
A B Y = A . B
1. 0 0 0
2. 0 1 0
3. 1 0 0
4. 1 1 1
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OR GATE
LOGIC DIAGRAM:
PIN DIAGRAM OF IC 7432 :
CIRCUIT DIAGRAM:
TRUTH TABLE:
S.No INPUT OUTPUT
A B Y = A + B
1. 0 0 0
2. 0 1 1
3. 1 0 1
4. 1 1 1
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NOT GATE
LOGIC DIAGRAM:
PIN DIAGRAM OF IC 7404 :
CIRCUIT DIAGRAM:
TRUTH TABLE:
S.No INPUT OUTPUT
A Y = A’
1. 0 1
2. 1 0
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NAND GATE
LOGIC DIAGRAM:
PIN DIAGRAM OF IC 7400 :
CIRCUIT DIARAM:
TRUTH TABLE:
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S.No INPUT OUTPUT
A B Y = (A . B)’
1. 0 0 1
2. 0 1 1
3. 1 0 1
4. 1 1 0
NOR GATE
LOGIC DIAGRAM:
PIN DIAGRAM OF IC 7402 :
CIRCUIT DIAGRAM:
TRUTH TABLE:
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S.No INPUT OUTPUT
A B Y = (A + B)’
1. 0 0 1
2. 0 1 0
3. 1 0 0
4. 1 1 0
EX-OR GATE
LOGIC DIAGRAM
PIN DIAGRAM OF IC 7486 :
CIRCUIT DIAGRAM:
TRUTH TABLE:
S.No INPUT OUTPUT
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A B Y = A B
1. 0 0 0
2. 0 1 1
3. 1 0 1
4. 1 1 0
d. NAND gate:
A NAND gate is a complemented AND gate. The output of the NAND gate will be
‘0’ if all the input signals are ‘1’ and will be ‘1’ if any one of the input signal is ‘0’.
e. NOR gate:
A NOR gate is a complemented OR gate. The output of the OR gate will be ‘1’ if all
the inputs are ‘0’ and will be ‘0’ if any one of the input signal is ‘1’.
f. EX-OR gate:
An Ex-OR gate performs the following Boolean function,
A B = ( A . B’ ) + ( A’ . B )
It is similar to OR gate but excludes the combination of both A and B being equal to
one. The exclusive OR is a function that give an output signal ‘0’ when the two
input signals are equal either ‘0’ or ‘1’.
PROCEDURE:
1. Connections are given as per the circuit diagram
1. For all the ICs 7th
pin is grounded and 14th
pin is given +5 V supply.
2. Apply the inputs and verify the truth table for all gates.
RESULT:
The truth table of all the basic digital ICs were verified.
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1.b. STUDY OF FLIP-FLOPS USING GATES
Aim : To construct RS, JK, D and T Flip flops using logic gates and
verify truth table for each of it.
Apparatus Required:
S.NO ITEM SPECIFICATION QUANTITY
1
2
3
Digital IC trainer kit
IC7404, IC 7400
IC 7410
QUAD
1
1 each
1
Circuit Diagram :
RS FLIP FLOP
S 1 3 4
2 6 Q
5
9 7400
8 7400
R 10 12
11 Q’
13
TRUTH TABLE
R S Q Q’
0 0 0 1
0 1 1 0
1 0 0 1
1 1 1 1
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JK FLIP FLOP
1 1 3 Q
J 2 12
13 2
CLK 7410 7400
3
4
K 4 6
5 5 6 Q’
TRUTH TABLE
J K Q Q’
0 0 1 0
0 1 1 0
1 0 0 1
1 1 1 1
T FLIP FLOP
1 1 3 Q
J 2 12
13 2
CLK 7410 7400
3
4
4 6
5 5 6 Q’
TRUTH TABLE
D Q Q’
1 1 0
0 0 1
D FLIP FLOP
1 1 3 Q
J 2 12
7404 1 13 2
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CLK 2 7410 7400
3
4
4 6
5 5 6 Q’
TRUTH TABLE
T Q Q’
1 1 1
0 0 1
THEORY :
S-R Flip Flop :
It is formed out of any two NAND gates. It has 2 input SET (s)
and RESET(R) and 2 outputs (Q) and ( Q ). The device has 2
stable states.
J-K Flip Flop :
The uncertainty in the state of S-R Flip Flop when Sn = Rn =1 (fourth row of
truth table) can be eliminated by converting it in to a J-K Flip Flop. The data
inputs are J and K, which are ANDed with Q and Q respectively to obtain S and R
inputs.
D Flip Flop :
If we use only the middle 2 rows of the truth table of the
S-R or J-K Flip Flop, we obtain a D type Flip Flop. It has only one input referred
to as D input or data input.
T Flip Flop :
In a J-K Flip Flop, if J = K, the resulting FLIP-FLOP is
Referred to as a T type Flip Flop. It has only one input, referred to as T input. If
T=1 it acts as a toggle switch. For every clock pulse, the output Q changes.
Procedure:
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• Give connections as per the circuit diagram.
• Inputs are given to the circuit making high ‘1’ i.e. +5 V or + Vcc supply
and for low ‘0’ i.e. GND, clock input is given from the IC trainer kit.
• The binary input 00, 01, 10, 11 are given and the outputs are observed.
• Repeat the same procedure for JK, D, and T Flip-Flops and verify the truth
table.
Result: Thus the RS, JK, D, and T Flip Flops were constructed and its truth table were
verified.
Exp No. 2a HALF ADDER & FULL ADDER
AIM:
To design and verify the truth table of the Half Adder & Full Adder circuits.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408
3. OR gate IC 7432
4. NOT gate IC 7404
5. EX-OR gate IC 7486
6. Connecting wires As required
THEORY:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 102
The first three operations produce a sum of whose length is one digit, but when the last
operation is performed the sum is two digits. The higher significant bit of this result is called
a carry and lower significant bit is called the sum.
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HALF ADDER:
A combinational circuit which performs the addition of two bits is called half adder. The
input variables designate the augend and the addend bit, whereas the output variables
produce the sum and carry bits.
FULL ADDER:
A combinational circuit which performs the arithmetic sum of three input bits is called full
adder. The three input bits include two significant bits and a previous carry bit. A full adder
circuit can be implemented with two half adders and one OR gate.
HALF ADDER
TRUTH TABLE:
S.No INPUT OUTPUT
A B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 0 1
DESIGN:
From the truth table the expression for sum and carry bits of the output can be obtained as,
Sum, S = A B
Carry, C = A . B
CIRCUIT DIAGRAM:
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FULL ADDER
TRUTH TABLE:
S.No INPUT OUTPUT
A B C SUM CARRY
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
DESIGN:
From the truth table the expression for sum and carry bits of the output can be obtained as,
SUM = A’B’C + A’BC’ + AB’C’ + ABC
CARRY = A’BC + AB’C + ABC’ +ABC
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
SUM
SUM = A’B’C + A’BC’ + AB’C’ + ABC = A B C
CARRY
CARRY = AB + AC + BC
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CIRCUIT DIAGRAM:
PROCEDURE:
1. Connections are given as per the circuit diagrams.
2. For all the ICs 7th
pin is grounded and 14th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
RESULT:
The design of the half adder and full adder circuits was done and their truth tables were
verified.
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2.b. HALF SUBTRACTOR & FULL SUBTRACTOR
AIM:
To design and verify the truth table of the Half Subtractor & Full Subtractor circuits.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408
3. OR gate IC 7432
4. NOT gate IC 7404
5. EX-OR gate IC 7486
6. Connecting wires As required
THEORY:
The arithmetic operation, subtraction of two binary digits has four possible elementary
operations, namely,
0 - 0 = 0
0 - 1 = 1 with 1 borrow
1 - 0 = 1
1 - 1 = 0
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In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the
second operation the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed.
HALF SUBTRACTOR:
A combinational circuit which performs the subtraction of two bits is called half subtractor.
The input variables designate the minuend and the subtrahend bit, whereas the output
variables produce the difference and borrow bits.
FULL SUBTRACTOR:
A combinational circuit which performs the subtraction of three input bits is called full
subtractor. The three input bits include two significant bits and a previous borrow bit. A full
subtractor circuit can be implemented with two half subtractors and one OR gate.
HALF SUBTRACTOR
TRUTH TABLE:
S.No INPUT OUTPUT
A B DIFF BORR
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
DESIGN:
From the truth table the expression for difference and borrow bits of the output can be
obtained as,
Difference, DIFF = A B
Borrow, BORR = A’ . B
CIRCUIT DIAGRAM:
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FULL SUBTRACTOR
TRUTH TABLE:
S.No INPUT OUTPUT
A B C DIFF BORR
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
DESIGN:
From the truth table the expression for difference and borrow bits of the output can be
obtained as,
Difference, DIFF= A’B’C + A’BC’ + AB’C’ + ABC
Borrow, BORR = A’BC + AB’C + ABC’ +ABC
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
DIFFERENCE
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DIFF = A’B’C + A’BC’ + AB’C’ + ABC = A B C
BORROW
BORR = A’B + A’C + BC
CIRCUIT DIAGRAM:
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PROCEDURE:
1. Connections are given as per the circuit diagrams.
2. For all the ICs 7th
pin is grounded and 14th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the half subtractor and full subtractor
circuits.
RESULT:
The design of the half subtractor and full subtractor circuits was done and their truth tables
were verified.
2.c. IMPLEMENTATION OF BOOLEAN FUNCTIONS
AIM:
To design the logic circuit and verify the truth table of the given Boolean expression,
F (A,B,C,D) = Σ (0,1,2,5,8,9,10)
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408
3. OR gate IC 7432
4. NOT gate IC 7404
5. NAND gate IC 7400
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6. NOR gate IC 7402
7. EX-OR gate IC 7486
8. Connecting wires As required
DESIGN:
Given , F (A,B,C,D) = Σ (0,1,2,5,8,9,10)
The output function F has four input variables hence a four variable Karnaugh Map is used to
obtain a simplified expression for the output as shown,
From the K-Map,
F = B’ C’ + D’ B’ + A’ C’ D
Since we are using only two input logic gates the above expression can be re-written as,
F = C’ (B’ + A’ D) + D’ B’
Now the logic circuit for the above equation can be drawn.
CIRCUIT DIAGRAM:
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TRUTH TABLE:
S.No INPUT OUTPUT
A B C D F=D’B’+C’(B’+A’D)
1. 0 0 0 0 1
2. 0 0 0 1 1
3. 0 0 1 0 1
4. 0 0 1 1 0
5. 0 1 0 0 0
6. 0 1 0 1 1
7. 0 1 1 0 0
8. 0 1 1 1 0
9. 1 0 0 0 1
10. 1 0 0 1 1
11. 1 0 1 0 1
12. 1 0 1 1 0
13. 1 1 0 0 0
14. 1 1 0 1 0
15. 1 1 1 0 0
16. 1 1 1 1 0
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PROCEDURE:
1. Connections are given as per the circuit diagram
2. For all the ICs 7th
pin is grounded and 14th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the given Boolean expression.
RESULT:
The truth table of the given Boolean expression was verified.
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Exp No.3 CODE CONVERTERS
AIM :
To construct and verify the truth table of Binary to Gray code, Gray to Binary
Code, BCD to Excess-3 code converter circuits.
APPARATUS REQUIRED:
S.NO Particular Name SPECIFICATION QUANTITY
1
2
3
4
Digital IC trainer kit
IC 7486
IC 7404
Connecting Wires
----
QUAD
QUAD
1
3
1
PROCEDURE:
1. Give connections as per the circuit diagram
2. Inputs are given to the circuit making high ‘1’ i.e. +5 V or
+ Vcc supply to the 14th
pin and for low ‘0’ i.e. GND to the 7th
pin of gate IC
3. Verify the truth table as given for all the code converter
CIRCUIT DIAGRAM:
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TRUTH TABLE:
INPUTS(Binary Code) OUTPUTS (Gray Code)
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
CIRCUIT DIAGRAM:
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TRUTH TABLE:
INPUTS(Gray Code) OUTPUTS(Binary Code)
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
CIRCUIT DIAGRAM:
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TRUTH TABLE:
INPUTS(BCD Code) OUTPUTS(Binary Code)
A B C D B3 B2 B1 B0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
RESULT:
The code converter circuits are all constructed and truth table is verified.
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3.b. PARITY GENERATOR & CHECKER
AIM:
To design and verify the truth table of a three bit Odd Parity generator and checker.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. EX-OR gate IC 7486
3. NOT gate IC 7404
4. Connecting wires As required
THEORY:
A parity bit is used for the purpose of detecting errors during transmission of binary
information. A parity bit is an extra bit included with a binary message to make the number
of 1’s either odd or even. The message including the parity bit is transmitted and then
checked at the receiving end for errors. An error is detected if the checked parity does not
correspond with the one transmitted. The circuit that generates the parity bit in the
transmitter is called a parity generator and the circuit that checks the parity in the receiver is
called a parity checker.
In even parity the added parity bit will make the total number of 1’s an even amount and in
odd parity the added parity bit will make the total number of 1’s an odd amount.
In a three bit odd parity generator the three bits in the message together with the parity bit are
transmitted to their destination, where they are applied to the parity checker circuit. The
parity checker circuit checks for possible errors in the transmission.
Since the information was transmitted with odd parity the four bits received must have an
odd number of 1’s. An error occurs during the transmission if the four bits received have an
even number of 1’s, indicating that one bit has changed during transmission. The output of
the parity checker is denoted by PEC (parity error check) and it will be equal to 1 if an error
occurs, i.e., if the four bits received has an even number of 1’s.
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ODD PARITY GENERATOR
TRUTH TABLE:
S.No
INPUT
( Three bit message)
OUTPUT
( Odd Parity bit)
A B C P
1. 0 0 0 1
2. 0 0 1 0
3. 0 1 0 0
4. 0 1 1 1
5. 1 0 0 0
6. 1 0 1 1
7. 1 1 0 1
8. 1 1 1 0
From the truth table the expression for the output parity bit is,
P( A, B, C) = Σ (0, 3, 5, 6)
Also written as,
P = A’B’C’ + A’BC + AB’C + ABC’ = (A B C) ‘
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CIRCUIT DIAGRAM:
ODD PARITY GENERATOR
ODD PARITY CHECKER
TRUTH TABLE:
S.No
INPUT
( four bit message
Received )
OUTPUT
(Parity error check)
A B C P X
1. 0 0 0 0 1
2. 0 0 0 1 0
3. 0 0 1 0 0
4. 0 0 1 1 1
5. 0 1 0 0 0
6. 0 1 0 1 1
7. 0 1 1 0 1
8. 0 1 1 1 0
9. 1 0 0 0 0
10. 1 0 0 1 1
11. 1 0 1 0 1
12. 1 0 1 1 0
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13. 1 1 0 0 1
14. 1 1 0 1 0
15. 1 1 1 0 0
16. 1 1 1 1 1
From the truth table the expression for the output parity checker bit is,
X (A, B, C, P) = Σ (0, 3, 5, 6, 9, 10, 12, 15)
The above expression is reduced as,
X = (A B C P) ‘
CIRCUIT DIAGRAM:
ODD PARITY CHECKER
PROCEDURE:
1. Connections are given as per the circuit diagrams.
2. For all the ICs 7th
pin is grounded and 14th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the Parity generator and checker.
RESULT:
The design of the three bit odd Parity generator and checker circuits was done and their truth
tables were verified.
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Expt. No. 4 MULTIPLEXER & DEMULTIPLEXER
AIM:
To design and verify the truth table of a 4X1 Multiplexer & 1X4 Demultiplexer.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. OR gate IC 7432
3. NOT gate IC 7404
4. AND gate ( three input ) IC 7411
5. Connecting wires As required
THEORY:
Multiplexer is a digital switch which allows digital information from several sources to be
routed onto a single output line. The basic multiplexer has several data input lines and a
single output line. The selection of a particular input line is controlled by a set of selection
lines. Normally, there are 2n input lines and n selector lines whose bit combinations
determine which input is selected. Therefore, multiplexer is ‘many into one’ and it provides
the digital equivalent of an analog selector switch.
A Demultiplexer is a circuit that receives information on a single line and transmits this
information on one of 2n possible output lines. The selection of specific output line is
controlled by the values of n selection lines.
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DESIGN:
4 X 1 MULTIPLEXER
LOGIC SYMBOL:
TRUTH TABLE:
S.No SELECTION INPUT OUTPUT
S1 S2 Y
1. 0 0 I0
2. 0 1 I1
3. 1 0 I2
4. 1 1 I3
PIN DIAGRAM OF IC 7411:
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CIRCUIT DIAGRAM:
1X4 DEMULTIPLEXER
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LOGIC SYMBOL:
TRUTH TABLE:
S.No INPUT OUTPUT
S1 S2 Din Y0 Y1 Y2 Y3
1. 0 0 0 0 0 0 0
2. 0 0 1 1 0 0 0
3. 0 1 0 0 0 0 0
4. 0 1 1 0 1 0 0
5. 1 0 0 0 0 0 0
6. 1 0 1 0 0 1 0
7. 1 1 0 0 0 0 0
8. 1 1 1 0 0 0 1
CIRCUIT DIAGRAM:
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PROCEDURE:
1. Connections are given as per the circuit diagrams.
2. For all the ICs 7th
pin is grounded and 14th
pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the multiplexer & demultiplexer.
RESULT:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth
tables were verified.
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Expt. No. 5 ASYNCHRONOUS DECADE COUNTER
AIM:
To implement and verify the truth table of an asynchronous decade counter.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. JK Flip Flop IC 7473 2
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4. NAND gate IC 7400 1
5. Connecting wires As required
THEORY:
Asynchronous decade counter is also called as ripple counter. In a ripple counter the flip flop
output transition serves as a source for triggering other flip flops. In other words the clock
pulse inputs of all the flip flops are triggered not by the incoming pulses but rather by the
transition that occurs in other flip flops. The term asynchronous refers to the events that do
not occur at the same time. With respect to the counter operation, asynchronous means that
the flip flop within the counter are not made to change states at exactly the same time, they
do not because the clock pulses are not connected directly to the clock input of each flip flop
in the counter.
PIN DIAGRAM OF IC 7473:
CIRCUIT DIAGRAM:
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TRUTH TABLE:
S.No CLOCK
PULSE
OUTPUT
D(MSB) C B A(LSB)
1 - 0 0 0 0
2 1 0 0 0 1
3 2 0 0 1 0
4 3 0 0 1 1
5 4 0 1 0 0
6 5 0 1 0 1
7 6 0 1 1 0
8 7 0 1 1 1
9 8 1 0 0 0
10 9 1 0 1 0
11 10 0 0 0 0
PROCEDURE:
1. Connections are given as per the circuit diagrams.
2. Apply the input and verify the truth table of the counter.
RESULT:
The truth table of the Asynchronous decade counter was hence verified.
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Expt. No. 6 IMPLEMENTATION OF SHIFT REGISTERS
AIM:
To implement and verify the truth table of a serial in serial out shift register.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. D Flip Flop IC 7474 2
3. Connecting wires As required
THEORY:
A register capable of shifting its binary information either to the left or to the right is called a
shift register. The logical configuration of a shift register consists of a chain of flip flops
connected in cascade with the output of one flip flop connected to the input of the next flip
flop. All the flip flops receive a common clock pulse which causes the shift from one stage
to the next.
The Q output of a D flip flop is connected to the D input of the flip flop to the left. Each
clock pulse shifts the contents of the register one bit position to the right. The serial input
determines, what goes into the right most flip flop during the shift. The serial output is taken
from the output of the left most flip flop prior to the application of a pulse. Although this
register shifts its contents to its left, if we turn the page upside down we find that the register
shifts its contents to the right. Thus a unidirectional shift register can function either as a
shift right or a shift left register.
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PIN DIAGRAM OF IC 7474:
CIRCUIT DIAGRAM:
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TRUTH TABLE:
For a serial data input of 1101,
S.NO CLOCK
PULSE
INPUTS OUTPUTS
D1 D2 D3 D4 Q1 Q2 Q3 Q4
1 1 1 X X X 1 X X X
2 2 1 1 X X 1 1 X X
3 3 0 1 1 X 0 1 1 X
4 4 1 0 1 1 1 0 1 1
5 5 X 1 0 1 X 1 0 1
6 6 X X 1 0 1 X 1 0
7 7 X X X 1 0 X X 1
8 8 X X X X X X X X
PROCEDURE:
1. Connections are given as per the circuit diagrams.
2. Apply the input and verify the truth table of the counter.
RESULT:
The truth table of a serial in serial out left shift register was hence verified.
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Expt. No.7 Op-amp Applications
a. INVERTING AMPLIFIER
AIM:
To design an Inverting Amplifier for the given specifications using Op-Amp IC 741.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors As required
7. Connecting wires and probes As required
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator,
appropriate input voltage is applied to the inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage
waveforms are plotted in a graph sheet.
PIN DIAGRAM:
CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:
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DESIGN:
We know for an inverting Amplifier ACL = RF / R1
Assume R1 ( approx. 10 KΩ ) and find Rf
Hence Vo = - ACL Vi
OBSERVATIONS:
S.No Input Output
Practical Theoretical
1. Amplitude
( No. of div x Volts per div )
2. Time period
( No. of div x Time per div )
MODEL GRAPH:
(V)
Vin
Vo
(V)
t(sec)
t(sec)
Inverting amp
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b. NON - INVERTING AMPLIFIER
AIM:
To design a Non-Inverting Amplifier for the given specifications using Op-Amp IC 741.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors As required
7. Connecting wires and probes As required
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator,
appropriate input voltage is applied to the non - inverting input terminal of the Op-
Amp.
4. The output voltage is obtained in the CRO and the input and output voltage
waveforms are plotted in a graph sheet.
PIN DIAGRAM:
CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:
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DESIGN:
We know for a Non-inverting Amplifier ACL = 1 + ( RF / R1)
Assume R1 ( approx. 10 KΩ ) and find Rf
Hence Vo = ACL Vi
OBSERVATIONS:
S.No Input Output
Practical Theoretical
1. Amplitude
( No. of div x Volts per div )
2. Time period
( No. of div x Time per div )
MODEL GRAPH:
(V)
Vin
Vo
(V)
t(sec)
t(sec)
Non-Inverting amp
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c. DIFFERENTIATOR
AIM:
To design a Differentiator circuit for the given specifications using Op-Amp IC 741.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors
7. Capacitors
PIN DIAGRAM:
CIRCUIT DIAGRAM OF DIFFERENTIATOR:
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DESIGN :
[ To design a differentiator circuit to differentiate an input signal that varies in
frequency from 10 Hz to about 1 KHz. If a sine wave of 1 V peak at 1000Hz is applied to
the differentiator , draw its output waveform.]
Given fa = 1 KHz
We know the frequency at which the gain is 0 dB, fa = 1 / (2π Rf C1)
Let us assume C1 = 0.1 µF ; then
Rf = _________
Since fb = 20 fa , fb = 20 KHz
We know that the gain limiting frequency fb = 1 / (2π R1 C1)
Hence R1 = _________
Also since R1C1 = Rf Cf ; Cf = _________
Given Vp = 1 V and f = 1000 Hz, the input voltage is Vi = Vp sin ωt
We know ω = 2πf
Hence Vo = - Rf C1 ( dVi /dt )
= - 0.94 cos ωt
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator,
appropriate input voltage is applied to the inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage
waveforms are plotted in a graph sheet.
OBSERVATIONS:
S.No Input Output
1. Amplitude
( No. of div x Volts per div )
2. Time period
( No. of div x Time per div )
MODEL GRAPH:
IV
Vin
Vo
t
t
-IV
Model graph
2V
-2V
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d. INTEGRATOR
AIM:
To design an Integrator circuit for the given specifications using Op-Amp IC 741.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC 741 1
5. Bread Board 1
6. Resistors
7. Capacitors
8. Connecting wires and probes As required
PIN DIAGRAM:
CIRCUIT DIAGRAM OF INTEGRATOR:
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DESIGN:
[ To obtain the output of an Integrator circuit with component values R1Cf = 0.1ms , Rf = 10
R1 and Cf = 0.01 µF and also if 1 V peak square wave at 1000Hz is applied as input.]
We know the frequency at which the gain is 0 dB, fb = 1 / (2π R1 Cf)
Therefore fb = _____
Since fb = 10 fa , and also the gain limiting frequency fa = 1 / (2π Rf Cf)
We get , R1 = _______ and hence Rf = __________
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator,
appropriate input voltage is applied to the inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage
waveforms are plotted in a graph sheet.
OBSERVATIONS:
S.No Input Output
1. Amplitude
( No. of div x Volts per div )
2. Time period
( No. of div x Time per div )
MODEL GRAPH:
Vin
Vo
t
t
Model graph
t
t
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e. Summing Amplifier: [Inverting]
Design: R1=R2=R3=R & R = Rf = 4.7KΩ; RL = 10 KΩ; RCOMP = R1 || R2 || R3 || Rf
VO = - Rf / R [V1+V2+V3]
Circuit Diagram
V2
V1 +12V
+
-
IC 7413
26
74
RL
Vo = - Rf/R [V1+V2+V3]
R2
Rom
Rf
-12V
V3
R1
0
R3
RCOMP
f. Schmitt Trigger (comparator):
Design : VCC = 12 V; VSAT
VUT = + [VSAT R2] / [R1+R2] & V
Circuit Diagram
Model Graph
Vin
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Schmitt Trigger (comparator):
SAT = 0.9 VCC; R1= 47KΩ; R2 = 120Ω
] & VLT = - [VSAT R2] / [R1+R2] & HYSTERSIS [H] =
+12V
R1
-12V
R2
0
+
-
3
26
74
RL = 10K
] & HYSTERSIS [H] = VUT - VLT
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g. Voltage Follower (Slew rate verifications):
Design:
Vin = Vout [Unity Gain] & Rin = ∞ & Rf = 0
Circuit Diagram
-12V
Vo
+
-
U1
IC 7413
26
74
I1
1V/1KHz
0
+12V
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Procedure
1. Connect the circuit as shown in the circuit
2. Set the input voltage as 5V (p-p) at 1KHz. (Input should be always less than Vcc)
3. Note down the output voltage at CRO
4. To observe the phase difference between the input and the output, set the CRO in dual
Mode and switch the trigger source in CRO to CHI.
5. Plot the input and output waveforms on the graph.
Observation:
Peak to peak amplitude of the output = Volts.
Frequency = Hz.
Upper threshold voltage = Volts.
Lower threshold voltage = Volts.
Result
Thus Applications of op-amp were studied.
Expt. 8 TIMER IC APPLICATIONS
a. ASTABLE MULTIVIBRATOR
AIM:
To design an Astable multivibrator circuit for the given specifications using 555 Timer IC.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Timer IC IC 555 1
5. Bread Board 1
6. Resistors
7. Capacitors
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8. Connecting wires and probes As required
PIN DIAGRAM:
CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR
DESIGN:
[ To design an astable multivibrator with 65% duty cycle at 4 KHz frequency, assume C=
0.01 µF]
Given f= 4 KHz,
Therefore, Total time period, T = 1/f = ____________
We know, duty cycle = tc / T
Therefore, tc = ------------------------
and td = ____________
We also know for an astable multivibrator
td = 0.69 (R2) C
Therefore, R2 = _____________
tc = 0.69 (R1 + R2) C
Therefore, R1 = _____________
PROCEDURE:
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1. Connections are given as per the circuit diagram.
2. + 5V supply is given to the + Vcc terminal of the timer IC.
3. At pin 3 the output waveform is observed with the help of a CRO
4. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc voltage
waveforms are plotted in a graph sheet.
OBSERVATIONS:
S.No
Amplitude
( No. of div x
Volts per div )
Time period
( No. of div x
Time per div )
tc td
1.
Output Voltage , Vo
2.
Capacitor voltage , Vc
MODEL GRAPH:
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RESULT:
The design of the Astable multivibrator circuit was done and the output voltage and capacitor
voltage waveforms were obtained.
b. MONOSTABLE MULTIVIBRATOR
AIM:
To design a monostable multivibrator for the given specifications using 555 Timer IC.
APPARATUS REQUIRED:
Voltage in volts
Voltage across the capacitor
t(mse)
vo
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S.No Name of the Apparatus Range Quantity
1. Function Generator 3 MHz, Analog 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Timer IC IC 555 1
5. Bread Board 1
6. Resistors
7. Capacitors
8. Connecting wires and probes As required
PIN DIAGRAM:
CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:
DESIGN:
[ To design a monostable multivibrator with tp = 0.616 ms , assume C = 0.01 µF ]
Given tp = 0.616 ms = 1.1 R1 C
Therefore, R1 = _____________
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. + 5V supply is given to the + Vcc terminal of the timer IC.
3. A negative trigger pulse of 5V, 2 KHz is applied to pin 2 of the 555 IC
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4. At pin 3 the output waveform is observed with the help of a CRO
5. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc voltage
waveforms are plotted in a graph sheet.
OBSERVATIONS:
S.No
Amplitude
( No. of div x
Volts per div )
Time period
( No. of div x
Time per div )
ton toff
1.
Trigger input
2.
Output Voltage , Vo
3.
Capacitor voltage , Vc
MODEL GRAPH:
RESULT:
The design of the Monostable multivibrator circuit was done and the input and output
waveforms were obtained.
EX.No. 9 DAC and ADC Converters
a. DAC CONVERTERS
Vin
VC
VO
Vsat
Vββββsat
VD
t
t
t
T–V sat
TP
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Aim:-
To design R-2R ladder type DAC using op-amp.
Components Required:-
S.No Components Range Quantity
1. Op-amp IC 741 1
2. Resistors 10KΩ,20KΩ 1
3. DPDT(switch) 1
4. Dual Tracking Supply (0-30)V 1
5. Voltage Source (0-30)V 1
Circuit Diagram: 4-Bit R/2R Ladder DAC:
Design:-
Output voltage,
+++−=
42
432
322
212
1bbbb
R
fR
RVoV
Binary value=1000(given)
Output voltage=6v (given)
Reference resistor =10KΩ (given)
Reference Voltage, VR=10V (given)
∴ Rf =12kΩ
Resolution,
f
RR
RV
nV ××=
2
1
Ω×Ω
×= kk
VV 12
10
10
42
1
2R
R
+
-LM741C3
26
7 14 5
2R
R
2R
VR
2R
R
Rf =12k
R
Vo
2R
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75.0=V
Procedure:-
1. Connections are given as per the circuit diagram.
2. The power supply is switched on.
3. Reference voltage is set as 10V.
4. Binary values are applied according to the binary input values.
5. The output voltage is noted down.
6. The output voltage obtained is compared with the given output voltage.
Result:-
Thus the R-2R ladder type DAC was designed using Op-amp.
b. ADC CONVERTORS
Aim:-
To design Flash type ADC and Successive approximation type ADC using op
Components Required:-
S.No Components
1. Op-amp
2. Resistors
3. DPDT(switch)
4. Dual Tracking Supply
5. Voltage Source
Circuit diagram: Flash ADC
Circuit diagram:
Successive approximation ADC
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To design Flash type ADC and Successive approximation type ADC using op
Range Quantity
IC 741
10KΩ,20KΩ
Supply (0-30)V
(0-30)V
Flash ADC
approximation ADC
To design Flash type ADC and Successive approximation type ADC using op-amp.
Quantity
1
1
1
1
1
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Procedure:-
1. Connections are given as per the circuit diagram.
2. The power supply is switched on.
3. Reference voltage is set as 10V.
4. Binary values are applied according to the binary input values.
5. The output voltage is noted down.
6. The output voltage obtained is compared with the given output voltage.
Result:-
Thus the ADC circuits were designed using Op-amp.
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EX.No. 10 Study of PLL and VCO characteristics
a. Voltage to frequency characteristics of VCO
Aim:
To study the voltage to frequency characteristics of VCO
Circuit diagram
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b. Frequency multiplication Of PLL IC
Aim: To study the Frequency multiplication of PLL IC.
Circuit diagram
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Result:
Thus the PLL and VCO characteristics were studied.
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