LHCb Scintillating Fiber detector - CERN · Scintillating Fiber Detector (SciFi) Wilco Vink Twepp...

LHCb Scintillating Fiber detector

Front end electronics

Design & Test

On behalf of the SciFi group,

Wilco Vink

TWEPP 2016

LHCb SciFi detector overview

The various boards in a Read Out Box

Design, production and test of the prototype PCBs

Front end electronics test system

Outline

Wilco Vink Twepp 2016 2

Wilco Vink Twepp 2016

LHCb detector

Scintillating Fiber detector

Scintillating Fiber Detector (SciFi)

Twepp 2016 Wilco Vink 4

One station

3 stations x 4 detector planes 24 modules and Read Out

Boxes per plane 250 um thick, 2,5 m long

scintillating fibers Mirror in the middle

5m

6m

Exploded view: Read Out Box (ROB)


SiPMs on flex cables

Cold box

Scintillating Fibers

Master Boards

Clusterization Boards

PACIFIC Boards

Cooling Plate

5

½ ROB electronics


FPGA

SCA

VT

Tx

VT

Rx

VT

Tx

VT

Tx

VT

Tx

Pwr

MSTR

GBT

DATA

GBT

DATA

GBT

DATA

GBT

DATA

GBT

DATA

GBT

DATA

GBT

DATA

GBT

DATA

GBT

FPGA FPGA

SCA

FPGA FPGA

SCA

FPGA FPGA

SCA

FPGA

FPGA

Master

Board

Clusterization Clusterization Clusterization Clusterization

SiPM SiPM SiPM SiPM SiPM SiPM SiPM SiPM

PACIFIC PACIFIC PACIFIC PACIFIC

SCA

Master Board

◦ Master GBTX Timing, Fast and slow controls distribution

◦ Data GBTXs Data serialisation

◦ Power supplies (11 FeastMP modules)

◦ Versatile link optical components

Clusterization board

◦ Microsemi IGLOO2 FPGA based Clustering algorithm

◦ SCA for slow controls Clusterization FPGAs and PACIFIC ASICs

PACIFIC Board

◦ Amplifier, shaper, integrator and ADCs, 2b/channel output based on three threshold values

SiPM: Silicon Photo Multiplier modules

◦ 2 arrays of 64 channel avalanche photodiodes

6

288 Read Out Boxes: ◦ 2 Master Boards

◦ 8 Clusterization Boards

◦ 8 Pacific Boards

◦ 16 Silicon Photo Multipliers (SiPMs)

Total: ◦ 576 Master Boards

◦ 2304 Clusterization and Pacific Boards

Some numbers


How can we produce and test the electronics?

7

Optimize PCBs and PCBAs for production

◦ Design For eXcellence (DFX)

Early design involvement

After the ROBs electronics have been assembled we test them with a full functional tester before mounting them on the detector

Board and system testability


Design For Manufacturability (DFM)

Design For Testability (DFT)

Design For eXcellence (DFX)


Manufacturability

Minimize cost

High first pass yield

Re-produceable

Highly testable (electrical)

Reliable product

Early Feedback

Process efficiency

9

Design For Manufacturability (DFM)

◦ Design with many nets: ten 400 pins 0,8mm pitch BGAs and four 400 pins high pin count connectors

◦ High density of 0402 parts under BGAs

Board design: component placement and footprints optimized for assembly process

◦ Minimize the risk of errors during assembly

◦ Minimize assembly stages minimize the cost

PCB Design : DFM


DFM design flow


Phase 1

Specify PCB: material, stackup, vias,

tracewidths and clearances.

BOM

Schematics

Component layers

Outer copper layers

Phase 2

Full BOM

Finish board layout (ODB++)

Implement recommendations

Component placement

Footprint check

Production IPC class

Analysis of makeability:

Footprint Check

Component placement check

Netlist analysis

Phase 0

Specifications

Design idea: block diagram

Select components

DFM rules

Preferred component list

Designer: Reviewer:

11

Design improvements due to DFM analysis ◦ PCB specifications in

cooperation with manufacturer

◦ Changed footprints of some components

◦ Use Pin In Paste(PIP) for through hole components no wave soldering needed

DFM: lessons learned


DFT

◦ Design optimized for test during & after assembly Optimize for test connectivity between Boundary scan capable devices

Place test points for probe access, when not possible component pads can be used

DFT checks during and after assembly:

◦ 3DAOI : 3D Automated Optical Inspection Optical inspection at three different stages of the assembly process, after:

applying paste

component placement

reflow soldering process

◦ Automated X-ray inspection(AXI)

◦ Flying probe test Test electrical connections and component values

◦ In Circuit Testing(ICT) Dedicated needle card

◦ EBST : Extended Boundary Scan Test Test electrical connections between components. Active loopback board(s) are used for routing to

connectors.

Design For Test (DFT):


DFT design flow


Phase 1

• Netlist

• Schematics

• Boundary scan files(BSDL)

• Full BOM

Phase 2

• Add test points

• Layout changes

• CAD data (ODB++)

• Updated Schematics

• Preliminary reports:

• Test coverage

• Test strategy

• CAD script files containing desired

test points

• Final reports:

• Test coverage

• Test strategy

• Percentage of slip through

Phase 0

• Design idea: Block diagram

• Select components

• Traceability

• DFT rules

• Data exchange guidelines

Designer: Reviewer:

14

Applied changes for DFT:

◦ Two JTAG chains One for remotely re-programming the FPGA and for BS

One additional BS chain for 9 400 pins BGAs

◦ Test points for flying probe access, minimized the usage of component pads for test access.

Advised Test strategy:

◦ 3DAOI : 3D Automated Optical Inspection Optical inspection at three different stages of the assembly process,

after: applying paste

component placement

reflow soldering process

◦ Flying probe test (FPT) Test electrical connections and component values

◦ EBST : Extended Boundary Scan Test Test electrical connections between components. Active loopback

board(s) are used for routing to connectors.

DFT: lessons learned


DFT reports


Master Board Clusterization Board

16

Full functional tester of the ROB electronics ◦ The electronics will be mounted at the detector frame on top of the

coldbox

◦ Sixteen SiPM flexcable connections between electronics and cold box

◦ Full functional test is required prior installation of the electronics, therefore we are designing a front end tester to inject individual test pulses at all 2048 channels of a ROB

ROB tester


Full functional test of the ROB electronics

Based on standard LHCb control and readout via MiniDAQ. Both hardware and software

Front end tester:

◦ 2048 injector circuits for individual pulse injection

◦ Design challenges Tuneable SiPM pulse emulator

board space required per channel does not fit the available width 512mm

ROB electronics full functional test


16 Data GBTX

data links

MiniDAQ

Control DAQ

Read Out Box electronics Two Master Boards

Eight Clusterization Boards

Eight Pacific boards

Front end tester 2048 channel SiPM pulse emulator

2048 channels

2

Ctrl

PC

10

Gbe

Gbe

18

Two types of boards and a flex cable to connect the ROB under test

◦ Eight pulse injector PCBs developed, 256 pulse injectors per board

◦ Control board based on the same electronics as our front end board to be able to reuse control software

◦ GBTX and GBT SCA chipset, Controls distributed via eight cables to pulse Injector boards

◦ 16 Flex cables, each cable fan-out 128 inputs to eight boards which each 16 pulse injectors


ROB

under test

Test pulse injector:

8 PCBs

Control Board

3D image of the Flex

cable

Front end tester

Test Pulse Injector Control board(TPIC)

84 x 160 mm;

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Boards can be mounted in the Read Out Box after assembly ◦ Not needed to test them individually

Full functional tester in development ◦ Used to test ROBs after assembly, and a second time prior

installation on the detector.

The percentage of slip through fits in the number of spares, which gives us the ability and time to further investigate and repair faulty boxes

Conclusion


Thanks for your attention!

Acknowledgements:

Ulisses Carneiro, Mauricio Feo, Jan Koopstra, Charles

Ietswaard, Hans Verkooijen, Antonio Pellegrino TWEPP 2016

[email protected]

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LHCb Scintillating Fiber detector - CERN · Scintillating Fiber Detector (SciFi) Wilco Vink Twepp...

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