Leveraging THE commercial SECTOR and providing ...• ≤ 5µm HIC length and pitch • ~5 HBTs, 4...

LEVERAGING THE COMMERCIAL SECTOR AND PROVIDING DIFFERENTIATION THROUGH FUNCTIONAL DISAGGREGATION

Dr. Daniel S. Green, DARPA/MTO Program Manager

DISTRIBUTION A. Approved for public release: distribution unlimited.

The DARPA solution is to provide a menu of hardware security options that can be selectively applied based on need

2

DAHI and CHIPS can help protect against the malicious introduction of unknown functionalities into ASIC products.


3DISTRIBUTION A. Approved for public release: distribution unlimited.

Heterogeneous integration: Broadens the device material options

SiGe HBT

InP HBT

ABCS HBT

ABCS HEMT

InP HEMT

Si MOSFET

104

103

102

101

100 101 102 103 104 105 106 107 108 109 1010

Terminology: InP = indium phosphide, GaN = gallium nitride, SiGe = silicon germanium, ABCS = antimonide-based compound semiconductorHBT = heterojunction bipolar transistor, HEMT = high electron mobility transistor, CMOS = complementary metal oxide semiconductorCOSMOS = Compound Semiconductor Materials on Silicon

Number of transistors

John

son

Figu

re o

f Mer

it (G

Hz*

Volt)

GaN HEMT

GaAs MESFET

Si CMOS

DiverseAccessibleHeterogeneousIntegration

Trusted ICs

COSMOS program showed the promise of heterogeneous integration

D/A converter

100

1000

A/D converter

Transistor-scale Integration Technology

Yield Enhancement & Circuit Integration

Advanced Circuits

10

• ~10 heterogeneous interconnects (HICs)

• ≤ 5µm HIC length and pitch• ~5 HBTs, 4 CMOS • ~500 HICs

• ~400 HBTs, 3200 CMOS.

COSMOSPhase I completed

COSMOSPhase II completed

FILTER

I/2 I I 2I 4I4I4I

R-2R

D16D15D10D9D8D1D0CLK

DEGLITCHER SWITCH DAC

VOUT

• ~1800 HICS.• ~1000HBTs, 18000 CMOS

Differential amplifier

6-BITFOLDING

ADCS/H 6

66-BIT

FOLDING ADC

66-BIT

FOLDING ADC

66-BIT

FOLDING ADC

S/H

S/H

S/H

S/H

S/H

6SERIAL

INTERFACE

6SERIAL

INTERFACE

6SERIAL

INTERFACE

6SERIAL

INTERFACE

23 GHzCLK

OU

TPU

T D

ATA

(24

Bits

@ 5

.75

Gsp

s)

TIMINGGENERATOR CALIBRATION

AIN_A

AIN_B

# of

Het

erog

eneo

us In

terc

onne

cts

COSMOS: Demonstrated benefits of integration of completed devices

FY07 FY08 FY09 FY10 FY11 FY12 FY13

COSMOSPhase III completed

1. Developed technology for intimate integration of III-V devices and Si.

2. Demonstrated world-record capabilities with heterogeneous circuits.

3. Clarified benefits of integration processes that use finished devices.

4. Demonstrated fine-pitch interconnect (3um), a critical enabler for device disaggregation.

Image courtesy of Northrop Grumman Aerospace Systems

COSMOS1

3 um Pitch


1Compound Semiconductor Materials on Silicon

5

Diverse Accessible Heterogeneous Integration (DAHI)foundry for heterogeneous integration

Heterogeneous Integration of a diverse array of devices on a common Si CMOS platform

Goal: To establish a versatile platform of heterogeneous integration that enables pervasive impact on DoD systems

GaN HEMTs

InP HBTs

AdvancedSi CMOS

Si substrate

65 nm IBM CMOS Wafer

InP HBT Chiplets

GaN HEMT Chiplets

(first three-technology integration demonstrated in Jan 2015)Image courtesy of Northrop Grumman Aerospace Systems

Heterogeneous technology integration in accessible foundry


Image courtesy of University of California, Santa Barbara

Image courtesy of HRL Laboratories

Image courtesy of Globalfoundries

Artist’s Concept

6

DAHI MPW0 CMOS + InP HBT + GaN HEMT demonstration

65 nm IBM CMOS Wafer

InP HBT Chiplets

GaN HEMT Chiplets

(3 technology integration demonstrated in Jan 2015)Image courtesy of Northrop Grumman Aerospace Systems

Successful integration of high performance III-V technologies with CMOS

Team 1

Team 1

Team 2

Yield TV

Calibration

Team 3

Team 4

Team 5

Team 6

Team 7

Team 8

Team 9


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DAHI MPW1: Excellent yield, successful initial tests

300mm diameter Si CMOS wafer (45nm node)

Successful testing identified optimal S/H circuit for ADC

(>65dB SFDR @ 2GHz)Frequency (Hz) 10 9

0 1 2 3 4 5 6 7

Rel

ativ

e Am

plitu

de (d

B)

-90

-80

-70

-60

-50

-40

-30

-20

-10

0FCLK_15 GHz, FCW_771_clk_ttune_128_dem_en_0

DAC with very low digital noise

(-70dBc)

0

20

40

60

80

R2C3

M0

R3C4

M0

R4C3

M0

R5C4

M0

R2C3

M0

R3C4

M0

R4C3

M0

R5C4

M0

R2C3

M0

R3C4

M0

R4C3

M0

R5C4

M0

R2C3

M1

R3C4

M1

R4C3

M1

R5C4

M1

R2C3

M0

R3C4

M0

R4C3

M0

R5C4

M0

R2C3

M0

R3C4

M0

R4C3

M0

R5C4

M0

AR_2 AR_2A AR_1 AR_1A AR_1B

HIC Redundancy: None HIC Redundancy: 2x

HBT

Arra

y -B

eta

at 1

mA

Beta_812_@1mA Beta_813_@1mA Beta_814_@1mA Beta_815_@1mA Beta_862_@1mA Beta_863_@1mA Beta_864_@1mA Beta_865_@1mA Beta_872_@1mA Beta_873_@1mA Beta_874_@1mA Beta_875_@1mA

High foundry integration yields; test

vehicles fully functional

99.94% HIC yield98% HBT post-integration

DAHI integration (Dec 2015): Si (45nm), InP (TF5 HBT), GaN (GaN20 HEMT)


Northrop Grumman

BAE Systems Teledyne

GlobalFoundries

Northrop Grumman

8

Standard CMOS fabrication

Standard TF4/TF5InP HBT fabrication Thinning

Mechanical Integration CMOS wafer with integrated

InP and GaN chiplets

CMOS wafer with HICs ready for integration

CMOS wafer with integrated GaN chiplets

High-Q Passives standard process

HIC Interface deposition

Standard GaN20

fabrication

Thinning / backside via

etching

Backside metal

depositionIntegration

Standard T-3 fabrication

Backside metal

deposition

Thinning / backside via

etchingHRL

Singulation and integration

IBM

NGAS

NGAS

Nuvotronics

Integration

Integration approach - disaggregation

MPW0: 65nmMPW1: 45nmMPW2: 45nm

• Obfuscation - Disaggregation of circuit into multiple chiplets conceals total circuit design/performance – circuit design is compartmentalized by technology

• Anti-tamper - Tampering with individual chiplets complicated by lack of knowledge of overall circuit

• Minimizes semiconductor process changeDISTRIBUTION A. Approved for public release: distribution unlimited.

9

Too much of a good thing is wonderful…


10

DAHI process extensions

1. Silicon Carbide Interposera. Better thermal conductivityb. Better thermal expansion

mismatchc. Design/process studies underwayd. Pathfinder lots in process

2. Chiplet Stackinga. Process demonstrations, design

rule development underwayb. RF transition modeling in process

3. COTS CMOS Tile Processinga. Developing handling tools and

preparation processes


Images courtesy of Northrop Grumman

11

Integration: Enabling IP and chiplet re-use

Chiplet process modules designed with IP re-use in mind

GaN VLSI Si

SiGeInP

3 um Pitch

Example interconnect

DAHI-enabled integration technology plus IP re-use ecosystem to speed the design cycle and reduce the access cost

Minimized NRE for rapid system prototyping

• Develop a pre-defined “common” interposer (SiC/Si/Glass) platform

• Populate common platform with library of chiplets of IP/circuit blocks

• Different complex configurations can be formed rapidly with reusable IP blocks/chiplets

Passives

GaAs, MEMS, etc.


Image courtesy of Northrop Grumman

CHIPS will develop the design tools and integration standards required to demonstrate modular electronic systems that can leverage the best of

DoD and commercial designs and technology.

What is CHIPS?

Today – Monolithic Tomorrow – Modular

12

Common Heterogeneous integration and IP reuse Strategies program


Artist’s conceptCourtesy: Intel

What will CHIPS do?

SIGINTCOMM RADAR EW

Custom chiplets Commercial chiplets

CHIPS enables rapid integration of functional blocks at the chiplet level

Adaptive filter

Beam forming

QR Decomp.

SerDes

Beam forming

QR Decomp.

SerDes

Adaptive filter

QR Decomp.


Artist’s conceptVideo not included here

14

Today: PCB

Today: Monolithic

Tomorrow: CHIPS

Cost (NRE) $0.1’s M $5-10 M ~$2 M

Schedule 2 months 21 months 7 months

Modularity Board-level No Die-level

IP Availability COTS universe (packaged ICs)

Process node and vendor constrained

COTS and DoD pre-verified chiplets

Performance Low High High

Heterogeneous Integration

Yes, within COTSuniverse No Yes

CHIPS impact on DoD electronics

CHIPS is projected to reduce IC design to one-third cost and time


Courtesy: Aitech

15

CHIPS metrics (preliminary)


Design Level Digital Interfaces Analog InterfacesParameter Value

IP reuse (%) > 50% public1

IP blocksModular design (%)

> 80% reused 2

IP

Access to IP > 3 sources3of IP

Heterogeneous integration

> 3 technologies4

Parameter ValueData rate (scalable) 5 10 Gbps

Energy efficiency 6 < 5 pJ/bit

Latency 6 ? 5 nsec

Parameter ValueInsertion loss (across full bandwidth)

< 1 dB

Bandwidth ? 50 GHz

CHIPS end state vs. conventional supply chain

CAD tools Pkg / TestDesign SystemsFabricationVerificationIP Blocks Architecture

Com

mer

cial

ChipletsDesign specs

Defense Emerging Distributor

? ?

Commercial

CHIP

SD

oD

16

CHIPS

Trusted sources for critical componentsDISTRIBUTION A. Approved for public release: distribution unlimited.

Mentor Graphics

Cadence

Synopsys

Mentor Graphics

Cadence

Synopsys

Mentor Graphics

Cadence

Synopsys

NorthropRaytheon

LockheedBoeingBAE

NorthropRaytheon

LockheedBoeingBAE

NorthropRaytheon

LockheedBoeingBAE

NorthropRaytheon

LockheedBoeingBAE

NorthropRaytheon

LockheedBoeingBAE

NorthropRaytheon

LockheedBoeingBAENorthrop

Raytheon

LockheedBoeingBAE

NorthropRaytheon

LockheedBoeingBAE

AppleGoogle

MicrosoftSamsung

AppleGoogle

MicrosoftSamsung

BroadcomQualcomm

AppleTIMarvell

BroadcomQualcomm

AppleTIMarvell

SMICTSMC

GlobalFoun.IntelSamsung

ARMGlobal Foundries.

TSMCARM

CadenceImagination

TSMCARM

CadenceImagination

ASE GroupTSMC

Amkor

NovatiNorthrop

US OSAT

IntelTSMC

Global Foundries

IntrinsixJariet

FlexlogixRaytheonNorthrop

HRL

TowerjazzNorthrop

HRLGlobal Foundries

Digi-KeyMouser

Artist’s concept

17

But there’s more to DAHI than just the foundry…


18

DAHI alternate flow: wafer-scale bonding

Comparison to chiplet-based approach:• ~10x reduced pitch more interconnects per unit area (<2μm pitch,

>108/cm2 densities have been realized)• Requires similar area sizes for GaN, InP, and CMOS• Technology is significantly less mature than chiplet-based approach


Images courtesy of Teledyne

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DAHI alternate flow:Wafer bonding of InP and Si CMOS (Teledyne/Tezzaron)

130 nmSi CMOS

wafer

Cu/SiO2wafer bond

interface

250 nmInP HBT wafer

wafer bonding

DISTRIBUTION A. Approved for public release: distribution unlimited.Images courtesy of

Teledyne

20

Concept: trusted fabrication through 3D ICs

• Can a trusted design be produced by integrating two untrusted CMOS chips and a trusted wiring only tier using established 3DIC fabrication techniques?

• TIC program approached this by splitting BEOL from FEOL but exposed difficulties

Problem Statement

Approach

Netlist

3D partitioning and place & route

Untrusted CMOS tier

Untrusted CMOS tier

Trusted 3D wiring tier

Fabrication(TSV insertion not shown)

Ziptronix

Floorplanning Partitioning Placement in CMOS 1

Integrated Verification

*Netlist

Via Placement CMOS1 Route

Wiring only route

CMOS2 P&R

Clock Insertion*

• Put together basic CAD flow• Run designs through this flow• Investigate metrics against technology

node, 3D integration pitch, and complexity of wiring only tier

Exploring trust through combination of untrusted processesDISTRIBUTION A. Approved for public release: distribution unlimited.

Images courtesy of NC State University

21

Future of heterogeneous integration

Access and trust through disaggregationDISTRIBUTION A. Approved for public release: distribution unlimited.

Artist’s concept

www.darpa.mil


TRUST THROUGH FUNCTIONAL DISAGGREGATION

Ken Plaks, DARPA/MTO Program Manager


The DARPA solution is to provide a menu of hardware security options that can be selectively applied based on need

24

SPADE will help to prevent and respond to threats such as the malicious insertion of hardware trojans and reliability failures.


25

The ASIC Dilemma


Source: ITRS “average” ASIC complexity

How do we ensure that the warfighter has access to state-of-the-art electronics?

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Advanced packaging

• Manage complexity• Improve yield• Allow specialization


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Key technical enabler … interconnects


Source: MIT Lincoln Labs

28

ASIC trust solution


Artist’s concepts

Artist’s concept

29

Malicious logic: passive techniques


Source: MIT Lincoln Labs

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Malicious logic: active techniques


Artist’s concept

31

SPADE trust demo for ASICS

Achieve the spirit and intent of trust while meeting warfighter need


Artist’s concept

32

Conclusion

Bring the state-of-the-art back to military electronics


www.darpa.mil


Leveraging THE commercial SECTOR and providing ...• ≤ 5µm HIC length and pitch • ~5 HBTs, 4...

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Transcript of Leveraging THE commercial SECTOR and providing ...• ≤ 5µm HIC length and pitch • ~5 HBTs, 4...