Lecture01!1!2005 Design Abstraction

8/19/2019 Lecture01!1!2005 Design Abstraction

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Lecture 1-1Design Abstraction

Pradondet [email protected]

Department of Computer Engineering

Kasetsart University


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"

Acknowledgement

'his lecture note has (een summari)ed fromlecture note on *ntroduction to +,-* Design!+,-* Circuit Design all over the orld. * can/t

remem(er here those slide come from.0o ever! */d like to thank all professors hocreate such a good ork on those lecturenotes. 1ithout those lectures! this slide can/t(e finished.


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2

The VLSI design process

May (e part of larger product design.Ma3or levels of a(straction4

specification5

architecture5logic design5circuit design5

layout.


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%

Dealing with complexity

Divide6and6con7uer4 limit the num(er ofcomponents you deal ith at any one time.8roup several components into larger

components4transistors form gates5gates form functional units5

functional units form processing elements5etc.


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Hierarchical name

*nterior vie of a component4components and ires that make it up.

E:terior vie of a component ; type4

(ody5pins.

Fulladder

a

bcin

sum

cout


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Instantiating component types

Each instance has its o n name4add


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A hierarchical logic design

z

box1 box2 x


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Net lists and component lists

Net list4net 4 top.in in .innet"4 i .out :::.topin 4 top.n :::.:intopin"4 top.n" :::.:in"(otin 4 top.n2 :::.:in2net24 :::.out i".inoutnet4 i".out top.out

Component list4top4 in ;net n ;topin

n";topin" n2;topineout;outnet

i 4 in;net out;net":::4 :in ;topin

:in";topin" :in2;(otin;net" out;net2

i"4 in;net2 out;outnet


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Component hierarchy

top

i1 xxx i2


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Hierarchical names

'ypical hierarchical name4topBi .foo

component pin


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Layout and its a stractions

,ayout for dynamic latch4


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Stick diagram


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Transistor schematic


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!ixed schematic

inverter


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Le"els o# a straction

-pecification4 function! cost! etc. &rchitecture4 large (locks.,ogic4 gates registers.Circuits4 transistor si)es for speed! po er.,ayout4 determines parasitics.


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Circuit a straction

Continuous voltages and time4


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Digital a straction

Discrete levels! discrete time4


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$egister%trans#er a straction

&(stract components! a(stract data types4

+

+

0010

0001

0100

0011


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Top%down "s& ottom%up design

'op6do n design adds functional detail.Create lo er levels of a(straction from upperlevels.

ottom6up design creates a(stractions fromlo 6level (ehavior.8ood design needs (oth top6do n and(ottom6up efforts.


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Design a stractions

specification

behavior

register-transfer

logic

circuit

la out

!nglish

!xecutable program

"e#uentialmachines

$ogic gates

transistors

rectangles

&hroughput'design time

Function units'cloc c cles

$iterals'logic depth

nanoseconds

microns

function cost


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Design "alidation

Must check at every step that errors haven/t(een introduced6the longer an error remains!the more e:pensive it (ecomes to remove it.

or ard checking4 compare results of less6and more6a(stract stages.

ack annotation4 copy performance num(ers

to earlier stages.


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VLSI Design Cycle


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VLSI Design Cycle '()*+

" stem "pecification

Architectural esign

$ogic esign

*ircuit esign

h sical esign

Functional esign Fabrication

ac aging


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VLSI Design Cycle ',)*+

-ystem -pecification -pecification of thesi)e! speed! po er and functionality of the+,-* system.

&rchitectural Design Decisions on thearchitecture! e.g.! F*-CBC*-C! G of &,U/s!pipeline structure! cache si)e! etc. -uchdecisions can provide an accurate estimationof the system performance! die si)e! po erconsumption! etc.


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VLSI Design Cycle '-)*+

unctional Design *dentify main functionalunits and their interconnections. No details ofimplementation.


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VLSI Design Cycle '.)*+

,ogic Design Design the logic! e.g.!(oolean e:pressions! control flo ! ord

idth! register allocation! etc. 'he outcome is

called an F', < Register Transfer Level =description. F', is e:pressed in a 0D,


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VLSI Design Cycle '/)*+

Circuit Design Design the circuit includinggates! transistors! interconnections! etc. 'heoutcome is called a netlist .


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VLSI Design Cycle '0)*+

Net list4net 4 top.in in .innet"4 i .out :::.topin 4 top.n :::.:in

topin"4 top.n" :::.:in"(otin 4 top.n2 :::.:in2net24 :::.out i".inoutnet4 i".out top.out

Component list4top4 in ;net n ;topin

n";topin" n2;topineout;outnet

i 4 in;net out;net":::4 :in ;topin

:in";topin" :in2;(otin;net" out;net2

i"4 in;net2 out;outnet


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2#


top

i1 xxx i2

Component hierarchy


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Physical Design Convert the netlist into ageometric representation. 'he outcome iscalled a layout .


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VLSI Design Cycle '*)*+

a(rication Process includes lithography!polishing! deposition! diffusion! etc.! toproduce a chip .

Packaging Put together the chips on a PC


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VLSI Design Cycle

" stem "pecification

Architectural

"pecification

&$ in $

3etlist

$a out

&iming 4 relationship

bet5een functional units

*hips

ac aged andtested chips

Architectural Design

Functional Design

Logic Design

Physical Design

Fabrication

Packaging

Circuit Designor

Logic Synthesis


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2%

3hysical Design Cycle '()0+

*ircuit artitioning

Floorplanning 4 lacement

outing

$a out *ompaction

!xtraction and 6erification


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3hysical Design Cycle ',)0+

Circuit Partitioning Partition a large circuitinto su(6circuits


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3hysical Design Cycle '-)0+

loorplanning -et up a plan for a goodlayout. Place the modules


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3hysical Design Cycle '.)0+

Placement E:act placement of themodules


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3hysical Design Cycle '/)0+

Fouting Complete the interconnections(et een modules. actors like critical path!clock ske ! ire spacing! etc.! are

considered. *nclude global routing anddetailed routing .

v

Feedthrough

& pe 1 standard cel1

& pe 2 standard cell


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3hysical Design Cycle '0)0+

Compaction Compress the layout from alldirections to minimi)e the total chip area.

+erification Check the correctness of the

layout. *nclude DFC < Design Rule Chec ing =!circuit e!traction


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Design Styles '(),+

ull6Custom &-*Cs-ome


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Design Styles ',),+

Programma(le &-*Cs &ll logic cells are predesigned andnone of the mask layers are customi)ed'ypes4 P,D


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4ull%custom ASICs '()-+

Engineers design some or all of the logiccells! circuits! or layout specifically for one

&-*Cull6custom *Cs are the most e:pensive

to manufacture and to designManufacturing lead time


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4ull%custom ASICs ',)-+

1hen does it make senseJthere are no suita(le e:isting cell li(raries availa(lee:isting logic cells are not fast enoughlogic cells are not small enoughlogic cells consume too much po er

&-*C is so speciali)ed thatsome circuits must (e custom designed

'rends4 fe er and fe er full6custom *Cs are(eing designed


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%%

4ull Custom Design '-)-+


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Standard%Cell%5ased ASICs '()/+

Cell6 ased &-*C


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Standard%Cell%5ased ASICs',)/+

Characteristicscustom (locks can (e em(edded5

&-*C designer defines only the placement of thestandard cells and the interconnect in a C *C

standard cells can (e placed any here on asilicon ;all mask layers of a C *C are customi)edmanufacturing lead time is ? eeks


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Standard%Cell%5ased ASICs '-)/+

&dvantagesdesigners save time! money! and reduce risks using apredesigned! pretested! and precharacteri)ed standard6cellli(rarystandard cells in the li(rary are constructed using full6custom5each standard cell can (e optimi)ed individually


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Standard%Cell%5ased ASICs'.)/+

-tandard6cells are designedto fit hori)ontally together to form ro s*nternal construction of a cell

- 25 microns w ide (lambda is 0 .25)- AB: abutment box- BB: bounding box- Power supplies: VDD, GND- Each different shaded andlabeled pattern represents adifferent layer- Connections: A1, B1, Z


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Standard%Cell%5ased ASICs '/)/+

Fouting the C *C - Interconnectionsbetween cells u sespaces ( calledchannels) between rows- 2 separate layers o f

metal interconnect(metal1 a nd m etal2)running at right anglesto each other- Feedthrough: refers

either to the piece ofmetal that is used topass a signal through acell or to a space in acell waiting to be used

as a feedthrough


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6ate%Array%5ased ASICs

*n gate6array6(ased &-*Ctransistors are predefined on the silicon afer

ase cell the smallest element that is replicatedase array the predefined pattern of transistors

Masked 8ate &rray


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6ate%Array%5ased ASICs ',).+

Channeled gate arraye leave space (et een the ro s of transistors for iring

Characteristicsonly interconnect is customi)ed

the interconnect uses predefined spaces (et een ro smanufacturing lead time is (et een " days and " eeks


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6ate%Array%5ased ASICs '-).+

Channelless gate array


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6ate%Array%5ased ASICs '.).+

-tructured gate array or em(edded gate arraycom(ines features of C *C and M8&motivation4 M8& has only fi:ed gate6array (ase cell5difficult and inefficient implementation of memory

e set aside some *C area and dedicate it to a specific function


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3rogramma le Logic De"ices'(),+

P,Dsstandard *Cs! availa(le in standard configurationssold in high volume to many different customersP,Ds may (e configured or programmed to create

a part customi)ed to specific applicationCharacteristics

no customi)ed mask layers or logic cellsfast design turnaround

a single large (lock of programma(le interconnecta matri: of logic macrocells that usually consists ofprogramma(le array logic follo ed (y a flip6flop or latch


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4ield%3rogramma le 6ate


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4ield%3rogramma le 6ateArrays '436A+

P8&a step a(ove the P,D in comple:ity5it is usually larger and more comple: than a P,Drapidly gro ing in importance

Characteristics

none of mask layers are customi)eda method for programming (asic cellsand the interconnectthe core is regular arrayof programma(le (asic logic cells


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7conomics o# ASICs

8oaldiscuss the economics of using &-*Cs in a product andcompare the most popular types of &-*Cs4an P8&! an M8&! and a C *C

1arningL costs change rapidly and *C industry is notorious forkeeping its costs! prices! and pricing strategy closelyguarded secrets! so the num(ers e ill use to illustratethe different components of cost are appro:imate

Part costvary enormously4 from a fe dollars to several hundreds

P8&s are more e:pensive per gate than M8&sM8&s are more e:pensive per gate than C *Cs

Lecture01!1!2005 Design Abstraction

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