Lecture Outline VLSI Fundamentals

1

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lec 9: February 14, 2019 MOS Inverter: Static Performance

Penn ESE 570 Spring 2019 – Khanna

Lecture Outline

!  Regeneration !  Saturated nMOS Load Inverter !  CMOS Inverter !  Symmetric CMOS Inverter Design !  Inverter Performance (time permitting)

"  Power

3 Penn ESE 570 Spring 2019 – Khanna

Regeneration Discipline

!  Define legal inputs "  Gate works if Vin “close enough” to the rail

!  Regeneration "  Gate produces Vout “closer to rail”

"  This tolerates some drop between one gate and next (between out and in)

"  Call this our “Noise Margin”

Regeneration/Restoration/Static Discipline


Noise Margin

!  VOH – output high !  VOL – output low

!  VIH – input high !  VIL – input low

!  NMH = VOH-VIH

!  NML = VIL-VOL

“1”

“0”

VOH

VOL

VIL

VIHNMH

NML

Undefined region

Gate Output Stage M

Gate Input Stage M + 1


Regeneration Discipline (getting precise)

!  Define legal inputs "  Gate works if Vin “close

enough” to the rail "  Vin > VIH or Vin < VIL

!  Regeneration "  Gate produces Vout “closer to

rail” "  Vout < VOL or Vout > VOH

“1”

“0”

VOH

VOL

VIL

VIHNMH

NML

Undefined region

Gate Output Stage M

Gate Input Stage M + 1


Decomposing

!  An input closer to respective rail than VIL/VIH doesn’t make much difference on Vout

"  i.e transfer function is flat close to rails

!  Defining VIL lower (VIH higher) would reduce NMs and increase our undefined region

-1

-1

VIL VIH

VOL

VOH

VIL

VIH

NML

NMH

δVoutδVin VIL

=δVoutδVin VIH

= −1

VOH ≈ f (VIL )VOL ≈ f (VIH ) 7 Penn ESE 570 Spring 2019 – Khanna

2

Noise Implications

!  What is the output when all inputs are all 0.95 and NAND(A, B) = 1-A*B?


1 2 3 4 5 6

Transfer Function for Multiple Inputs

Vout = f (Vin1,Vin2 )

?


Controlling Input

!  Consider a nor2 gate "  If want B to control the output "  What value should A be?

!  We call A the non-controlling input since it does not determine the output


Controlling Input



A B NOR

0 0 1

0 1 0

1 0 0

1 1 0 11 Penn ESE 570 Spring 2019 – Khanna

Controlling Input



!  What should the non-controlling input value be for a nand2 gate?

A B NOR

0 0 1

0 1 0

1 0 0

1 1 0

A B NAND

0 0 1

0 1 1

1 0 1

1 1 0 12 Penn ESE 570 Spring 2019 – Khanna

Review: Resistive Load Inverter

13

VSB


3

Review: Summary: Resistive Load Inverter

14 VT0n

VDD

0 VDD Penn ESE 570 Spring 2019 – Khanna

Saturated nMOS-Load Inverter

15

VSB,d VSB,L

VSB,L ≠ 0

Load: IL =

µn ⋅Cox

2WLVDD −Vout −VT 0,n( )2



16

VSB,L ≠ 0

ID = ISWL

!

"#

$

%&e

Vin−VT 0,nnkT /q

!

"#

$

%&

1− e−VoutkT /q!

"#

$

%&!

"

##

$

%

&&

ID =µn ⋅Cox

2WL2 Vin −VT 0,n( )Vout −V 2

out( )

ID =µn ⋅Cox

2WLVin −VT 0,n( )2

Vin =VGS <VT 0,n

Vin =VGS ≥VT 0,n,Vout =VDS ≤Vin −VT 0,n

Vin =VGS ≥VT 0,n,Vout =VDS >Vin −VT 0,n

Subthreshold:

Linear:

Saturation:

Load: IL =

µn ⋅Cox



VSB,d VSB,L


17

VSB,L ≠ 0

ID = ISWL

!

"#

$

%&e

Vin−VT 0,nnkT /q

!

"#

$

%&

1− e−VoutkT /q!

"#

$

%&!

"

##

$

%

&&

ID =µn ⋅Cox

2WL2 Vin −VT 0,n( )Vout −V 2

out( )

ID =µn ⋅Cox

2WLVin −VT 0,n( )2

Vin =VGS <VT 0,n

Vin =VGS ≥VT 0,n,Vout =VDS ≤Vin −VT 0,n

Vin =VGS ≥VT 0,n,Vout =VDS >Vin −VT 0,n

Subthreshold:

Linear:

Saturation:

Load: IL =

µn ⋅Cox


ID = 0


VSB,d VSB,L


18

VSB,L ≠ 0


VSB,d VSB,L


19

VSB,L ≠ 0

µn ⋅Cox

2WL

"

#$

%

&'L

VDD −Vout −VT 0,n( )2 = 0

µn ⋅Cox

2WL

"

#$

%

&'L

VDD −Vout −VT 0,n( )2 = µn ⋅Cox

2WL

"

#$

%

&'D

2 Vin −VT 0,n( )Vout −V 2out( )

µn ⋅Cox

2WL

"

#$

%

&'L

VDD −Vout −VT 0,n( )2 = µn ⋅Cox

2WL

"

#$

%

&'D

Vin −VT 0,n( )2


VSB,d VSB,L

4

CMOS Inverter

20

IDn = IDp

VGSn = Vin

VDSn = Vout

VGSp = Vin - VDD

VDSp = Vout - VDD


CMOS Inverter

21

IDn = IDp

VGSn = Vin

VDSn = Vout

VGSp = Vin - VDD

VDSp = Vout - VDD

Subthreshold: Linear: Saturation:


CMOS Inverter

22

IDn = IDp

VGSn = Vin

VDSn = Vout

VGSp = Vin - VDD

VDSp = Vout - VDD



CMOS Inverter

23

IDn = IDp

VGSn = Vin

VDSn = Vout

VGSp = Vin - VDD

VDSp = Vout - VDD



CMOS Inverter: Visual VTC

24

V DD

-1

-1

V ILV IH

Vin

Vout

VT0n

A

A

-VT0n

LIN

SAT

Vout = Vin - VT0n

OFF

LIN

V th

VOH= V DD

V OL= 0

Vin<VT0n



25

V DD

-1

-1

V ILV IH

Vin

Vout

VT0n VDD+VT0p

A E

A

E

-VT0n

-VT0p

LIN

SAT LIN

SAT

Vout = Vin - VT0n

Vout = Vin - VT0p

LIN &

OFF

LIN &

OFF

V th

VOH= V DD

V OL= 0

Vin<VT0n

Vin>VT0p - VDD


5

26

Kenneth R. Laker, University of

Pennsylvania, updated 12Feb15

V th− VT0p

V th− VT0n

V th

V th V DD

-1

-1

V ILV IH

Vout = Vin - VT0p

Vout = Vin - VT0n

-VT0n



27

V th− VT0p

V th− VT0n

V th

V th V DD

-1

-1

V ILV IH

Vout = Vin - VT0p

Vout = Vin - VT0n

-VT0n



= 0

IDn = IDp = 0

28

V th− VT0p

V th− VT0n

V th

V th V DD

-1

-1

V ILV IH

Vout = Vin - VT0p

Vout = Vin - VT0n

-VT0n

CMOS Inverter: VOL


29

0 =

IDn = IDp = 0

V th− VT0p

V th− VT0n

V th

V th V DD

-1

-1

V ILV IH

Vout = Vin - VT0p

Vout = Vin - VT0n

-VT0n

CMOS Inverter: VOH


CMOS Inverter: VIL

30




CMOS Inverter: VIL

31



IDn = IDp


6

CMOS Inverter: VIL

32



IDn = IDp

k 'n2

WL

!

"#

$

%&n

Vin −VT 0n( )2 =k 'p2

WL

!

"#

$

%&p

2 Vin −VDD −VT 0 p( ) Vout −VDD( )− Vout −VDD( )2()

*+


CMOS Inverter: VIL

33

Set Vin = VIL and dVout/dVin = -1

k 'n2

WL

!

"#

$

%&n

2 Vin −VT 0n( ) =k 'p2

WL

!

"#

$

%&p

2 Vout −VDD( )+ 2 Vin −VDD −VT 0 p( ) dVoutdVin− 2 Vout −VDD( ) dVout

dVin

(

)*

+

,-

k 'n2

WL

!

"#

$

%&n

Vin −VT 0n( )2 =k 'p2

WL

!

"#

$

%&p


*+

k 'nWL

!

"#

$

%&n

VIL −VT 0n( ) = k 'pWL

!

"#

$

%&p

Vout −VDD( )+ VIL −VDD −VT 0 p( )(−1)− Vout −VDD( )(−1)() *+

k 'nWL

!

"#

$

%&n


!

"#

$

%&p

2Vout −VIL +VT 0 p −VDD() *+


CMOS Inverter: VIL

34


k 'n2

WL

!

"#

$

%&n

2 Vin −VT 0n( ) =k 'p2

WL

!

"#

$

%&p


dVin

(

)*

+

,-

k 'n2

WL

!

"#

$

%&n

Vin −VT 0n( )2 =k 'p2

WL

!

"#

$

%&p


*+

k 'nWL

!

"#

$

%&n


!

"#

$

%&p


k 'nWL

!

"#

$

%&n


!

"#

$

%&p


k 'nWL

!

"#

$

%&n

k 'pWL

!

"#

$

%&p

= kR

kR VIL −VT 0n( ) = 2Vout −VIL +VT 0 p −VDD

VIL =2Vout +VT 0 p −VDD + kRVT 0n

1+ kRPenn ESE 570 Spring 2019 – Khanna

CMOS Inverter: VIL

35


k 'n2

WL

!

"#

$

%&n

2 Vin −VT 0n( ) =k 'p2

WL

!

"#

$

%&p


dVin

(

)*

+

,-

k 'n2

WL

!

"#

$

%&n

Vin −VT 0n( )2 =k 'p2

WL

!

"#

$

%&p


*+

k 'nWL

!

"#

$

%&n


!

"#

$

%&p


k 'nWL

!

"#

$

%&n


!

"#

$

%&p


k 'nWL

!

"#

$

%&n

k 'pWL

!

"#

$

%&p

= kR




CMOS Inverter: VIL

36


k 'n2

WL

!

"#

$

%&n

2 Vin −VT 0n( ) =k 'p2

WL

!

"#

$

%&p


dVin

(

)*

+

,-

k 'n2

WL

!

"#

$

%&n

Vin −VT 0n( )2 =k 'p2

WL

!

"#

$

%&p


*+

k 'nWL

!

"#

$

%&n


!

"#

$

%&p


k 'nWL

!

"#

$

%&n


!

"#

$

%&p


k 'nWL

!

"#

$

%&n

k 'pWL

!

"#

$

%&p

= kR



1+ kR

Eq. (1)

Eq. (2)


CMOS Inverter: VIH

37




7

CMOS Inverter: VIH

38



IDn = IDp


CMOS Inverter: VIH

39



IDn = IDp


CMOS Inverter: VIH

40

Set Vin = VIH and dVout/dVin = -1

k 'n2

WL

!

"#

$

%&n

2 Vin −VT 0n( )Vout −Vout2() *+=k 'p2

WL

!

"#

$

%&p

Vin −VDD −VT 0 p( )2

k 'nWL

!

"#

$

%&n

k 'pWL

!

"#

$

%&p

= kR

k 'n2

WL

!

"#

$

%&n

2 Vin −VT 0n( ) dVoutdVin

+ 2Vout − 2VoutdVoutdVin

(

)*

+

,-=

k 'p2

WL

!

"#

$

%&p

2 Vin −VDD −VT 0 p( )

k 'nWL

!

"#

$

%&n

VIH −VT 0n( )(−1)+Vout −Vout (−1)() *+= k 'pWL

!

"#

$

%&p

VIH −VDD −VT 0 p( )

k 'nWL

!

"#

$

%&n

−VIH +VT 0n + 2Vout[ ] = k 'pWL

!

"#

$

%&p


kR −VIH +VT 0n + 2Vout[ ] = VIH −VDD −VT 0 p( )

VIH =VDD +VT 0 p + kR (VT 0n + 2Vout )


CMOS Inverter: VIH

41


k 'n2

WL

!

"#

$

%&n


WL

!

"#

$

%&p


k 'nWL

!

"#

$

%&n

k 'pWL

!

"#

$

%&p

= kR

k 'n2

WL

!

"#

$

%&n



(

)*

+

,-=

k 'p2

WL

!

"#

$

%&p


k 'nWL

!

"#

$

%&n


!

"#

$

%&p


k 'nWL

!

"#

$

%&n


!

"#

$

%&p





CMOS Inverter: VIH

42


k 'n2

WL

!

"#

$

%&n


WL

!

"#

$

%&p


k 'nWL

!

"#

$

%&n

k 'pWL

!

"#

$

%&p

= kR

k 'n2

WL

!

"#

$

%&n



(

)*

+

,-=

k 'p2

WL

!

"#

$

%&p


k 'nWL

!

"#

$

%&n


!

"#

$

%&p


k 'nWL

!

"#

$

%&n


!

"#

$

%&p




1+ kR

Eq. (3)

Eq. (4)


CMOS Inverter: Vth

43




8

CMOS Inverter: Vth

44



IDn = IDp


CMOS Inverter: Vth

45



IDn = IDp


CMOS Inverter: Vth

46



k 'n2

WL

!

"#

$

%&n

Vin −VT 0n( )2 =k 'p2

WL

!

"#

$

%&p


kR Vth −VT 0n( )2 = Vth −VDD −VT 0 p( )22

Vth =VT 0n +

1kR

VDD +VT 0 p( )

1+ 1kR


CMOS Inverter: Vth

47



k 'n2

WL

!

"#

$

%&n

Vin −VT 0n( )2 =k 'p2

WL

!

"#

$

%&p


kR Vth −VT 0n( )2 = Vth −VDD −VT 0 p( )22

Vth =VT 0n +

1kR

VDD +VT 0 p( )

1+ 1kR

Typically, Ln=Lp=Lmin

kR =k 'n W L( )nk 'p W L( )p

=µn W L( )nµp W L( )p

=µnWn

µpWp


48



If, also

ideal Vth

Important design Eq. for CMOS inverter VTC.

CMOS Inverter: Design/Sizing

Vth =VT 0n +

1kR

VDD +VT 0 p( )

1+ 1kR

kR =VDD +VT 0 p −VthVth −VT 0n

"

#$

%

&'

2


49 Kenneth R. Laker,

University of Pennsylvania, updated

12Feb15

If Vth is set to ideal case:

ideal Vth



Vth =VT 0n +

1kR

VDD +VT 0 p( )

1+ 1kR

Vth =12VDD


"

#$

%

&'

2

kR =VDD +VT 0 p −1 2VDD1 2VDD −VT 0n

"

#$

%

&'

2

=1 2VDD +VT 0 p1 2VDD −VT 0n

"

#$

%

&'

2


9

50



If Vth is set to ideal case:

If, also

ideal Vth

k R啇symetric= 1



Vth =VT 0n +

1kR

VDD +VT 0 p( )

1+ 1kR

Vth =12VDD


"

#$

%

&'

2

kR =VDD +VT 0 p −1 2VDD1 2VDD −VT 0n

"

#$

%

&'

2

=1 2VDD +VT 0 p1 2VDD −VT 0n

"

#$

%

&'

2

If VT0n= -VT0p= VT0 (symmetric CMOS)

kR =1 2VDD −VT 01 2VDD −VT 0

⎛

⎝⎜⎜

⎞

⎠⎟⎟

2

=1 1= µnWn

µpWp

⇒Wp

Wn

=µn

µp




12Feb15

Switching Threshold Voltage


Symmetric CMOS Inverter: VIL

52

Eq.(1)

Symmetric CMOS inverter: Vth = VDD/2, VT0n = - VT0p = VT0 and kR = 1

Eq.(2)

k 'n2

WL

!

"#

$

%&n

Vin −VT 0n( )2 =k 'p2

WL

!

"#

$

%&p


*+


1+ kRVIL =

2Vout −VDD2

=Vout −12VDD



53

Eq.(1)


Eq.(2)

Substitute into Eq.(1), i.e. , Vin = VIL and Sym-Inv Cond.

k 'n2

WL

!

"#

$

%&n

Vin −VT 0n( )2 =k 'p2

WL

!

"#

$

%&p


*+


1+ kRVIL =

2Vout −VDD2

=Vout −12VDD

VIL +12VDD =Vout

VIL −VT 0( )2 = 2 VIL −VDD +VT 0( ) VIL +12VDD −VDD

"

#$

%

&'− VIL +

12VDD −VDD

"

#$

%

&'2(

)**

+

,--

⇒VIL =18(3VDD + 2VT 0 )



54

Eq.(1)


Eq.(2)

Substitute into Eq.(1), i.e. , Vin = VIL and Sym-Inv Cond.

k 'n2

WL

!

"#

$

%&n

Vin −VT 0n( )2 =k 'p2

WL

!

"#

$

%&p


*+


1+ kRVIL =

2Vout −VDD2

=Vout −12VDD

VIL +12VDD =Vout


"

#$

%

&'− VIL +

12VDD −VDD

"

#$

%

&'2(

)**

+

,--

⇒VIL =18(3VDD + 2VT 0 )


"

#$

%

&'− VIL +

12VDD −VDD

"

#$

%

&'2(

)**

+

,--

VIL2 − 2VILVT 0 +VT 0

2 = 2 VIL −VDD +VT 0( ) VIL −12VDD

"

#$

%

&'− VIL −

12VDD

"

#$

%

&'2(

)**

+

,--


2 = VIL −VDD +VT 0( ) 2VIL −VDD( )− V 2IL −VILVDD +

14V 2

DD"

#$

%

&'

(

)*

+

,-


2 = 2VIL2 − 2VILVDD + 2VILVT 0 −VILVDD +V

2DD −VT 0VDD −V

2IL +VILVDD −

14V 2

DD(

)*+

,-


2 =VIL2 − 2VILVDD + 2VILVT 0 +

34V 2

DD −VT 0VDD

2VILVDD − 4VILVT 0 =34V 2

DD −VT 0VDD −VT 02

VIL (2VDD − 4VT 0 ) =34V 2


VIL =

34V 2


2VDD − 4VT 0=18(3VDD + 2VT 0 )(VDD − 2VT 0 )

VDD − 2VT 0

VIL =18(3VDD + 2VT 0 )


Symmetric CMOS Inverter


55

VIL =18(3VDD + 2VT 0 )

VIH =18(5VDD − 2VT 0 )

FROM Eq. (1) and Eq. (2)


10

Symmetric CMOS Inverter


56

VIL =18(3VDD + 2VT 0 )

VIH =18(5VDD − 2VT 0 )



NML =VIL −VOL =VIL −0 = 18

(3VDD + 2VT 0 )

NMH =VOH −VIH =VDD −18

(5VDD − 2VT 0 ) = 18

(3VDD + 2VT 0 )

Example:

!  Compute the noise margins for a symmetric CMOS inverter that has been designed to achieve Vth = VDD/2, where VDD = 5 V and VT0n = - VT0p = 1 V.




12Feb15 Example:





12Feb15

NML =18(3VDD + 2VT 0 )

NMH =18(3VDD + 2VT 0 )

NML = NMH = 2.125

Example:





12Feb15

NML =18(3VDD + 2VT 0 )

NMH =18(3VDD + 2VT 0 )

NML = NMH = 2.125

NMH = NML = 2.5 V > VDD/2

RECALL (with VDD = 5 V) 1.

2.

1.

Ideal NM =>

1. NMH, NML > VDD/4 = 1.25 V Preferred NM =>

Performance: Inverter Power


Power

!  P = I×V

!  Tricky part: "  Understanding I "  (pairing with correct V)


11

Operating Modes

!  Steady-State: What modes are the transistors in? "  Vin=Vdd

"  Vin=Gnd

!  What current flows in steady state?


Operating Modes

!  Steady-State: Vin=Vdd

"  PMOS: subthreshold "  NMOS: linear


Operating Modes



64

€

IDSp = −IS#WL

$

% &

'

( ) e

−VGS −VTnkT / q

$

% &

'

( )

1− eVDSkT / q$

% &

'

( )

$

% & &

'

( ) ) 1− λVDS( )

IDSn = µnCOXWL

!

"#

$

%& VGS −VT( )VDS −

VDS2

2(

)*

+

,-


Operating Modes



65

€

IDSp = −IS#WL

$

% &

'

( ) e

−VGS −VTnkT / q

$

% &

'

( )

1− eVDSkT / q$

% &

'

( )

$

% & &

'

( ) ) 1− λVDS( )

IDSn = µnCOXWL

!

"#

$


VDS2

2(

)*

+

,-

Which current determines Istatic ?


Operating Modes



66

€

IDSp = −IS#WL

$

% &

'

( ) e

−VGS −VTnkT / q

$

% &

'

( )

1− eVDSkT / q$

% &

'

( )

$

% & &

'

( ) ) 1− λVDS( )

IDSn = µnCOXWL

!

"#

$


VDS2

2(

)*

+

,-

Which current determines Istatic ?


Static Power

!  P = Istatic×V !  What V should we use?

"  Where is the static current flowing?


12

Switching Currents

!  Dynamic current flow:

!  If both transistor on: "  Current path from Vdd

to Gnd "  Short circuit current


Currents Summary

!  I changes over time !  At least two components

"  Istatic – no switching "  Iswitch – when switching

"  Idyn and Isc


Currents Summary

!  I changes over time !  At least two components

"  Istatic – no switching "  Iswitch – when switching

"  Idyn and Isc

70

VRAMP

CLK

φ

ramp_enable


Switching

Dynamic Power

71 Penn ESE 570 Spring 2019 - Khanna

Switching Currents

!  Itotal(t) = Istatic(t)+Iswitch(t)

!  Iswitch(t) = Isc(t) + Idyn(t)

72

Isc

Istatic

Idyn

Penn ESE 570 Spring 2019 - Khanna

Charging

!  Idyn(t) – why is it changing? "  Ids = f(Vds,Vgs) "  and Vgs, Vds changing

73

€

IDS = µnCOXWL

"

# $

%

& ' VGS −VT( )VDS −

VDS2

2)

* +

,

- .

€

IDS ≈νsatCOXW VGS −VT −VDSAT

2%

& '

(

) *


13

Switching Energy – focus on Idyn(t)


Isc

Istatic

Idyn

Switching Energy – focus on Idyn(t)

E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫

75

Idyn


Switching Energy

76

!  Do we know what this is?

Idyn

Idyn (t)dt∫



Switching Energy

77


Idyn

Q = Idyn (t)dt∫



Switching Energy

78


!  What is Q? Idyn

Q = Idyn (t)dt∫



Switching Energy

79



Q = Idyn (t)dt∫


€

Q = CV = I(t)dt∫


14

Switching Energy

80



Q = Idyn (t)dt∫


€

Q = CV = I(t)dt∫

€

E = CVdd2

Capacitor charging energy


Switching Power

!  Every time output switches 0#1 pay: "  E = CV2

!  Pdyn = (# 0#1 trans) × CV2 / time

!  # 0#1 trans = ½ # of transitions

!  Pdyn = (# trans) × ½CV2 / time


Switching


Short Circuit Power

Short Circuit Power

!  Between VTN and Vdd - VTP

"  Both N and P devices conducting


Short Circuit Power

!  Between VTN and Vdd - VTP

"  Both N and P devices conducting

!  Roughly:

84

Isc


Vin

time

Vout

Isdp

time

time

time

Vthn

Vdd

Vdd

Vdd-Vthp

Isc

tsc tsc

Peak Current

!  Ipeak around Vdd/2 "  If |VTN|=|VTP| and sized equal rise/fall

85

€


2%

& '

(

) *


Vin

time

Vout

Isdp

time

time

time

Vthn

Vdd

Vdd

Vdd-Vthp

Isc

tsc tsc

15

Peak Current


86

€


2%

& '

(

) *

€

I(t)dt∫ ≈ Ipeak × tsc ×12%

& ' (

) *


Vin

time

Vout

Isdp

time

time

time

Vthn

Vdd

Vdd

Vdd-Vthp

Isc

tsc tsc

Vin

time

Vout

Isdp

time

time

time

Vthn

Vdd

Vdd

Vdd-Vthp

Isc

tsc tsc

Peak Current


87

€


2%

& '

(

) *

€

I(t)dt∫ ≈ Ipeak × tsc ×12%

& ' (

) *

€

E =Vdd × Ipeak × tsc ×12#

$ % &

' (


Short Circuit Energy

!  Make it look like a capacitance, CSC

"  Q=I×t "  Q=CV

88

E =Vdd × I peak × tsc ×12"

#$%

&'

"

#$

%

&'

E =Vdd ×QSC

E =Vdd × (CSCVdd ) =CSCV2dd


CSC =I peaktsc2Vdd

Short Circuit Energy

!  Every time switch (0#1 and 1#0) "  Also dissipate short-circuit energy: E = CV2

"  Different C = Csc

"  Ccs “fake” capacitance (for accounting)


Idea

!  Design Symmetric Inverters for symmetric and large noise margins for robust design "  kR=1

!  Ptot = Pstatic + Pdyn+ Psc

Penn ESE 570 Spring 2019 - Khanna 90

Admin

!  HW 4 due Friday, 2/15 (tomorrow) !  HW 5 posted over the weekend, due in two weeks

!  Quiz 1 next week Thursday "  First 15 minutes of class "  Starts at 1:30pm exactly "  Closed book "  Covers lecture 1-9 (today)


Lecture Outline VLSI Fundamentals

Documents

Transcript of Lecture Outline VLSI Fundamentals