Lecture Notes in Electrical Engineering

Volume 623

Series Editors

Leopoldo Angrisani, Department of Electrical and Information Technologies Engineering, University of NapoliFederico II, Naples, ItalyMarco Arteaga, Departament de Control y Robótica, Universidad Nacional Autónoma de México, Coyoacán,MexicoBijaya Ketan Panigrahi, Electrical Engineering, Indian Institute of Technology Delhi, New Delhi, Delhi, IndiaSamarjit Chakraborty, Fakultät für Elektrotechnik und Informationstechnik, TU München, Munich, GermanyJiming Chen, Zhejiang University, Hangzhou, Zhejiang, ChinaShanben Chen, Materials Science and Engineering, Shanghai Jiao Tong University, Shanghai, ChinaTan Kay Chen, Department of Electrical and Computer Engineering, National University of Singapore,Singapore, SingaporeRüdiger Dillmann, Humanoids and Intelligent Systems Laboratory, Karlsruhe Institute for Technology,Karlsruhe, GermanyHaibin Duan, Beijing University of Aeronautics and Astronautics, Beijing, ChinaGianluigi Ferrari, Università di Parma, Parma, ItalyManuel Ferre, Centre for Automation and Robotics CAR (UPM-CSIC), Universidad Politécnica de Madrid,Madrid, SpainSandra Hirche, Department of Electrical Engineering and Information Science, Technische UniversitätMünchen, Munich, GermanyFaryar Jabbari, Department of Mechanical and Aerospace Engineering, University of California, Irvine, CA,USALimin Jia, State Key Laboratory of Rail Traffic Control and Safety, Beijing Jiaotong University, Beijing, ChinaJanusz Kacprzyk, Systems Research Institute, Polish Academy of Sciences, Warsaw, PolandAlaa Khamis, German University in Egypt El Tagamoa El Khames, New Cairo City, EgyptTorsten Kroeger, Stanford University, Stanford, CA, USAQilian Liang, Department of Electrical Engineering, University of Texas at Arlington, Arlington, TX, USAFerran Martin, Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, Bellaterra,Barcelona, SpainTan Cher Ming, College of Engineering, Nanyang Technological University, Singapore, SingaporeWolfgang Minker, Institute of Information Technology, University of Ulm, Ulm, GermanyPradeep Misra, Department of Electrical Engineering, Wright State University, Dayton, OH, USASebastian Möller, Quality and Usability Laboratory, TU Berlin, Berlin, GermanySubhas Mukhopadhyay, School of Engineering & Advanced Technology, Massey University,Palmerston North, Manawatu-Wanganui, New ZealandCun-Zheng Ning, Electrical Engineering, Arizona State University, Tempe, AZ, USAToyoaki Nishida, Graduate School of Informatics, Kyoto University, Kyoto, JapanFederica Pascucci, Dipartimento di Ingegneria, Università degli Studi “Roma Tre”, Rome, ItalyYong Qin, State Key Laboratory of Rail Traffic Control and Safety, Beijing Jiaotong University, Beijing, ChinaGan Woon Seng, School of Electrical & Electronic Engineering, Nanyang Technological University,Singapore, SingaporeJoachim Speidel, Institute of Telecommunications, Universität Stuttgart, Stuttgart, GermanyGermano Veiga, Campus da FEUP, INESC Porto, Porto, PortugalHaitao Wu, Academy of Opto-electronics, Chinese Academy of Sciences, Beijing, ChinaJunjie James Zhang, Charlotte, NC, USA

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Dhanasekharan Natarajan

Fundamentals of DigitalElectronics

123

Dhanasekharan NatarajanBengaluru, India

ISSN 1876-1100 ISSN 1876-1119 (electronic)Lecture Notes in Electrical EngineeringISBN 978-3-030-36195-2 ISBN 978-3-030-36196-9 (eBook)https://doi.org/10.1007/978-3-030-36196-9

© Springer Nature Switzerland AG 2020This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or partof the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations,recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmissionor information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilarmethodology now known or hereafter developed.The use of general descriptive names, registered names, trademarks, service marks, etc. in thispublication does not imply, even in the absence of a specific statement, that such names are exempt fromthe relevant protective laws and regulations and therefore free for general use.The publisher, the authors and the editors are safe to assume that the advice and information in thisbook are believed to be true and accurate at the date of publication. Neither the publisher nor theauthors or the editors give a warranty, expressed or implied, with respect to the material containedherein or for any errors or omissions that may have been made. The publisher remains neutral with regardto jurisdictional claims in published maps and institutional affiliations.

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Dedicated to OM SHAKTHI

Preface

Electrical signals are processed for controls, monitoring, transmission, and otherrequirements. The signals could be processed by analog or digital circuits. Digitalsignal processing (DSP) has distinct advantages over analog signal processing.Higher accuracy in controls, reduced noise in transmission and encryption are someof the advantages. DSP is highly popular in consumer, industrial, military and otherapplications. Understanding digital electronics is necessary to design logic circuitsfor digital signal processing.

This book presents the fundamentals of digital electronics for students to becomeDSP engineers. Most of the topics of digital electronics are presented in tutorialform for self-learning with high clarity. Digital signal processing (DSP) applicationinformation is provided for many topics of the subject to appreciate the practicalsignificance of learning. Strong references are provided for additional learning. Thepresentation of the book is also structured for comfortable teaching for teachers.

Chapter 1 presents the overview of digital signal processing. Combinationallogic circuits and related information are explained in Chaps. 2–6. Logic gates,logic minimization methods, digital hardware, hazards, binary number systems,binary codes, bit error detection, arithmetic operations, and arithmetic circuits arepresented in the chapters.

Clock signal network and timing signals are used in computers and digital signalprocessing systems for controlling and performing their intended functions. Theyare explained in Chap. 7. Sequential logic elements (latches and flip-flops) andcircuits (registers and counters) are presented in Chaps. 8–10.

Signal conversion architectures (ADC and DAC) are explained in Chap. 11.Simple programmable logic devices (SPLDs), complex programmable logic devices(CPLDs), and field programmable gate arrays (FPGAs) are presented in Chap. 12.The design of sequential logic circuits using Moore and Mealy machines is illus-trated with examples in Chap. 13. The technologies and general application relia-bility information of digital ICs are presented in Chap. 14.

Bengaluru, India Dhanasekharan Natarajan

vii

Acknowledgements

Throughout my career, I was assisted by a team of committed and talented engi-neers and technicians with a lot of enthusiasm and initiatives. I would like to thankthe team first for making me a better professional with time. I thank my wife,Rameswari, also for encouraging me to engage in writing books after myretirement.

Most importantly, I wish to express my sincere thanks to Prof. B. I. Khodanpur,HOD (CSE, Retired) of R V College of Engineering, one of the premier institutionsin Bangalore. He provided me the opportunity to teach digital electronics toundergraduate students. I would also like to acknowledge the collaborative supportfrom my colleagues at RVCE in teaching the subject.

ix

Contents

1 Overview of Digital Signal Processing . . . . . . . . . . . . . . . . . . . . . . . 11.1 Types of Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1.1 Analog Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.2 Digital Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Basic Characteristics of Digital Signal . . . . . . . . . . . . . . . . . . . 31.2.1 Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2.2 Period, Frequency and Duty Cycle . . . . . . . . . . . . . . . 41.2.3 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 Analog Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.4 Digital Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4.1 Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.4.2 Digital SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.4.3 Digital Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.5 Simplifying Logic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . 81.5.1 Basic Logical Operators . . . . . . . . . . . . . . . . . . . . . . . 81.5.2 Boolean Algebra . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.5.3 De Morgan Laws . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101.5.4 Shannon Theorems . . . . . . . . . . . . . . . . . . . . . . . . . . . 101.5.5 Simplification of Logic Functions . . . . . . . . . . . . . . . . 10

1.6 Hardware Description Language . . . . . . . . . . . . . . . . . . . . . . . 11References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2 Basic Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2.1 OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2.2 AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.2.3 NOT Gate (Inverter) . . . . . . . . . . . . . . . . . . . . . . . . . . 162.2.4 Active High and Active Low Input Signals . . . . . . . . . 17

xi

2.3 Universal Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.3.1 NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.3.2 NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4 General Purpose Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . 212.4.1 AND-OR-INVERT Gate . . . . . . . . . . . . . . . . . . . . . . . 222.4.2 Expandable AND-OR-INVERT Gate . . . . . . . . . . . . . . 222.4.3 XOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.4.4 XNOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3 Combinational Logic Minimization . . . . . . . . . . . . . . . . . . . . . . . . . 293.1 Overview of Combinational Logic Design . . . . . . . . . . . . . . . . 29

3.1.1 General Design Approach . . . . . . . . . . . . . . . . . . . . . . 303.2 Logic Function in SOP Form . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2.1 Minterm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.2.2 Obtaining Logic Function . . . . . . . . . . . . . . . . . . . . . . 32

3.3 Logic Function in POS Form . . . . . . . . . . . . . . . . . . . . . . . . . 333.3.1 Maxterm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.3.2 Obtaining Logic Function . . . . . . . . . . . . . . . . . . . . . . 34

3.4 Algebraic Method for Logic Simplification . . . . . . . . . . . . . . . . 353.4.1 Simplifying Logic Function in SOP Form . . . . . . . . . . 353.4.2 Simplifying Logic Function in POS Form . . . . . . . . . . 363.4.3 Transformation Between SOP and POS Forms . . . . . . . 37

3.5 Karnaugh Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.5.1 K-map with Two Variables . . . . . . . . . . . . . . . . . . . . . 373.5.2 K-map with Three Variables . . . . . . . . . . . . . . . . . . . . 403.5.3 K-map with Four Variables . . . . . . . . . . . . . . . . . . . . . 423.5.4 Variable-Entered K-map . . . . . . . . . . . . . . . . . . . . . . . 433.5.5 Don’t-Care Conditions . . . . . . . . . . . . . . . . . . . . . . . . 493.5.6 Logic Function in POS Form . . . . . . . . . . . . . . . . . . . 50

3.6 Quine-McCluskey Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513.6.1 Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . 523.6.2 Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.7 Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573.7.1 Causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573.7.2 Types of Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593.7.3 Avoiding Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4 Combinational Logic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654.2 Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.2.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664.2.2 Implementing 3-Variable Truth Table

Using 8:1 MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

xii Contents

4.2.3 Implementing 4-Variable Truth TableUsing 8:1 MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.2.4 Direct Implementation of Logic Function . . . . . . . . . . . 714.2.5 Cascading Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . 72

4.3 Demultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754.3.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754.3.2 Cascading Demultiplexers . . . . . . . . . . . . . . . . . . . . . . 77

4.4 Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784.4.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784.4.2 Demultiplexers as Decoders . . . . . . . . . . . . . . . . . . . . 794.4.3 Applications of Decoders . . . . . . . . . . . . . . . . . . . . . . 804.4.4 Implementing Logic Functions . . . . . . . . . . . . . . . . . . 804.4.5 BCD to Decimal Decoder/Driver . . . . . . . . . . . . . . . . . 814.4.6 BCD to 7-Segment Decoder/Driver . . . . . . . . . . . . . . . 82

4.5 Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854.5.1 Decimal-to-BCD Encoder . . . . . . . . . . . . . . . . . . . . . . 864.5.2 Priority Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.6 Magnitude Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894.6.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894.6.2 Logic Function for 1-Bit Comparator . . . . . . . . . . . . . . 904.6.3 Logic Function for 2-Bit Comparator . . . . . . . . . . . . . . 904.6.4 Cascading Magnitude Comparators . . . . . . . . . . . . . . . 92

Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5 Number Systems and Binary Codes . . . . . . . . . . . . . . . . . . . . . . . . 955.1 Types of Number Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . 955.2 Decimal Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955.3 Binary Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

5.3.1 Decimal-Binary Conversion . . . . . . . . . . . . . . . . . . . . 965.3.2 Binary-Decimal Conversion . . . . . . . . . . . . . . . . . . . . 985.3.3 Binary Coded Decimal . . . . . . . . . . . . . . . . . . . . . . . . 995.3.4 Excess-3 Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

5.4 Octal Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025.4.1 Octal-Binary Conversion . . . . . . . . . . . . . . . . . . . . . . . 1025.4.2 Binary-Octal Conversion . . . . . . . . . . . . . . . . . . . . . . . 1035.4.3 Octal-Decimal Conversion . . . . . . . . . . . . . . . . . . . . . 1035.4.4 Decimal-Octal Conversion . . . . . . . . . . . . . . . . . . . . . 104

5.5 Hexadecimal Number System . . . . . . . . . . . . . . . . . . . . . . . . . 1045.5.1 Hexadecimal-Binary Conversion . . . . . . . . . . . . . . . . . 1055.5.2 Binary-Hexadecimal Conversion . . . . . . . . . . . . . . . . . 1065.5.3 Hexadecimal-Decimal Conversion . . . . . . . . . . . . . . . . 106

Contents xiii

5.5.4 Decimal-Hexadecimal Conversion . . . . . . . . . . . . . . . . 1065.5.5 Hexadecimal-Octal Conversion . . . . . . . . . . . . . . . . . . 1075.5.6 Octal-Hexadecimal Conversion . . . . . . . . . . . . . . . . . . 108

5.6 Binary Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085.6.1 Unipolar Straight Binary . . . . . . . . . . . . . . . . . . . . . . . 1095.6.2 Unipolar Gray Code . . . . . . . . . . . . . . . . . . . . . . . . . . 1095.6.3 Bipolar Offset Binary . . . . . . . . . . . . . . . . . . . . . . . . . 1105.6.4 Bipolar Binary Two’s Complement . . . . . . . . . . . . . . . 110

5.7 Alphanumeric Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115.7.1 ASCII and EBCDIC Schemes . . . . . . . . . . . . . . . . . . . 1125.7.2 Unicode Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5.8 Bit Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135.8.1 Types of Random Bit Errors . . . . . . . . . . . . . . . . . . . . 1135.8.2 Error Detection Methods . . . . . . . . . . . . . . . . . . . . . . . 1145.8.3 Single Bit Parity Check . . . . . . . . . . . . . . . . . . . . . . . 1155.8.4 Two Dimensional Parity Check . . . . . . . . . . . . . . . . . . 1175.8.5 Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185.8.6 Cyclic Redundancy Check . . . . . . . . . . . . . . . . . . . . . 119

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

6 Arithmetic Operations and Circuits . . . . . . . . . . . . . . . . . . . . . . . . 1216.1 Binary Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . 1216.2 Binary Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

6.2.1 Addition of 4-Bit Binary Numbers . . . . . . . . . . . . . . . 1226.2.2 Half Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236.2.3 Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246.2.4 Parallel Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256.2.5 Fast Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266.2.6 Cascading Fast Adders . . . . . . . . . . . . . . . . . . . . . . . . 128

6.3 Binary Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296.3.1 Rules for Binary Subtraction . . . . . . . . . . . . . . . . . . . . 1296.3.2 Coding Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306.3.3 Signed Magnitude . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306.3.4 One’s Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . 1316.3.5 Two’s Complement . . . . . . . . . . . . . . . . . . . . . . . . . . 132

6.4 Arithmetic Operations with Two’s Complement Codes . . . . . . . 1346.4.1 Illustrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346.4.2 Parallel Adder for Addition and Subtraction . . . . . . . . . 1356.4.3 Overflow Detection and Correction . . . . . . . . . . . . . . . 136

6.5 Binary Multiplication and Division . . . . . . . . . . . . . . . . . . . . . 1386.5.1 Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396.5.2 Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

xiv Contents

7 Clock and Timing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

7.1.1 Clock Signal Network . . . . . . . . . . . . . . . . . . . . . . . . 1417.2 Quality Requirements of Clock Signals . . . . . . . . . . . . . . . . . . 142

7.2.1 Clock Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1427.3 Generating Clock and Timing Signals . . . . . . . . . . . . . . . . . . . 143

7.3.1 Reference Crystal Oscillator . . . . . . . . . . . . . . . . . . . . 1447.3.2 Clock Generator Using Standard Gates . . . . . . . . . . . . 144

7.4 Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457.4.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457.4.2 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

7.5 Timer IC, 555 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1467.5.1 Astable Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477.5.2 Monostable Operation . . . . . . . . . . . . . . . . . . . . . . . . . 148

7.6 Monostable Multivibrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507.6.1 Non-retriggerable Monostable Multivibrator . . . . . . . . . 1507.6.2 Retriggerable Monostable Multivibrator . . . . . . . . . . . . 151

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

8 Latches and Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1538.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1538.2 Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

8.2.1 SR Latch with NOR Gates . . . . . . . . . . . . . . . . . . . . . 1548.2.2 S′R′ Latch with NAND Gates . . . . . . . . . . . . . . . . . . . 1558.2.3 SR Latch for Eliminating Contact Bounce Errors . . . . . 1568.2.4 Gated SR Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1578.2.5 D Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

8.3 Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1598.3.1 Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608.3.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1618.3.3 D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1618.3.4 T Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648.3.5 JK Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

8.4 Flip-Flop Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . 1668.4.1 Set-up and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . 167

8.5 Flip-Flops Using Master-Slave Latches . . . . . . . . . . . . . . . . . . 1688.5.1 D Master-Slave Flip-Flop . . . . . . . . . . . . . . . . . . . . . . 168

8.6 State Transition Diagram of Flip-Flop . . . . . . . . . . . . . . . . . . . 169References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

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9.2 Storage Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719.2.1 Simple Storage Register . . . . . . . . . . . . . . . . . . . . . . . 1729.2.2 Standard Storage Register . . . . . . . . . . . . . . . . . . . . . . 172

9.3 Basic Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1749.3.1 Serial-In/Parallel-Out Shift Register . . . . . . . . . . . . . . . 1759.3.2 Parallel-In/Serial-Out Shift Register . . . . . . . . . . . . . . . 1769.3.3 Serial-In/Serial-Out Shift Register . . . . . . . . . . . . . . . . 1789.3.4 Parallel-In/Parallel-Out Shift Register . . . . . . . . . . . . . 179

9.4 Applications of Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . 1819.4.1 Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1819.4.2 Johnson Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1839.4.3 Linear Feedback Shift Register . . . . . . . . . . . . . . . . . . 1859.4.4 Serial Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

9.5 Universal Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1949.5.1 Mode Select Function . . . . . . . . . . . . . . . . . . . . . . . . . 195

Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

10 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19710.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

10.1.1 Understanding Counters . . . . . . . . . . . . . . . . . . . . . . . 19710.2 Asynchronous Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

10.2.1 Binary Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . 19910.2.2 BCD Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . 200

10.3 Synchronous Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20210.3.1 Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20210.3.2 BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20410.3.3 Up-Down Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

10.4 Decoding Counter States and Glitches . . . . . . . . . . . . . . . . . . . 20910.4.1 Decoder for Synchronous Counters . . . . . . . . . . . . . . . 21010.4.2 Decoder for Asynchronous Counters . . . . . . . . . . . . . . 211

10.5 Cascading Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21110.5.1 Terminal Count for Cascading . . . . . . . . . . . . . . . . . . 21210.5.2 Cascading Standard IC Counters . . . . . . . . . . . . . . . . . 214

10.6 Digital Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21610.6.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

10.7 Design of Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21910.7.1 Mod-6 Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . 21910.7.2 Mod-6 Gray Code Counter . . . . . . . . . . . . . . . . . . . . . 222

Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

11 Signal Converter Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22511.1 Overview of Signal Conversion . . . . . . . . . . . . . . . . . . . . . . . . 225

11.1.1 Pre-processing and Post-processing . . . . . . . . . . . . . . . 22511.1.2 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

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11.1.3 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22811.1.4 Standard ICs for ADCs and DACs . . . . . . . . . . . . . . . 228

11.2 Analog Components for Signal Conversion . . . . . . . . . . . . . . . 22811.2.1 Sample-Hold Amplifier . . . . . . . . . . . . . . . . . . . . . . . . 22811.2.2 Anti-aliasing Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 23111.2.3 Reconstruction Filter . . . . . . . . . . . . . . . . . . . . . . . . . 23211.2.4 Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 232

11.3 ADC Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23511.3.1 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23511.3.2 Successive Approximation ADC . . . . . . . . . . . . . . . . . 23711.3.3 Dual Slope ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23911.3.4 Sigma-Delta ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

11.4 DAC Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24411.4.1 Binary-Weighted Input DAC . . . . . . . . . . . . . . . . . . . . 24511.4.2 R-2R Ladder DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

12 Programmable Logic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24912.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24912.2 Logic Devices Programmed by Manufacturers . . . . . . . . . . . . . 250

12.2.1 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25012.2.2 Mask ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25012.2.3 Applications of ROM . . . . . . . . . . . . . . . . . . . . . . . . . 251

12.3 Simple Programmable Logic Devices . . . . . . . . . . . . . . . . . . . . 25412.3.1 Programmable Read-Only Memory . . . . . . . . . . . . . . . 25412.3.2 Programmable Logic Array . . . . . . . . . . . . . . . . . . . . . 25712.3.3 Programmable Array Logic . . . . . . . . . . . . . . . . . . . . . 25812.3.4 Generic Array Logic . . . . . . . . . . . . . . . . . . . . . . . . . . 260

12.4 Complex Programmable Logic Device . . . . . . . . . . . . . . . . . . . 26112.4.1 Basic Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

12.5 Field Programmable Gate Array . . . . . . . . . . . . . . . . . . . . . . . . 26212.5.1 General Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 263

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

13 Design of Sequential Logic Circuits . . . . . . . . . . . . . . . . . . . . . . . . 26713.1 FSM Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

13.1.1 General Models of Moore and Mealy Machines . . . . . . 26713.1.2 Designing Sequential Logic Circuits . . . . . . . . . . . . . . 268

13.2 Sequence Detector Using Moore Machine . . . . . . . . . . . . . . . . 26913.2.1 State Transition Diagram . . . . . . . . . . . . . . . . . . . . . . 26913.2.2 Next State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27113.2.3 Number of Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . 27113.2.4 Encoding of States . . . . . . . . . . . . . . . . . . . . . . . . . . . 27113.2.5 Final State Table with Binary Encoding . . . . . . . . . . . . 272

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13.2.6 Logic Functions with Binary Encoding . . . . . . . . . . . . 27313.2.7 Sequential Logic Circuit with Binary Encoding . . . . . . 27313.2.8 Sequential Logic Circuit with Gray

Code Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27413.3 Sequence Detector Using Mealy Machine . . . . . . . . . . . . . . . . 275

13.3.1 State Transition Diagram . . . . . . . . . . . . . . . . . . . . . . 27613.3.2 Next State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27613.3.3 Sequential Logic Circuit with Binary Encoding . . . . . . 27713.3.4 Sequential Logic Circuit with Gray

Code Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27813.4 Algorithmic State Machine Chart . . . . . . . . . . . . . . . . . . . . . . . 27913.5 State Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

13.5.1 Row Elimination Method . . . . . . . . . . . . . . . . . . . . . . 28113.5.2 Implication Table Method . . . . . . . . . . . . . . . . . . . . . . 282

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

14 Technologies and General Parameters of ICs . . . . . . . . . . . . . . . . . 28714.1 Logic Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

14.1.1 TTL Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28714.1.2 CMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 28814.1.3 BiCMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . 289

14.2 Generic Application Requirements . . . . . . . . . . . . . . . . . . . . . . 28914.2.1 Logic Switching Voltage Levels . . . . . . . . . . . . . . . . . 29014.2.2 Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29114.2.3 Fan-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29214.2.4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . 29314.2.5 ESD Requirements for CMOS Devices . . . . . . . . . . . . 293

14.3 Logic Pulser and Probe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

Appendix: Erasable PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

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About the Author

Dhanasekharan Natarajan, Electronics Engineer from College of Engineering,Guindy (presently Anna University), Chennai in 1970, obtained his post-graduatein Engineering Production (Q&R Option) from the University of Birmingham, UK,in 1984. He is Life Senior Member, IEEE (00064352), and his biography is pub-lished by Marquis, USA, in their fourth edition, Who’s Who in Science &Engineering.

He retired as Assistant Professor in R V College of Engineering, Bengaluru.His earlier assignments were at Bharat Electronics and Radiall Protectron. Hisachievements in the industries include application of reliability techniques fordefense equipment, root cause analysis on electronic component failures, qualifi-cation testing of electronic components as per USA and Indian military standards,designing and implementing computerized quality management system, designingsoftware for optical interferometer, and design and manufacturing of lumped,semi-lumped, and microwave cavity filters using self-developed software.

He has authored three books, and the books are published by Springer. The firstbook, A Practical Design of Lumped, Semi-lumped and Microwave Cavity Filters,Springer, 2013, presents the design of L-C, tubular, and combline/iris-coupledcavity filters with examples.

The second book, Reliable Design of Electronic Equipment: An EngineeringGuide, Springer, 2015, presents the application of derating, FMEA, overstressanalysis, and reliability evaluation tests for designing reliable electronic equipment.

The third book, ISO 9001 Quality Management Systems, Springer, 2017, explainsthe requirements of ISO 9001 with examples from industries. Integrating QMSrequirements with ERP software is the most effective method of implementing thesystem in organizations. The methods of integrating QMS requirements with ERPsoftware are illustrated with examples. A chapter is dedicated for explaining theapplication of Indian classic, Thirukkural, for QMS planning.

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