Lecture 5. Sequential Logic 3
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Transcript of Lecture 5. Sequential Logic 3
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Lecture 5. Sequential Logic 3
Prof. Taeweon SuhComputer Science Education
Korea University
2010 R&E Computer System Education & Research
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Korea Univ
What Determines Clock Speed?
• What is the operating clock frequency of your computer? Why does the atom processor on your netbook run at 1.4GHz? Why does the Core 2 Duo on your notebook run at 2.0GHz? Why can’t run at 100GHz or 1000GHz? We are going to answer to this question today
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Synchronous Sequential Circuit
• As studied, virtually all the synchronous sequential circuits (including CPU) are composed of Flip-flops cascaded Combinational logic between flip-flops
• Pipeline is also implemented in this way• We are going to talk deep about this in computer
architecture class next semester
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R1 R2 R3
Q2D2 D3D1CL1 CL2
Q3
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Short Answer
• Suppose that the circuit does addition (+1) to the input (D1) CL1 does “+1” So, we want to get “D1+1” after 1 clock cycle
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R1 R2
Q2D2D1CL1
CL1 delay CL1 delay
If delay is longer than 1ns, the circuit can’t run at 1GHz
If delay is shorter than 1ns, the circuit can run at 1GHz
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A Little Long Answer
• Let’s talk a little deep about what contributes to the delay
• Consequently what determines the clock frequency of synchronous sequential circuit
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Timing
• Flip-flop samples D at the (rising) edge of the clock
• Input data in D must be stable when it is sampled Similar to a photograph, input data must be stable
around the clock edge If input data is changing when it is sampled,
metastability can occur
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Input Timing Constraints
• Setup time tsetup = time before the clock edge that data must be stable
• Hold time thold = time after the clock edge that data must be stable
• Aperture time ta = time around clock edge that data must be stable (tsetup +
thold)
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CLK
tsetup
D
thold
ta
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Output Timing of Flip-Flop
• Propagation delay tpcq = time after clock edge that the output Q is guaranteed to be
stable (i.e., to stop changing)
• Contamination delay tccq = time after clock edge that Q might be unstable (i.e., start
changing)
• Output timing is determined depending on how you implement flip-flop
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CLK
tccq
tpcq
tsetup
Q
D
thold
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Dynamic Discipline
• The input to a synchronous sequential circuit must be stable during the aperture (setup and hold) time around the clock edge.
• Specifically, the input must be stable at least tsetup before the clock edge
at least until thold after the clock edge
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Dynamic Discipline
• The delay between registers has a minimum and maximum delay, dependent on the delays of the circuit elements
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CL
CLKCLK
R1 R2
Q1 D2
(a)
CLK
Q1
D2
(b)
Tc
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Setup Time Constraint
• The setup time constraint depends on the maximum delay from register R1 through the combinational logic
• The input to register R2 must be stable at least tsetup before the clock edge
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CLK
Q1
D2
Tc
tpcq tpd tsetup
CL
CLKCLK
Q1 D2
R1 R2 Tc ≥ tpcq + tpd + tsetup
tpd ≤ Tc – (tpcq + tsetup)
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Hold Time Constraint
• The hold time constraint depends on the minimum delay from register R1 through the combinational logic
• The input to register R2 must be stable for at least thold after the clock edge
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CLK
Q1
D2
tccq tcd
thold
CL
CLKCLK
Q1 D2
R1 R2 tccq + tcd > thold
tcd > thold - tccq
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Timing Analysis Example
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CLK CLK
A
B
C
D
X'
Y'
X
Y
Timing Characteristics
tccq = 30 ps
tpcq = 50 ps
tsetup = 60 ps
thold = 70 ps
tpd = 35 ps
tcd = 25 ps
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Timing Analysis Example
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CLK CLK
A
B
C
D
X'
Y'
X
Y
per
gate
Setup time constraint:
tpd = 3 x 35 ps = 105 ps
Tc ≥ (50 + 105 + 60) ps = 215 ps
fc = 1/Tc = 4.65 GHz
Hold time constraint:
tccq + tcd > thold ?
(30 + 25) ps > 70 ps ? No!
Timing Characteristics
tccq = 30 ps
tpcq = 50 ps
tsetup = 60 ps
thold = 70 ps
tpd = 35 ps
tcd = 25 psTc ≥ tpcq + tpd + tsetup
tccq + tcd > thold
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Fixing Hold Time Violation
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Add buffers to the short paths:
Setup time constraint:
tpd = 3 x 35 ps = 105 ps
Tc ≥ (50 + 105 + 60) ps = 215 ps
fc = 1/Tc = 4.65 GHz
Tc ≥ tpcq + tpd + tsetup
per
gate
Timing Characteristics
tccq = 30 ps
tpcq = 50 ps
tsetup = 60 ps
thold = 70 ps
tpd = 35 ps
tcd = 25 ps
tccq + tcd > thold
Hold time constraint:
tccq + tcd > thold ?
(30 + 50) ps > 70 ps ? Yes!
CLK CLK
A
B
C
D
X'
Y'
X
Y