Lecture #2 Page 1 ECE 4110– Sequential Logic Design Lecture #2 Agenda 1.Logic Design Tools...
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Transcript of Lecture #2 Page 1 ECE 4110– Sequential Logic Design Lecture #2 Agenda 1.Logic Design Tools...
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Lecture #2Page 1
ECE 4110– Sequential Logic Design
Lecture #2
• Agenda
1. Logic Design Tools
• Announcements
1. n/a
![Page 2: Lecture #2 Page 1 ECE 4110– Sequential Logic Design Lecture #2 Agenda 1.Logic Design Tools Announcements 1.n/a.](https://reader036.fdocuments.in/reader036/viewer/2022070401/56649f1a5503460f94c2fde6/html5/thumbnails/2.jpg)
Lecture #2Page 2
Logic Design Tools
• MS Visio
- a generic drawing program.- industry is converging on this program for documentation.- has built in shape libraries, including analog/digital logic.- we’ll use it for this class to create clean schematics.
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Lecture #2Page 3
Logic Design Tools
• MS Visio
Predefined Shapes
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Lecture #2Page 4
Logic Design Tools
• ModelSim (by Mentor Graphics)
- an HDL Simulation (VHDL and Verilog)- widely used in industry- has color-coded text editing for keywords- has console for verification reporting- we’ll use for homework & before FPGA synthesis.
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Lecture #2Page 5
Logic Design Tools
• ModelSim Simulation Waveform
ProjectNavigator
Console
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Lecture #2Page 6
Logic Design Tools
• ModelSim Text Editor
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Lecture #2Page 7
Logic Design Tools
• Xilinx ISE
- Integrated Software Environment (ISE)- Implementation tool - compile / simulate- synthesis- technology mapping- place and route- back annotation for post-route simulation and timing verification- can do similar simulation as in ModelSim
- this is where we :
- select FPGA to target - assign signal pins - set timing constraints - set placement constraints - set routing constraints - generate programming file - download file to FPGA, EEprom, or CPLD using the JTAG interface.
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Lecture #2Page 8
Logic Design Tools
• Xilinx ISE
SourcesWindow
ProcessesWindow
Edit/ViewWindow
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Lecture #2Page 9
Logic Design Tools
• Xilinx ISE
ResourceUsage
Pin Assignments
PackageView
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Lecture #2Page 10
Logic Design Tools
• Xilinx ISE
HDL or Schematic
Entry
RoutingEditor
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Altera Quartus II Development Tool
Lecture #2Page 11
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Example of File Menu
Lecture #2Page 12
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New Project Wizard
Lecture #2Page 13
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Creation of new project
Lecture #2Page 14
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Adding files to project
Lecture #2Page 15
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Choose device family and specific device
Lecture #2Page 16
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Electronic Design Automation Tools
Lecture #2Page 17
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Summary of project settings
Lecture #2Page 18
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Quartus II display of created project
Lecture #2Page 19
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Processing>Start Compilation
Lecture #2Page 20
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Assignment > Pins
For example, SW0,SW1 are connected on FPGA Pins N25,N26. LEDG0 is pin AE22.
Lecture #2Page 21
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Available pins
Lecture #2Page 22
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Programming the FPGA:Tools>Programmer
•Check the Program/Configure box, then click Start. •Wait till the progress bar show 100% (done).
Lecture #2Page 23