Lecture 22 – Reducing Leakage Borivoje...
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inst.eecs.berkeley.edu/~ee241b Borivoje Nikolić EE241B : Advanced Digital Circuits Lecture 22 – Reducing Leakage 1 EECS241B L22 LEAKAGE Sweetfarm.org/goat-2-meeting: Invite a goat or a llama to a zoom meeting https://www.sweetfarm.org/goat-2-meeting
Transcript of Lecture 22 – Reducing Leakage Borivoje...
inst.eecs.berkeley.edu/~ee241b
Borivoje Nikolić
EE241B : Advanced Digital Circuits
Lecture 22 – Reducing Leakage
1EECS241B L22 LEAKAGE
Sweetfarm.org/goat-2-meeting: Invite a goat or a llama to a zoom meeting
https://www.sweetfarm.org/goat-2-meeting
Announcements
• Assignment 4 due next Friday.
• Reading• Rabaey, LPDE, Chapter 8
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Outline
• Module 5• Clock gating
• Leakage reduction during design time and runtime
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5.G Reducing Switching Activity Through Logic Design
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Power /Energy Optimization Space
Constant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run Time
Active
Logic designScaled VDD
Trans. sizingMulti-VDD
Clock gatingDFS, DVS
Leakage
Stack effectsTrans sizingScaling VDD
+ Multi-VTh
Sleep T’sMulti-VDD Variable VTh
+ Input control+ Variable VTh
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Basic Idea
• E ~ αCV2
• Reduce switching activity, α, through logic and architectural transformations
• Many options• Switching activity lower with deeper logic
• Pipelining has significant effect
• Reduce the number of clocked devices in a flip-flop
• e.g. group generation of clk_b
• A few logic ideas follow
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Circuit-Level Activity Encoding
Conditional InversionCoding for Interconnect
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Number Representation
• Input signals are noise most of the time
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5.H Clock Gating
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Power /Energy Optimization Space
Constant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run Time
Active
Logic designScaled VDD
Trans. sizingMulti-VDD
Clock gatingDFS, DVS
Leakage
Stack effectsTrans sizingScaling VDD
+ Multi-VTh
Sleep T’sMulti-VDD Variable VTh
+ Input control
DVS,Variable VTh
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Clock Gating
Requires a bit more complex gate ...Well handled in today’s EDA tools
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Clock Gating
• Enabling clock needs to be synchronized
Clk
En
Gated Clk
Sequential cell
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DSP/HIF
DEU
MIF
VDE
896Kb SRAM
10
8.5mW
0 155
30.6mW
20 25
Without clock gating
With clock gating
Power [mW]
Clock Gating Efficiently Reduces Power
Courtesy M. Ohashi, Matsushita, ISSCC 2002
90% of F/F’s were clock-gated.
70% power reduction by clock-gating alone.
MPEG4 decoder
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Clock Gating
ARM Cortex-A9 Technical Reference Manual:
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Local Clock Gating
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Local Clock Gating
D
QCKI
CKIB
0.85 0.85
2
0.850.5 0.5
0.5
1.2
CP
0.50.85 0.50.85
XNOR
CKIB
CKI
CKIB 0.5
0.5
0.85
0.5
PulseGenerator
Data-TransitionLook-Ahead
DI
‘Clock on demand’Flip-flop
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Complex Designs
Fischer, ISSCC’05EECS241B L22 LEAKAGE 17
Power /Energy Optimization Space
Constant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run Time
Active
Logic designScaled VDD
Trans. sizingMulti-VDD
Clock gatingDFS, DVS
Leakage
Stack effectsTrans sizingScaling VDD
+ Multi-VTh
Sleep T’sMulti-VDD Variable VTh
+ Input control
DVS,Variable VTh
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Plan For the Rest of the Semester
• 4 more lectures (including today’s):• Finish low power (2 lectures)
• Supplies, clocks and their interaction
• Homework 4 due on April 24th
• Quiz 4 on April 28th
• Final on April 30th
• 80 minutes, open everything
• Final presentations, May 4• Final reports due on May 4
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5.I Lowering Leakage During Design: Multiple Thresholds
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Power /Energy Optimization Space
Constant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run Time
Active
Logic designScaled VDD
Trans. sizingMulti-VDD
Clock gatingDFS, DVS
Leakage
Stack effectsTrans sizingScaling VDD
+ Multi-VTh
Sleep T’sMulti-VDD
Variable VTh
+ Input control
DVS,Variable VTh
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Technology Options
• Multiple thresholds, each spaced 50-100mV apart (5-10x less leakage)
180 130 90 65 45Technology [nm]
Ion, HS, LP
Ioff,HP
Ioff,LP
Ig,LP
Ig,HP
HP
LP (LOP)
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Using Multiple Thresholds
Yano, SSTCW’00EECS241B L22 LEAKAGE 23
Typical Technologies
• 2-3 Thresholds • To choose from 4-6 in a node
• In bulk and finfet, but not in FDSOI (unless doped)
• Threshold voltage diff ~5-10x in leakage
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5.I Lowering Leakage During Design: Longer Channels
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Power /Energy Optimization Space
Constant Throughput/Latency Variable Throughput/Latency
Energy Design Time Sleep Mode Run Time
Active
Logic designScaled VDD
Trans. sizingMulti-VDD
Clock gatingDFS, DVS
Leakage
Stack effectsTrans sizingScaling VDD
+ Multi-VTh
Sleep T’sMulti-VDD
Variable VTh
+ Input control
DVS,Variable VTh
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Longer Channels
0
1
2
3
4
5
6
7
8
0.1 0.15 0.2 0.25 0.3Gate Length [um]
Leak
age
Cur
rent
[nA
]
Switching energy
Leakage Current35%
10%
Lnom
•10% longer gates reduce leakage by 35% (in 130nm)• Increases switching energy by 21% with W/L = const.
•Attractive when don’t have to increase W (memory)•Doubling L reduces leakage by 3x (in 0.13um)•Much stronger effect in 28nm!•Effect improves with shorter channel devices
W/L = const.
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Poly Bias
• 28FDSOI example
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Longer Channels
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