Layout and stick diagram
Transcript of Layout and stick diagram
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Jhon P. U
CMOS Layers
n-well process p-well process Twin-tub process
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n-well process
p-substrate
n+ n+ n+ n+ p+ p+ p+ p+
n-well
Gate NMOS NMOS PMOS PMOS
FOX
MOSFET Layers in an n-well process
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Layer Types
p-substrate n-well n+ p+ Gate oxide Gate (polycilicon) Field Oxide
Insulated glass Provide electrical isolation
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Top view of the FET pattern
n+ n+ n+ n+ p+ p+ p+ p+
NMOS NMOS PMOS PMOS
n-well
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Metal Interconnect Layers
Metal layers are electrically isolated from each other
Electrical contact between adjacent conducting layers requires contact cuts and vias
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Metal Interconnect Layers
p-substrate
n+ n+ n+ n+
Via
Activecontact
Ox3
Metal2
Metal1
Ox2
Ox1
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Interconnect Layout Example
Metal2
Metal1
Metal1
Active contact
Gate contact
MOS
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Designing MOS ArraysA B C
yx
y
x
A B C
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Parallel Connected MOS Patterning
x
y
A B
X X X
A B
x
y
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Alternate Layout Strategy
A B
x
y
X X
X X
x
A B
y
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Basic Gate Design
Both the power supply and ground are routed using the Metal layer
n+ and p+ regions are denoted using the same fill pattern. The only difference is the n-well
Contacts are needed from Metal to n+ or p+
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The CMOS NOT Gate
X
X
X
X
Vp
Gnd
x
Gnd
n-well
Vp
x xx
Contact Cut
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Alternate Layout of NOT Gate
Gnd
Vp
x
x
X
x
Vp
Gnd
X
x
X
X
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NAND2 Layout
Gnd
Vp
ba.
a b
X
Vp
Gnd
X X
X X
a b
ba.
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NOR2 Layout
Gnd
Vp
ba
a bX
Vp
Gnd
X X
X X
a b
ba
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NAND2-NOR2 Comparison
X
Vp
Gnd
X X
XX
XX
X
XX
Vp
Gnd
MOS Layout Wiring
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General Layout Geometry
IndividualTransistors
Shared Gates
Shared drain/source
Vp
Gnd
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Graph Theory: Euler PathVp
Gnd
a
c
b
b
a
c
Out
x
y
x
y
Vertex
Edge
Vertex
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Stick Diagram
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Stick Diagrams
• Cartoon of a layout.
• Shows all components.
• Does not show exact placement, transistor sizes, wire lengths, wire widths, boundaries, or any other form of compliance with layout or design rules.
• Useful for interconnect visualization, preliminary layout layout compaction, power/ground routing, etc.
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Stick Diagrams
Metal
poly
ndiff
pdiffCan also drawin shades of
gray/line style.
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Stick Diagrams
Buried Contact
Contact Cut
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5 V
Dep
Vout
Enh
0V
Vin
5 v
0 V
Vin
5 v
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Stick Diagram - Example I
NOR Gate
OUT
B
A
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Stick Diagram - Example II
Power
Ground
B
C
OutA
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Points to Ponder
• be creative with layouts
• sketch designs first
• minimize junctions but avoid long poly runs
• have a floor plan plan for input, output, power and ground locations
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The End