LayeredTrees : Most Specific Prefix based Pipelined Design for On-Chip IP Address Lookups

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LayeredTrees: Most Specific Prefix based Pipelined Design for On-Chip IP Address Lookups Author: Yeim-Kuau Chang, Fang-Chen Kuo, Han-Jhen Guo and Cheng-Chien Su Publisher: Presenter: Yu Hao, Tseng Date: 2013/03/20 1

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LayeredTrees : Most Specific Prefix based Pipelined Design for On-Chip IP Address Lookups . Author : Yeim-Kuau Chang, Fang-Chen Kuo , Han- Jhen Guo and Cheng- Chien Su Publisher : Presenter: Yu Hao , Tseng Date: 2013/03/20. Outline. Introduction Data Structure - PowerPoint PPT Presentation

Transcript of LayeredTrees : Most Specific Prefix based Pipelined Design for On-Chip IP Address Lookups

Page 1: LayeredTrees : Most Specific Prefix based Pipelined Design for On-Chip IP Address Lookups

LayeredTrees: Most Specific Prefix based Pipelined Design for On-Chip IP Address Lookups Author: Yeim-Kuau Chang, Fang-Chen Kuo, Han-Jhen Guo and Cheng-Chien SuPublisher: Presenter: Yu Hao, TsengDate: 2013/03/20

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Outline• Introduction• Data Structure• Proposed Pipelined Architecture• Performance• Conclusions

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Introduction• In this paper, we shall propose a high-speed pipelined

architecture called LayeredTrees. It uses layer-based prefix partitioning scheme to construct the multiway B-tree data structure. We will show that, other than trie and range based data structure, LayeredTrees can achieve a throughput of 120 Gbps that is even higher than the best multibit-trie-based implementation nowadays.

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Data Structure• LayeredTrees is proposed for dynamic routing tables.• In LayeredTrees, the prefixes in a routing table are grouped

into layers based the concept of the most specific prefixes proposed in our previous work [8].

• The prefixes in each layer are organized as a B-tree because the goal of LayeredTrees is to store the entire routing table in the on-chip memory of FPGA device currently available.

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Data Structure (Cont.)

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Data Structure (Cont.)• Two problems when the B-tree is used to organize the prefixes

in each layer• The utilization of the B-tree nodes is only about 50 percent.• The pointers used for the branches of a B-tree node consume a

large amount of memory.

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Data Structure (Cont.)• Two commonly used formats• Example : 101***

• mask format : 101000/111000• length format : 101000/3

• Lite Prefix Format• The prefix of length i, , is represented as , where for to , , and for

to , (i.e., is followed by a zero and consecutive ones).• For a prefix in the lite prefix format, its mask denoted by can be

easily recovered by the logical equations , .• Example : 1011**

• Lite Prefix Format : 1011011• Mask : 111100

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Data Structure (Cont.)• For the routing table consisting of 300K prefixes, the memory

required for storing the prefixes in a linear array based on the lite prefix format is 9.9 Mbits while mask format and length format need 19.2 and 11.4 Mbits, respectively.

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Data Structure (Cont.)• LayeredTrees Search

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Data Structure (Cont.)• LayeredTrees Insert

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Data Structure (Cont.)• LayeredTrees Delete

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Data Structure (Cont.)• Controlled B-tree Building Algorithm (CBA)• CBA inserts prefixes in an increasing order of their prefix values

and splits at the position of the last key, instead of the middle key of the node when the B-tree node is full.

• According to our analysis, CBA can improve the utilization of B-tree node to 90 percent.

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Data Structure (Cont.)• Aggregate array and Segmentation table• Only one pointer called base address is needed in a B-tree node,

instead of m branch pointers.• Using a segmentation table [20] is always the simplest way to

partition a tree into several smaller ones without complicating the search operations.

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Data Structure (Cont.)• Varying segmentation table and node sizes• The segmentation table size denoted by s and B-tree node size

denoted by m are two main factors effecting the memory consumption of the proposed LayeredTree.

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Proposed Pipelined Architecture

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Proposed Pipelined Architecture (Cont.)

• Leveled Search Engine (LSE)

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Proposed Pipelined Architecture (Cont.)

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Proposed Pipelined Architecture (Cont.)

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Performance

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Conclusions• The proposed Leveled Search Engine (LSE) is a 5-stage

pipeline and the parallel LSE uses 17-stage pipelines. The performance experiments on the chip XC6VSX315T of Virtex-6 FPGA family show that achieved throughput by parallel LSE is superior compared to the existing designs.

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