VERIFICATION OF BOOLEAN THEOREM

AIM:To verify Boolean theorems using AND, OR and NOT gate and to verify its truth table.

APPARATUS REQUIRED:1. IC 7404 12. IC 7408 13. IC 7432 14. Trainer kit 15. Wires as required

THEORY:DEMORGANS THEOREM:Theorem:1

It status that the complement of a product is equal to the sum of the complement that is the variable are A+B, then AB=A+B.

Theorem:2It states that the complement of the sum is equal to the product of complement. In equation from this can write as A+B=A.B

Commutative law:According to this law, the order of the OR gate operation conducted on variable makes no difference A+B=B+A, similary for multiplication A.B+B.A. Is the order of AND operation conducted on variable makes no difference.

Associative law:The OR & AND operation of several variable result i9n same regardless of the grouping of the variables that is for addition.

A+ (B+C) = (A+B) + CA. (B.C) = (A.B). C

Distributive law:It states that the AND operation of several variable of then the AND operation of the same.

A+ (B.C) = (A+B) (A+C)

Procedure:Connection is given as per the logic operation.Give variables state to i/p, verify truth table.The same procedure is repeated for all logic operation.

Result:Thus the Boolean theorem using AND, OR & NOT gate are verified.

HALF ADDER, FULL ADDER AND PARALLEL ADDER

Aim:To construct and design a half adder and full adder and parallel adder

circuits using logic gates & verify its truth table.

Apparatus Required:1. IC 7486 12. IC 7408 13. IC 7483 14. Trainer kit 15. Connecting wires as required.

Theory:Half adder:

A basic module used in binary arithmetic elements is the hale adder. The function of half adder is adding two binary digits, producing a sum and carry. There are two inputs to the half adder designed sum and carry. The half adder performs binary addition operation for two binary inputs. This is art6hmetic addition not logical and Boolean additions. The relationship can be written as,

Sum = A+BCarry = AB

Full adder:A full adder is a combinational circuit that forms the arithmetic sum

of three inputs bits. It consists of these inputs A and B, represented the carry from the previous lower significant position. The relationship can be written as,

Sum = Cin + (A+B)Carry = AB + ACin + BCin

Procedure:Connect the components as per the given circuit.Apply the bits as per the truth table.Check for the output as given i9n the characteristics table by the

glowing of LED.Give the conclusion.

Result:Thus the half adder, full adder and parallel adder circuit are designed and constructed using logic gates and the truth table is also verified.

HALF SUBTRACTOR, FULL SUBTRCTOR AND PARALLEL SUBTRACTOR

Aim:To construct and design a half sub tractor, full sub tractor and parallel

sub tractor circuits using logic gates and verify the truth table.

Apparatus required:1. IC 7486 12. IC 7404 13. IC 7432 14. IC 7408 15. Trainer kit 16. Connecting wires as required

Theory:Half subtractor:

A half sub tractor is a combinational circuits that subtracts two bits and produces their difference it also has an output to specify if a has been borrowed. Let us designate minuend bits as A and the subtrahends bit as B.To perform the A-B we have to check the relative magnitude of A & B. then the result is called difference bit. The half sub tractor needs two output. One output generates the difference and designed by D. the second output de3signated B for borrow generates the binary signal that uniform the next stage that a 1 has been borrowed.

Difference = A+BBorrow = AB

Full subtractor:A full sub tractor is a combination circuit that performs subtraction

between two bits taking into account borrow of lower significance stage. This circuit has 3 i/p’ s and 2 o/p ‘s. then three inputs are A&B and binary denoted the minuend, subtract and previous borrow respectively.

Difference = Bin + A+ BBorrow = AB + ABin + BBin

Parallel subtractor:The subtraction of binary numbers can be done most conveniently by

means of complements, discussed remember that the subtraction A-B can be done by taking the 2’s complement. The two’s complement is added.

Procedure:Connect the components as per the circuit diagram.Apply the bits as per truth tableCheck the output as per in the truth tableGive the conclusion.

Result:Thus the half subtractor,full subtractor and parallel subtractor circuits

are designed and constructed using logic gates and the truth tables are verified.

4- BIT ADDER / SUBTRACTOR

Aim:To design and setup an 4-bit binary adder and subtractor and to verify

the truth table.

Apparatus required:1. IC 7483 12. IC 7486 13. Trainer kit 14. Connecting wire as required

Theory:The subtraction of two numbers of two numbers can be done by

making the 2’s complement of the subtrahend and adding it to the minuend. The 2’s can be obtained by taking 1’s complement and adding 1. to perform A-B, we complement the four bits of B and then to the four bit of A and add 1 through the input carry. The four XOR gate complement the bits of B when the mode M=1 and leave the bits of B un changed, when M=0. thus the mode select ‘M’ is equal to L, the input carry is equal to 1, and the sum output is A plus the 2;s complement of B, when M is equal to 0, the input carry is equal to 0 and the sum generator A+b. during the addition, the output carry is equal to 1 when the sum exceeds 15 also when A>B the subtraction operation gives the correct answer.

But when A<B, the subtraction gives the 2’s complement of B-A and the output carry is equal to ‘0’.

Procedure:Give the connections as per the circuit diagram.Check the IC’s before usingApply input as per the truth tableVerify the inputs and output, hence truth table.

Result:Thus the 4-bit binary adder and subtractor using IC’s circuit is

constructed and designed and also truth table is verified.

MAGNITUDE COMPRATOR

Aim:To construct a magnitude comparator using the different logic gates

and also verify the truth table.

Apparatus required:1. IC 7404 12. IC 7400 13. IC 7408 14. IC 7402 15. IC – Trainer kit 16. Connecting wire as required

Theory:A magnitude comparator is a special combinational circuit designed

primarily to compare the relative magnitude of two binary numbers.If the two given number that is signal bit ‘A’ and ‘B’ then, A’B is high, it indicates A is less than B (A<B) A.B is high, it indicates A is equal to B (A=B) AB’ is high it indicates A is greater than B A>B.

Procedure: connect the component as per circuit diagram

Apply the bits as per the truth table.Check for the output as given in the characteristics table by glowing

the LCD.Give the conclusions.

Result:Thus the magnitude comparator using different logic gates are

constructed and their truth table is verified.

CODE CONVERTORS

Aim:To design the following code converters and verify their truth table.

A) binary to gray codeB) Gray to binary code.

Apparatus required:1. IC 7486 12. IC- Trainer kit 13. Connecting wires as required

Theory:Code converters:

Code converter is a combinational circuit which is used to connect the two systems with different inputs and the outputs.

Eg: a) binary to gray codeb) Gray to binary code

Binary to gray code:The MSB in the gray code is same as the corresponding MSB in the

binary number.Going from left to right, perform an EX-OR operations between this

adjacent pairs of binary code bits to get their next gray code.

Gray to binary code:The MSB in the binary code is same as the corresponding bit in the

gray code.To obtain the next binary bit, performs an EX-OR operation between

the bit just written down and this next gray code bit.

Procedure:Give the connections as per the circuit diagramApply the input as per the circuit diagram and truth tableCheck for the output by glowing of the LCD.

Result:Thus the code converters using different logic gates are constructed and their truth tables are verified.

PARITY GENERATOR AND CHECKER

Aim:To construct a logic circuit to perform a 4-bit word parity generator

and checker and to verify its truth table.

Apparatus required:1. IC 7486 12. IC 7400 13. IC-Trainer kit 14. Wires as required

Theory:A parity bit is used for the purpose detecting errors during

transmission of binary information. The circuit that generates the parity bit in the transmitter is called parity generator and the circuits that checks the parity in the receiver is called parity checker. In even parity the added parity bit will make the total number of 1’s an even amount. In odd parity the added parity bit will make total number of 1’s an odd amount. The parity checker circuit in transmission since the information was transmitted with even parity the four bits are received must have an even number of 1’s. an error occurs during the transmission of four bits received have an odd number of 1’s.

Procedure:Give the connections as per the circuit diagram.If the number of odd is high, odd parity is givenIf the number of even is high, even parity is givenFor input given, the outputs are verified and truth table is verified.

Result:Thus the parity generator and is constructed and verified by using IC

74180 successfully.

MULTIPLEXER

Aim:To design and construct multiplexer using logic gates.

Apparatus required:

1. IC 74150 12. IC-Trainer kit 13. Connecting wires as required

Theory:Multiplexer is a digital switch, it allows digital information from

several sources to be routed onto a input lines and a single output line. The selection of a particular i/p line is controlled by a set of selection lines. Normally there are 2^n input lines and n selection lines whose bit combinations determine which input is selected. Therefore multiplexer is many into one and it provides the digital equivalent of an analog selector switch. Each of four lines D0 to D3 is applied to one input of an AND gate.

Procedure:Give the connections as per the diagramApply bits as per truth tableCheck the output as per given in the table by glowing in the LEDGive the conclusion.

Result:

Thus the multiplexer using IC 74150 is studied and their truth is verified.

SHIFT REGISTER

Aim:To construct and verify the following shift register

1) serial in serial out register2) serial in parallel out shift register3) parallel in parallel out shift register4) parallel in serial out shift register

Apparatus required:1. IC 7474 12. IC- Trainer kit 13. Connecting wires as required

Theory:Shift register:

The binary information in a register in a register in a register can be resolved from stage to stage with in the register or into or out of the register upon application of clock –pulse. This type of bit movement is essential for certain arithmetic and logic operation in the microprocessor. This give rise to a group of register called as the shift register.

Serial in serial out shift register:In the case the data bits are entered into register in the serial manner.

The output is taken in the serial way.

Serial in parallel out shift register:In this case data bits are entered into register in parallel manner. The

output is taken as in the parallel manner once the date is stored, each bit appear on its respective output line and are bits are available.

Parallel in serial out shift register:I9n the type the bits are entered in parallel way simultaneously and the

output is taken in serial way.

Parallel in parallel out shift register:In this type, there is a simultaneous entry of all data bits and the bits appear at parallel output.

Procedure:Connect the circuit as per the circuit diagram.The clock pulse is given and it is checked for the bit shift.Check the output from the given truth table by giving clock pulse.

Result:Thus the following shift register are constructed and their truth table

are verified.1) Serial in serial out shift register.2) Serial in parallel out shift register3) Parallel in serial out shift register.4) Parallel in parallel out shift register.

3-BIT SYNCHRONOUS COUNTER

Aim:To design and construct the 3-bit synchronous counter and to verify

the truth table.

Apparatus required:1. IC 7476 2 2. IC 7408 23. Connecting wires -

Theory:In a ripple counter, the flip-flop output transition server as a source for

triggering other flip flops. In other words, the clock pulse inputs of all flip-flops (except the first) are triggered not by the incoming pulse, but rather by the transition that occurs in other flip-flop. In a synchronous counter, the input pulses are applied to all clock pulse all flip flops. The change of state of other flip-flops. Synchronous MSI counters are discussed in the next section. Here we present some common discussed MSI ripple counter and explain there operation. A binary ripple counter consists of a serious pf complementing flip=flops, with the output of each flip-flop connected to the clock input of the next of the next higher. Order flip-flop. The flip flop holding the least significant bit receiver the incoming count pluses. All J&K inputs are equal to 1.

Procedure:Connect the components as per diagram.Apply the bits as per truth table.Check the o/p as per given in the table by glowing the LED.Give the conclusion.

Result:Hence the 3-bit synchronous was designed was designed constructs

and the truth table was verified.

3-BIT ASYNCHRONOUS COUNTER

Aim:To construct and test the performance of 3-bit asynchronous ripple

counter.

Apparatus required:1. IC 7476 22. IC 7400 13. Trainer kit 14. Connecting wires -

Theory:A binary ripple counter of a serious connection of complementing flip

flop, with the o/p of each flip flop connected to check the input of the next higher order flip flop. This holding the least significant bit receivers the incoming clock pulses. A complementing can be contained from a JK flip flop with complementing o/p connected to the D input. In this copy the D i/p is always the complement o/p of the present state and the next state clock pulses wire cause the flip flop to complement.

Procedure:Connect the components as per the diagram.Apply the bits as per the truth table.Check the output as per given in the table, by the glowing of LED.Give the conclusion.

Result:Thus the 3-bit asynchronous counter was designed, constructed and its

truth table was verified.